mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
Merge git://www.denx.de/git/u-boot-marvell
This commit is contained in:
commit
7e10a7c3bc
@ -115,7 +115,7 @@ config KIRKWOOD
|
|||||||
select CPU_ARM926EJS
|
select CPU_ARM926EJS
|
||||||
|
|
||||||
config ARCH_MVEBU
|
config ARCH_MVEBU
|
||||||
bool "Marvell MVEBU family (Armada XP/38x)"
|
bool "Marvell MVEBU family (Armada XP/375/38x)"
|
||||||
select CPU_V7
|
select CPU_V7
|
||||||
select SUPPORT_SPL
|
select SUPPORT_SPL
|
||||||
select OF_CONTROL
|
select OF_CONTROL
|
||||||
|
@ -49,6 +49,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
|
|||||||
tegra210-p2571.dtb
|
tegra210-p2571.dtb
|
||||||
|
|
||||||
dtb-$(CONFIG_ARCH_MVEBU) += \
|
dtb-$(CONFIG_ARCH_MVEBU) += \
|
||||||
|
armada-375-db.dtb \
|
||||||
armada-388-clearfog.dtb \
|
armada-388-clearfog.dtb \
|
||||||
armada-388-gp.dtb \
|
armada-388-gp.dtb \
|
||||||
armada-xp-gp.dtb \
|
armada-xp-gp.dtb \
|
||||||
|
216
arch/arm/dts/armada-375-db.dts
Normal file
216
arch/arm/dts/armada-375-db.dts
Normal file
@ -0,0 +1,216 @@
|
|||||||
|
/*
|
||||||
|
* Device Tree file for Marvell Armada 375 evaluation board
|
||||||
|
* (DB-88F6720)
|
||||||
|
*
|
||||||
|
* Copyright (C) 2014 Marvell
|
||||||
|
*
|
||||||
|
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||||
|
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||||
|
*
|
||||||
|
* This file is dual-licensed: you can use it either under the terms
|
||||||
|
* of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
* licensing only applies to this file, and not this project as a
|
||||||
|
* whole.
|
||||||
|
*
|
||||||
|
* a) This file is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of the
|
||||||
|
* License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This file is distributed in the hope that it will be useful
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* Or, alternatively
|
||||||
|
*
|
||||||
|
* b) Permission is hereby granted, free of charge, to any person
|
||||||
|
* obtaining a copy of this software and associated documentation
|
||||||
|
* files (the "Software"), to deal in the Software without
|
||||||
|
* restriction, including without limitation the rights to use
|
||||||
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
* sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following
|
||||||
|
* conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be
|
||||||
|
* included in all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||||
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
#include "armada-375.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Marvell Armada 375 Development Board";
|
||||||
|
compatible = "marvell,a375-db", "marvell,armada375";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
/* So that mvebu u-boot can update the MAC addresses */
|
||||||
|
ethernet0 = ð0;
|
||||||
|
ethernet1 = ð1;
|
||||||
|
spi0 = &spi0;
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x40000000>; /* 1 GB */
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||||
|
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||||
|
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
|
||||||
|
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
|
||||||
|
|
||||||
|
internal-regs {
|
||||||
|
spi@10600 {
|
||||||
|
pinctrl-0 = <&spi0_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
/*
|
||||||
|
* SPI conflicts with NAND, so we disable it
|
||||||
|
* here, and select NAND as the enabled device
|
||||||
|
* by default.
|
||||||
|
*/
|
||||||
|
status = "okay";
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
|
||||||
|
spi-flash@0 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "n25q128a13", "jedec,spi-nor";
|
||||||
|
reg = <0>; /* Chip select 0 */
|
||||||
|
spi-max-frequency = <108000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@11000 {
|
||||||
|
status = "okay";
|
||||||
|
clock-frequency = <100000>;
|
||||||
|
pinctrl-0 = <&i2c0_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@11100 {
|
||||||
|
status = "okay";
|
||||||
|
clock-frequency = <100000>;
|
||||||
|
pinctrl-0 = <&i2c1_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@12000 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl {
|
||||||
|
sdio_st_pins: sdio-st-pins {
|
||||||
|
marvell,pins = "mpp44", "mpp45";
|
||||||
|
marvell,function = "gpio";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sata@a0000 {
|
||||||
|
status = "okay";
|
||||||
|
nr-ports = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
nand: nand@d0000 {
|
||||||
|
pinctrl-0 = <&nand_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
num-cs = <1>;
|
||||||
|
marvell,nand-keep-config;
|
||||||
|
marvell,nand-enable-arbiter;
|
||||||
|
nand-on-flash-bbt;
|
||||||
|
nand-ecc-strength = <4>;
|
||||||
|
nand-ecc-step-size = <512>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "U-Boot";
|
||||||
|
reg = <0 0x800000>;
|
||||||
|
};
|
||||||
|
partition@800000 {
|
||||||
|
label = "Linux";
|
||||||
|
reg = <0x800000 0x800000>;
|
||||||
|
};
|
||||||
|
partition@1000000 {
|
||||||
|
label = "Filesystem";
|
||||||
|
reg = <0x1000000 0x3f000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@54000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
usb3@58000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
mvsdio@d4000 {
|
||||||
|
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||||
|
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio {
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ethernet@f0000 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
eth0@c4000 {
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy0>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
};
|
||||||
|
|
||||||
|
eth1@c5000 {
|
||||||
|
status = "okay";
|
||||||
|
phy = <&phy3>;
|
||||||
|
phy-mode = "gmii";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie-controller {
|
||||||
|
status = "okay";
|
||||||
|
/*
|
||||||
|
* The two PCIe units are accessible through
|
||||||
|
* standard PCIe slots on the board.
|
||||||
|
*/
|
||||||
|
pcie@1,0 {
|
||||||
|
/* Port 0, Lane 0 */
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
pcie@2,0 {
|
||||||
|
/* Port 1, Lane 0 */
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
658
arch/arm/dts/armada-375.dtsi
Normal file
658
arch/arm/dts/armada-375.dtsi
Normal file
@ -0,0 +1,658 @@
|
|||||||
|
/*
|
||||||
|
* Device Tree Include file for Marvell Armada 375 family SoC
|
||||||
|
*
|
||||||
|
* Copyright (C) 2014 Marvell
|
||||||
|
*
|
||||||
|
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||||
|
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||||
|
*
|
||||||
|
* This file is dual-licensed: you can use it either under the terms
|
||||||
|
* of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
* licensing only applies to this file, and not this project as a
|
||||||
|
* whole.
|
||||||
|
*
|
||||||
|
* a) This file is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of the
|
||||||
|
* License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This file is distributed in the hope that it will be useful
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* Or, alternatively
|
||||||
|
*
|
||||||
|
* b) Permission is hereby granted, free of charge, to any person
|
||||||
|
* obtaining a copy of this software and associated documentation
|
||||||
|
* files (the "Software"), to deal in the Software without
|
||||||
|
* restriction, including without limitation the rights to use
|
||||||
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
* sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following
|
||||||
|
* conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be
|
||||||
|
* included in all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||||
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "skeleton.dtsi"
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
#include <dt-bindings/phy/phy.h>
|
||||||
|
|
||||||
|
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Marvell Armada 375 family SoC";
|
||||||
|
compatible = "marvell,armada375";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
gpio0 = &gpio0;
|
||||||
|
gpio1 = &gpio1;
|
||||||
|
gpio2 = &gpio2;
|
||||||
|
serial0 = &uart0;
|
||||||
|
serial1 = &uart1;
|
||||||
|
};
|
||||||
|
|
||||||
|
clocks {
|
||||||
|
/* 2 GHz fixed main PLL */
|
||||||
|
mainpll: mainpll {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <1000000000>;
|
||||||
|
};
|
||||||
|
/* 25 MHz reference crystal */
|
||||||
|
refclk: oscillator {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
enable-method = "marvell,armada-375-smp";
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pmu {
|
||||||
|
compatible = "arm,cortex-a9-pmu";
|
||||||
|
interrupts-extended = <&mpic 3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "marvell,armada375-mbus", "simple-bus";
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
controller = <&mbusc>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
pcie-mem-aperture = <0xe0000000 0x8000000>;
|
||||||
|
pcie-io-aperture = <0xe8000000 0x100000>;
|
||||||
|
|
||||||
|
bootrom {
|
||||||
|
compatible = "marvell,bootrom";
|
||||||
|
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
devbus-bootcs {
|
||||||
|
compatible = "marvell,mvebu-devbus";
|
||||||
|
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||||
|
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
devbus-cs0 {
|
||||||
|
compatible = "marvell,mvebu-devbus";
|
||||||
|
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||||
|
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
devbus-cs1 {
|
||||||
|
compatible = "marvell,mvebu-devbus";
|
||||||
|
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||||
|
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
devbus-cs2 {
|
||||||
|
compatible = "marvell,mvebu-devbus";
|
||||||
|
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||||
|
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
devbus-cs3 {
|
||||||
|
compatible = "marvell,mvebu-devbus";
|
||||||
|
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||||
|
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
internal-regs {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||||
|
|
||||||
|
L2: cache-controller@8000 {
|
||||||
|
compatible = "arm,pl310-cache";
|
||||||
|
reg = <0x8000 0x1000>;
|
||||||
|
cache-unified;
|
||||||
|
cache-level = <2>;
|
||||||
|
arm,double-linefill-incr = <1>;
|
||||||
|
arm,double-linefill-wrap = <0>;
|
||||||
|
arm,double-linefill = <1>;
|
||||||
|
prefetch-data = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
scu@c000 {
|
||||||
|
compatible = "arm,cortex-a9-scu";
|
||||||
|
reg = <0xc000 0x58>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@c600 {
|
||||||
|
compatible = "arm,cortex-a9-twd-timer";
|
||||||
|
reg = <0xc600 0x20>;
|
||||||
|
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||||
|
clocks = <&coreclk 2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gic: interrupt-controller@d000 {
|
||||||
|
compatible = "arm,cortex-a9-gic";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0xd000 0x1000>,
|
||||||
|
<0xc100 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "marvell,orion-mdio";
|
||||||
|
reg = <0xc0054 0x4>;
|
||||||
|
clocks = <&gateclk 19>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Network controller */
|
||||||
|
ethernet@f0000 {
|
||||||
|
compatible = "marvell,armada-375-pp2";
|
||||||
|
reg = <0xf0000 0xa000>, /* Packet Processor regs */
|
||||||
|
<0xc0000 0x3060>, /* LMS regs */
|
||||||
|
<0xc4000 0x100>, /* eth0 regs */
|
||||||
|
<0xc5000 0x100>; /* eth1 regs */
|
||||||
|
clocks = <&gateclk 3>, <&gateclk 19>;
|
||||||
|
clock-names = "pp_clk", "gop_clk";
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
eth0: eth0@c4000 {
|
||||||
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
port-id = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
eth1: eth1@c5000 {
|
||||||
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
port-id = <1>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@10300 {
|
||||||
|
compatible = "marvell,orion-rtc";
|
||||||
|
reg = <0x10300 0x20>;
|
||||||
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
spi0: spi@10600 {
|
||||||
|
compatible = "marvell,armada-375-spi",
|
||||||
|
"marvell,orion-spi";
|
||||||
|
reg = <0x10600 0x50>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <0>;
|
||||||
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
spi1: spi@10680 {
|
||||||
|
compatible = "marvell,armada-375-spi",
|
||||||
|
"marvell,orion-spi";
|
||||||
|
reg = <0x10680 0x50>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <1>;
|
||||||
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c0: i2c@11000 {
|
||||||
|
compatible = "marvell,mv64xxx-i2c";
|
||||||
|
reg = <0x11000 0x20>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
timeout-ms = <1000>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1: i2c@11100 {
|
||||||
|
compatible = "marvell,mv64xxx-i2c";
|
||||||
|
reg = <0x11100 0x20>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
timeout-ms = <1000>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0: serial@12000 {
|
||||||
|
compatible = "snps,dw-apb-uart";
|
||||||
|
reg = <0x12000 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg-io-width = <1>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1: serial@12100 {
|
||||||
|
compatible = "snps,dw-apb-uart";
|
||||||
|
reg = <0x12100 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg-io-width = <1>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl {
|
||||||
|
compatible = "marvell,mv88f6720-pinctrl";
|
||||||
|
reg = <0x18000 0x24>;
|
||||||
|
|
||||||
|
i2c0_pins: i2c0-pins {
|
||||||
|
marvell,pins = "mpp14", "mpp15";
|
||||||
|
marvell,function = "i2c0";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1_pins: i2c1-pins {
|
||||||
|
marvell,pins = "mpp61", "mpp62";
|
||||||
|
marvell,function = "i2c1";
|
||||||
|
};
|
||||||
|
|
||||||
|
nand_pins: nand-pins {
|
||||||
|
marvell,pins = "mpp0", "mpp1", "mpp2",
|
||||||
|
"mpp3", "mpp4", "mpp5",
|
||||||
|
"mpp6", "mpp7", "mpp8",
|
||||||
|
"mpp9", "mpp10", "mpp11",
|
||||||
|
"mpp12", "mpp13";
|
||||||
|
marvell,function = "nand";
|
||||||
|
};
|
||||||
|
|
||||||
|
sdio_pins: sdio-pins {
|
||||||
|
marvell,pins = "mpp24", "mpp25", "mpp26",
|
||||||
|
"mpp27", "mpp28", "mpp29";
|
||||||
|
marvell,function = "sd";
|
||||||
|
};
|
||||||
|
|
||||||
|
spi0_pins: spi0-pins {
|
||||||
|
marvell,pins = "mpp0", "mpp1", "mpp4",
|
||||||
|
"mpp5", "mpp8", "mpp9";
|
||||||
|
marvell,function = "spi0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio0: gpio@18100 {
|
||||||
|
compatible = "marvell,orion-gpio";
|
||||||
|
reg = <0x18100 0x40>;
|
||||||
|
ngpios = <32>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio1: gpio@18140 {
|
||||||
|
compatible = "marvell,orion-gpio";
|
||||||
|
reg = <0x18140 0x40>;
|
||||||
|
ngpios = <32>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio2: gpio@18180 {
|
||||||
|
compatible = "marvell,orion-gpio";
|
||||||
|
reg = <0x18180 0x40>;
|
||||||
|
ngpios = <3>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
system-controller@18200 {
|
||||||
|
compatible = "marvell,armada-375-system-controller";
|
||||||
|
reg = <0x18200 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gateclk: clock-gating-control@18220 {
|
||||||
|
compatible = "marvell,armada-375-gating-clock";
|
||||||
|
reg = <0x18220 0x4>;
|
||||||
|
clocks = <&coreclk 0>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usbcluster: usb-cluster@18400 {
|
||||||
|
compatible = "marvell,armada-375-usb-cluster";
|
||||||
|
reg = <0x18400 0x4>;
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mbusc: mbus-controller@20000 {
|
||||||
|
compatible = "marvell,mbus-controller";
|
||||||
|
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpic: interrupt-controller@20a00 {
|
||||||
|
compatible = "marvell,mpic";
|
||||||
|
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
msi-controller;
|
||||||
|
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@20300 {
|
||||||
|
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
|
||||||
|
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||||
|
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<&mpic 5>,
|
||||||
|
<&mpic 6>;
|
||||||
|
clocks = <&coreclk 0>, <&refclk>;
|
||||||
|
clock-names = "nbclk", "fixed";
|
||||||
|
};
|
||||||
|
|
||||||
|
watchdog@20300 {
|
||||||
|
compatible = "marvell,armada-375-wdt";
|
||||||
|
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
|
||||||
|
clocks = <&coreclk 0>, <&refclk>;
|
||||||
|
clock-names = "nbclk", "fixed";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpurst@20800 {
|
||||||
|
compatible = "marvell,armada-370-cpu-reset";
|
||||||
|
reg = <0x20800 0x10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
coherency-fabric@21010 {
|
||||||
|
compatible = "marvell,armada-375-coherency-fabric";
|
||||||
|
reg = <0x21010 0x1c>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@50000 {
|
||||||
|
compatible = "marvell,orion-ehci";
|
||||||
|
reg = <0x50000 0x500>;
|
||||||
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gateclk 18>;
|
||||||
|
phys = <&usbcluster PHY_TYPE_USB2>;
|
||||||
|
phy-names = "usb";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@54000 {
|
||||||
|
compatible = "marvell,orion-ehci";
|
||||||
|
reg = <0x54000 0x500>;
|
||||||
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gateclk 26>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usb3@58000 {
|
||||||
|
compatible = "marvell,armada-375-xhci";
|
||||||
|
reg = <0x58000 0x20000>,<0x5b880 0x80>;
|
||||||
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gateclk 16>;
|
||||||
|
phys = <&usbcluster PHY_TYPE_USB3>;
|
||||||
|
phy-names = "usb";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
xor@60800 {
|
||||||
|
compatible = "marvell,orion-xor";
|
||||||
|
reg = <0x60800 0x100
|
||||||
|
0x60A00 0x100>;
|
||||||
|
clocks = <&gateclk 22>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
xor00 {
|
||||||
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
dmacap,memcpy;
|
||||||
|
dmacap,xor;
|
||||||
|
};
|
||||||
|
xor01 {
|
||||||
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
dmacap,memcpy;
|
||||||
|
dmacap,xor;
|
||||||
|
dmacap,memset;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
xor@60900 {
|
||||||
|
compatible = "marvell,orion-xor";
|
||||||
|
reg = <0x60900 0x100
|
||||||
|
0x60b00 0x100>;
|
||||||
|
clocks = <&gateclk 23>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
xor10 {
|
||||||
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
dmacap,memcpy;
|
||||||
|
dmacap,xor;
|
||||||
|
};
|
||||||
|
xor11 {
|
||||||
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
dmacap,memcpy;
|
||||||
|
dmacap,xor;
|
||||||
|
dmacap,memset;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
crypto@90000 {
|
||||||
|
compatible = "marvell,armada-375-crypto";
|
||||||
|
reg = <0x90000 0x10000>;
|
||||||
|
reg-names = "regs";
|
||||||
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gateclk 30>, <&gateclk 31>,
|
||||||
|
<&gateclk 28>, <&gateclk 29>;
|
||||||
|
clock-names = "cesa0", "cesa1",
|
||||||
|
"cesaz0", "cesaz1";
|
||||||
|
marvell,crypto-srams = <&crypto_sram0>,
|
||||||
|
<&crypto_sram1>;
|
||||||
|
marvell,crypto-sram-size = <0x800>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sata@a0000 {
|
||||||
|
compatible = "marvell,orion-sata";
|
||||||
|
reg = <0xa0000 0x5000>;
|
||||||
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gateclk 14>, <&gateclk 20>;
|
||||||
|
clock-names = "0", "1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
nand@d0000 {
|
||||||
|
compatible = "marvell,armada370-nand";
|
||||||
|
reg = <0xd0000 0x54>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gateclk 11>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
mvsdio@d4000 {
|
||||||
|
compatible = "marvell,orion-sdio";
|
||||||
|
reg = <0xd4000 0x200>;
|
||||||
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gateclk 17>;
|
||||||
|
bus-width = <4>;
|
||||||
|
cap-sdio-irq;
|
||||||
|
cap-sd-highspeed;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
thermal@e8078 {
|
||||||
|
compatible = "marvell,armada375-thermal";
|
||||||
|
reg = <0xe8078 0x4>, <0xe807c 0x8>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
coreclk: mvebu-sar@e8204 {
|
||||||
|
compatible = "marvell,armada-375-core-clock";
|
||||||
|
reg = <0xe8204 0x04>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
coredivclk: corediv-clock@e8250 {
|
||||||
|
compatible = "marvell,armada-375-corediv-clock";
|
||||||
|
reg = <0xe8250 0xc>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
clocks = <&mainpll>;
|
||||||
|
clock-output-names = "nand";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie-controller {
|
||||||
|
compatible = "marvell,armada-370-pcie";
|
||||||
|
status = "disabled";
|
||||||
|
device_type = "pci";
|
||||||
|
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
msi-parent = <&mpic>;
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
|
|
||||||
|
ranges =
|
||||||
|
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||||
|
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||||
|
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||||
|
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
|
||||||
|
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
|
||||||
|
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
|
||||||
|
|
||||||
|
pcie@1,0 {
|
||||||
|
device_type = "pci";
|
||||||
|
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||||
|
reg = <0x0800 0 0 0 0>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||||
|
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||||
|
interrupt-map-mask = <0 0 0 0>;
|
||||||
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
marvell,pcie-port = <0>;
|
||||||
|
marvell,pcie-lane = <0>;
|
||||||
|
clocks = <&gateclk 5>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie@2,0 {
|
||||||
|
device_type = "pci";
|
||||||
|
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||||
|
reg = <0x1000 0 0 0 0>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||||
|
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||||
|
interrupt-map-mask = <0 0 0 0>;
|
||||||
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
marvell,pcie-port = <0>;
|
||||||
|
marvell,pcie-lane = <1>;
|
||||||
|
clocks = <&gateclk 6>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
crypto_sram0: sa-sram0 {
|
||||||
|
compatible = "mmio-sram";
|
||||||
|
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
|
||||||
|
clocks = <&gateclk 30>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
|
||||||
|
};
|
||||||
|
|
||||||
|
crypto_sram1: sa-sram1 {
|
||||||
|
compatible = "mmio-sram";
|
||||||
|
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
|
||||||
|
clocks = <&gateclk 31>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
@ -1,5 +1,8 @@
|
|||||||
if ARCH_MVEBU
|
if ARCH_MVEBU
|
||||||
|
|
||||||
|
config ARMADA_375
|
||||||
|
bool
|
||||||
|
|
||||||
config ARMADA_38X
|
config ARMADA_38X
|
||||||
bool
|
bool
|
||||||
|
|
||||||
@ -23,13 +26,17 @@ config DB_88F6820_GP
|
|||||||
select ARMADA_38X
|
select ARMADA_38X
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "Marvell MVEBU (Armada XP/38x) board select"
|
prompt "Marvell MVEBU (Armada XP/375/38x) board select"
|
||||||
optional
|
optional
|
||||||
|
|
||||||
config TARGET_CLEARFOG
|
config TARGET_CLEARFOG
|
||||||
bool "Support ClearFog"
|
bool "Support ClearFog"
|
||||||
select DB_88F6820_GP
|
select DB_88F6820_GP
|
||||||
|
|
||||||
|
config TARGET_DB_88F6720
|
||||||
|
bool "Support DB-88F6720 Armada 375"
|
||||||
|
select ARMADA_375
|
||||||
|
|
||||||
config TARGET_DB_88F6820_GP
|
config TARGET_DB_88F6820_GP
|
||||||
bool "Support DB-88F6820-GP"
|
bool "Support DB-88F6820-GP"
|
||||||
select DB_88F6820_GP
|
select DB_88F6820_GP
|
||||||
@ -54,6 +61,7 @@ endchoice
|
|||||||
|
|
||||||
config SYS_BOARD
|
config SYS_BOARD
|
||||||
default "clearfog" if TARGET_CLEARFOG
|
default "clearfog" if TARGET_CLEARFOG
|
||||||
|
default "db-88f6720" if TARGET_DB_88F6720
|
||||||
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
||||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||||
default "ds414" if TARGET_DS414
|
default "ds414" if TARGET_DS414
|
||||||
@ -62,6 +70,7 @@ config SYS_BOARD
|
|||||||
|
|
||||||
config SYS_CONFIG_NAME
|
config SYS_CONFIG_NAME
|
||||||
default "clearfog" if TARGET_CLEARFOG
|
default "clearfog" if TARGET_CLEARFOG
|
||||||
|
default "db-88f6720" if TARGET_DB_88F6720
|
||||||
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
||||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||||
default "ds414" if TARGET_DS414
|
default "ds414" if TARGET_DS414
|
||||||
@ -70,6 +79,7 @@ config SYS_CONFIG_NAME
|
|||||||
|
|
||||||
config SYS_VENDOR
|
config SYS_VENDOR
|
||||||
default "Marvell" if TARGET_DB_MV784MP_GP
|
default "Marvell" if TARGET_DB_MV784MP_GP
|
||||||
|
default "Marvell" if TARGET_DB_88F6720
|
||||||
default "Marvell" if TARGET_DB_88F6820_GP
|
default "Marvell" if TARGET_DB_88F6820_GP
|
||||||
default "solidrun" if TARGET_CLEARFOG
|
default "solidrun" if TARGET_CLEARFOG
|
||||||
default "Synology" if TARGET_DS414
|
default "Synology" if TARGET_DS414
|
||||||
|
@ -15,6 +15,7 @@ else
|
|||||||
obj-y = cpu.o
|
obj-y = cpu.o
|
||||||
obj-y += dram.o
|
obj-y += dram.o
|
||||||
ifndef CONFIG_SPL_BUILD
|
ifndef CONFIG_SPL_BUILD
|
||||||
|
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
|
||||||
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
|
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
|
||||||
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
|
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
|
||||||
endif
|
endif
|
||||||
|
@ -54,17 +54,57 @@ int mvebu_soc_family(void)
|
|||||||
case SOC_MV78260_ID:
|
case SOC_MV78260_ID:
|
||||||
case SOC_MV78460_ID:
|
case SOC_MV78460_ID:
|
||||||
return MVEBU_SOC_AXP;
|
return MVEBU_SOC_AXP;
|
||||||
|
|
||||||
|
case SOC_88F6720_ID:
|
||||||
|
return MVEBU_SOC_A375;
|
||||||
|
|
||||||
case SOC_88F6810_ID:
|
case SOC_88F6810_ID:
|
||||||
case SOC_88F6820_ID:
|
case SOC_88F6820_ID:
|
||||||
case SOC_88F6828_ID:
|
case SOC_88F6828_ID:
|
||||||
return MVEBU_SOC_A38X;
|
return MVEBU_SOC_A38X;
|
||||||
}
|
}
|
||||||
|
|
||||||
return MVEBU_SOC_UNKNOWN;
|
return MVEBU_SOC_UNKNOWN;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||||
|
|
||||||
#if defined(CONFIG_ARMADA_38X)
|
#if defined(CONFIG_ARMADA_375)
|
||||||
|
/* SAR frequency values for Armada 375 */
|
||||||
|
static const struct sar_freq_modes sar_freq_tab[] = {
|
||||||
|
{ 0, 0x0, 266, 133, 266 },
|
||||||
|
{ 1, 0x0, 333, 167, 167 },
|
||||||
|
{ 2, 0x0, 333, 167, 222 },
|
||||||
|
{ 3, 0x0, 333, 167, 333 },
|
||||||
|
{ 4, 0x0, 400, 200, 200 },
|
||||||
|
{ 5, 0x0, 400, 200, 267 },
|
||||||
|
{ 6, 0x0, 400, 200, 400 },
|
||||||
|
{ 7, 0x0, 500, 250, 250 },
|
||||||
|
{ 8, 0x0, 500, 250, 334 },
|
||||||
|
{ 9, 0x0, 500, 250, 500 },
|
||||||
|
{ 10, 0x0, 533, 267, 267 },
|
||||||
|
{ 11, 0x0, 533, 267, 356 },
|
||||||
|
{ 12, 0x0, 533, 267, 533 },
|
||||||
|
{ 13, 0x0, 600, 300, 300 },
|
||||||
|
{ 14, 0x0, 600, 300, 400 },
|
||||||
|
{ 15, 0x0, 600, 300, 600 },
|
||||||
|
{ 16, 0x0, 666, 333, 333 },
|
||||||
|
{ 17, 0x0, 666, 333, 444 },
|
||||||
|
{ 18, 0x0, 666, 333, 666 },
|
||||||
|
{ 19, 0x0, 800, 400, 267 },
|
||||||
|
{ 20, 0x0, 800, 400, 400 },
|
||||||
|
{ 21, 0x0, 800, 400, 534 },
|
||||||
|
{ 22, 0x0, 900, 450, 300 },
|
||||||
|
{ 23, 0x0, 900, 450, 450 },
|
||||||
|
{ 24, 0x0, 900, 450, 600 },
|
||||||
|
{ 25, 0x0, 1000, 500, 500 },
|
||||||
|
{ 26, 0x0, 1000, 500, 667 },
|
||||||
|
{ 27, 0x0, 1000, 333, 500 },
|
||||||
|
{ 28, 0x0, 400, 400, 400 },
|
||||||
|
{ 29, 0x0, 1100, 550, 550 },
|
||||||
|
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
|
||||||
|
};
|
||||||
|
#elif defined(CONFIG_ARMADA_38X)
|
||||||
/* SAR frequency values for Armada 38x */
|
/* SAR frequency values for Armada 38x */
|
||||||
static const struct sar_freq_modes sar_freq_tab[] = {
|
static const struct sar_freq_modes sar_freq_tab[] = {
|
||||||
{ 0x0, 0x0, 666, 333, 333 },
|
{ 0x0, 0x0, 666, 333, 333 },
|
||||||
@ -98,9 +138,13 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
|
|||||||
u32 freq;
|
u32 freq;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARMADA_375)
|
||||||
|
val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
|
||||||
|
#else
|
||||||
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
|
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
|
||||||
|
#endif
|
||||||
freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
|
freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
|
||||||
#if !defined(CONFIG_ARMADA_38X)
|
#if defined(SAR2_CPU_FREQ_MASK)
|
||||||
/*
|
/*
|
||||||
* Shift CPU0 clock frequency select bit from SAR2 register
|
* Shift CPU0 clock frequency select bit from SAR2 register
|
||||||
* into correct position
|
* into correct position
|
||||||
@ -110,7 +154,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
|
|||||||
#endif
|
#endif
|
||||||
for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
|
for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
|
||||||
if (sar_freq_tab[i].val == freq) {
|
if (sar_freq_tab[i].val == freq) {
|
||||||
#if defined(CONFIG_ARMADA_38X)
|
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
|
||||||
*sar_freq = sar_freq_tab[i];
|
*sar_freq = sar_freq_tab[i];
|
||||||
return;
|
return;
|
||||||
#else
|
#else
|
||||||
@ -152,6 +196,9 @@ int print_cpuinfo(void)
|
|||||||
case SOC_MV78460_ID:
|
case SOC_MV78460_ID:
|
||||||
puts("MV78460-");
|
puts("MV78460-");
|
||||||
break;
|
break;
|
||||||
|
case SOC_88F6720_ID:
|
||||||
|
puts("MV88F6720-");
|
||||||
|
break;
|
||||||
case SOC_88F6810_ID:
|
case SOC_88F6810_ID:
|
||||||
puts("MV88F6810-");
|
puts("MV88F6810-");
|
||||||
break;
|
break;
|
||||||
@ -180,6 +227,17 @@ int print_cpuinfo(void)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (mvebu_soc_family() == MVEBU_SOC_A375) {
|
||||||
|
switch (revid) {
|
||||||
|
case MV_88F67XX_A0_ID:
|
||||||
|
puts("A0");
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("?? (%x)", revid);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
|
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
|
||||||
switch (revid) {
|
switch (revid) {
|
||||||
case MV_88F68XX_Z1_ID:
|
case MV_88F68XX_Z1_ID:
|
||||||
@ -478,8 +536,15 @@ void enable_caches(void)
|
|||||||
/* Avoid problem with e.g. neta ethernet driver */
|
/* Avoid problem with e.g. neta ethernet driver */
|
||||||
invalidate_dcache_all();
|
invalidate_dcache_all();
|
||||||
|
|
||||||
/* Enable D-cache. I-cache is already enabled in start.S */
|
/*
|
||||||
dcache_enable();
|
* Armada 375 still has some problems with d-cache enabled in the
|
||||||
|
* ethernet driver (mvpp2). So lets keep the d-cache disabled
|
||||||
|
* until this is solved.
|
||||||
|
*/
|
||||||
|
if (mvebu_soc_family() != MVEBU_SOC_A375) {
|
||||||
|
/* Enable D-cache. I-cache is already enabled in start.S */
|
||||||
|
dcache_enable();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void v7_outer_cache_enable(void)
|
void v7_outer_cache_enable(void)
|
||||||
|
@ -17,7 +17,8 @@
|
|||||||
|
|
||||||
#include <asm/arch/soc.h>
|
#include <asm/arch/soc.h>
|
||||||
|
|
||||||
#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X)
|
#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
|
||||||
|
|| defined(CONFIG_ARMADA_38X)
|
||||||
/*
|
/*
|
||||||
* Set this for the common xor register definitions needed in dram.c
|
* Set this for the common xor register definitions needed in dram.c
|
||||||
* for A38x as well here.
|
* for A38x as well here.
|
||||||
@ -78,8 +79,10 @@
|
|||||||
#ifdef CONFIG_CMD_NET
|
#ifdef CONFIG_CMD_NET
|
||||||
#define CONFIG_CMD_MII
|
#define CONFIG_CMD_MII
|
||||||
#define CONFIG_MII /* expose smi ove miiphy interface */
|
#define CONFIG_MII /* expose smi ove miiphy interface */
|
||||||
|
#if !defined(CONFIG_ARMADA_375)
|
||||||
#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
|
#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
|
||||||
#define CONFIG_PHYLIB
|
#define CONFIG_PHYLIB
|
||||||
|
#endif
|
||||||
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
|
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
|
||||||
#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
|
#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
|
||||||
#define CONFIG_ARP_TIMEOUT 200
|
#define CONFIG_ARP_TIMEOUT 200
|
||||||
|
@ -61,6 +61,7 @@ enum cpu_attrib {
|
|||||||
|
|
||||||
enum {
|
enum {
|
||||||
MVEBU_SOC_AXP,
|
MVEBU_SOC_AXP,
|
||||||
|
MVEBU_SOC_A375,
|
||||||
MVEBU_SOC_A38X,
|
MVEBU_SOC_A38X,
|
||||||
MVEBU_SOC_UNKNOWN,
|
MVEBU_SOC_UNKNOWN,
|
||||||
};
|
};
|
||||||
@ -89,7 +90,11 @@ struct mbus_win {
|
|||||||
* Ref: Datasheet sec:A.28
|
* Ref: Datasheet sec:A.28
|
||||||
*/
|
*/
|
||||||
struct mvebu_system_registers {
|
struct mvebu_system_registers {
|
||||||
|
#if defined(CONFIG_ARMADA_375)
|
||||||
|
u8 pad1[0x54];
|
||||||
|
#else
|
||||||
u8 pad1[0x60];
|
u8 pad1[0x60];
|
||||||
|
#endif
|
||||||
u32 rstoutn_mask; /* 0x60 */
|
u32 rstoutn_mask; /* 0x60 */
|
||||||
u32 sys_soft_rst; /* 0x64 */
|
u32 sys_soft_rst; /* 0x64 */
|
||||||
};
|
};
|
||||||
|
@ -14,10 +14,14 @@
|
|||||||
#define SOC_MV78230_ID 0x7823
|
#define SOC_MV78230_ID 0x7823
|
||||||
#define SOC_MV78260_ID 0x7826
|
#define SOC_MV78260_ID 0x7826
|
||||||
#define SOC_MV78460_ID 0x7846
|
#define SOC_MV78460_ID 0x7846
|
||||||
|
#define SOC_88F6720_ID 0x6720
|
||||||
#define SOC_88F6810_ID 0x6810
|
#define SOC_88F6810_ID 0x6810
|
||||||
#define SOC_88F6820_ID 0x6820
|
#define SOC_88F6820_ID 0x6820
|
||||||
#define SOC_88F6828_ID 0x6828
|
#define SOC_88F6828_ID 0x6828
|
||||||
|
|
||||||
|
/* A375 revisions */
|
||||||
|
#define MV_88F67XX_A0_ID 0x3
|
||||||
|
|
||||||
/* A38x revisions */
|
/* A38x revisions */
|
||||||
#define MV_88F68XX_Z1_ID 0x0
|
#define MV_88F68XX_Z1_ID 0x0
|
||||||
#define MV_88F68XX_A0_ID 0x4
|
#define MV_88F68XX_A0_ID 0x4
|
||||||
@ -106,7 +110,20 @@
|
|||||||
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
|
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
|
||||||
#define BOOTROM_ERR_MODE_UART 0x6
|
#define BOOTROM_ERR_MODE_UART 0x6
|
||||||
|
|
||||||
#if defined(CONFIG_ARMADA_38X)
|
#if defined(CONFIG_ARMADA_375)
|
||||||
|
/* SAR values for Armada 375 */
|
||||||
|
#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
|
||||||
|
#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204))
|
||||||
|
|
||||||
|
#define SAR_CPU_FREQ_OFFS 17
|
||||||
|
#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
|
||||||
|
|
||||||
|
#define BOOT_DEV_SEL_OFFS 3
|
||||||
|
#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
|
||||||
|
|
||||||
|
#define BOOT_FROM_UART 0x30
|
||||||
|
#define BOOT_FROM_SPI 0x38
|
||||||
|
#elif defined(CONFIG_ARMADA_38X)
|
||||||
/* SAR values for Armada 38x */
|
/* SAR values for Armada 38x */
|
||||||
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
|
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
|
||||||
|
|
||||||
|
@ -99,11 +99,14 @@ void board_init_f(ulong dummy)
|
|||||||
|
|
||||||
timer_init();
|
timer_init();
|
||||||
|
|
||||||
|
/* Armada 375 does not support SerDes and DDR3 init yet */
|
||||||
|
#if !defined(CONFIG_ARMADA_375)
|
||||||
/* First init the serdes PHY's */
|
/* First init the serdes PHY's */
|
||||||
serdes_phy_config();
|
serdes_phy_config();
|
||||||
|
|
||||||
/* Setup DDR */
|
/* Setup DDR */
|
||||||
ddr3_init();
|
ddr3_init();
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Return to the BootROM to continue the Marvell xmodem
|
* Return to the BootROM to continue the Marvell xmodem
|
||||||
|
6
board/Marvell/db-88f6720/MAINTAINERS
Normal file
6
board/Marvell/db-88f6720/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
DB_88F6720 BOARD
|
||||||
|
M: Stefan Roese <sr@denx.de>
|
||||||
|
S: Maintained
|
||||||
|
F: board/Marvell/db-88f6720/
|
||||||
|
F: include/configs/db-88f6720.h
|
||||||
|
F: configs/db-88f6720_defconfig
|
7
board/Marvell/db-88f6720/Makefile
Normal file
7
board/Marvell/db-88f6720/Makefile
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
#
|
||||||
|
# Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y := db-88f6720.o
|
91
board/Marvell/db-88f6720/db-88f6720.c
Normal file
91
board/Marvell/db-88f6720/db-88f6720.c
Normal file
@ -0,0 +1,91 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <miiphy.h>
|
||||||
|
#include <netdev.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/arch/cpu.h>
|
||||||
|
#include <asm/arch/soc.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Those values and defines are taken from the Marvell U-Boot version
|
||||||
|
* "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
|
||||||
|
*/
|
||||||
|
#define DB_88F6720_MPP0_7 0x00020020 /* SPI */
|
||||||
|
#define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
|
||||||
|
#define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
|
||||||
|
#define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
|
||||||
|
#define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
|
||||||
|
#define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
|
||||||
|
#define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
|
||||||
|
#define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
|
||||||
|
#define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
|
||||||
|
|
||||||
|
#define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
|
||||||
|
#define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
|
||||||
|
#define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
|
||||||
|
#define DB_88F6720_GPP_OUT_VAL_LOW 0x0
|
||||||
|
#define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
|
||||||
|
#define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
|
||||||
|
#define DB_88F6720_GPP_POL_LOW 0x0
|
||||||
|
#define DB_88F6720_GPP_POL_MID 0x0
|
||||||
|
#define DB_88F6720_GPP_POL_HIGH 0x0
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
/* Configure MPP */
|
||||||
|
writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
|
||||||
|
writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
|
||||||
|
writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
|
||||||
|
writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
|
||||||
|
writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
|
||||||
|
writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
|
||||||
|
writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
|
||||||
|
writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
|
||||||
|
writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
|
||||||
|
|
||||||
|
/* Configure GPIO */
|
||||||
|
/* Set GPP Out value */
|
||||||
|
writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||||
|
writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||||
|
writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
|
||||||
|
|
||||||
|
/* Set GPP Polarity */
|
||||||
|
writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||||
|
writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||||
|
writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
|
||||||
|
|
||||||
|
/* Set GPP Out Enable */
|
||||||
|
writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||||
|
writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||||
|
writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
/* adress of boot parameters */
|
||||||
|
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
puts("Board: Marvell DB-88F6720\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_eth_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||||
|
return pci_eth_init(bis);
|
||||||
|
}
|
12
board/Marvell/db-88f6720/kwbimage.cfg
Normal file
12
board/Marvell/db-88f6720/kwbimage.cfg
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
#
|
||||||
|
# Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||||
|
#
|
||||||
|
|
||||||
|
# Armada XP uses version 1 image format
|
||||||
|
VERSION 1
|
||||||
|
|
||||||
|
# Boot Media configurations
|
||||||
|
BOOT_FROM spi
|
||||||
|
|
||||||
|
# Binary Header (bin_hdr) with DDR3 training code
|
||||||
|
BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
|
28
configs/db-88f6720_defconfig
Normal file
28
configs/db-88f6720_defconfig
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_MVEBU=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||||
|
CONFIG_TARGET_DB_88F6720=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL=y
|
||||||
|
# CONFIG_CMD_IMLS is not set
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
|
CONFIG_MISC=y
|
||||||
|
CONFIG_NAND_PXA3XX=y
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_MACRONIX=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
CONFIG_MVPP2=y
|
||||||
|
CONFIG_DEBUG_UART=y
|
||||||
|
CONFIG_DEBUG_UART_BASE=0xf1012000
|
||||||
|
CONFIG_DEBUG_UART_CLOCK=250000000
|
||||||
|
CONFIG_DEBUG_UART_SHIFT=2
|
||||||
|
CONFIG_SYS_NS16550=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_STORAGE=y
|
@ -115,6 +115,14 @@ config ETH_DESIGNWARE
|
|||||||
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
|
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
|
||||||
provide the PHY (physical media interface).
|
provide the PHY (physical media interface).
|
||||||
|
|
||||||
|
config MVPP2
|
||||||
|
bool "Marvell Armada 375 network interface support"
|
||||||
|
depends on ARMADA_375
|
||||||
|
select PHYLIB
|
||||||
|
help
|
||||||
|
This driver supports the network interface units in the
|
||||||
|
Marvell ARMADA 375 SoC.
|
||||||
|
|
||||||
config PCH_GBE
|
config PCH_GBE
|
||||||
bool "Intel Platform Controller Hub EG20T GMAC driver"
|
bool "Intel Platform Controller Hub EG20T GMAC driver"
|
||||||
depends on DM_ETH && DM_PCI
|
depends on DM_ETH && DM_PCI
|
||||||
|
@ -42,6 +42,7 @@ obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
|
|||||||
obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
|
obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
|
||||||
obj-$(CONFIG_MVGBE) += mvgbe.o
|
obj-$(CONFIG_MVGBE) += mvgbe.o
|
||||||
obj-$(CONFIG_MVNETA) += mvneta.o
|
obj-$(CONFIG_MVNETA) += mvneta.o
|
||||||
|
obj-$(CONFIG_MVPP2) += mvpp2.o
|
||||||
obj-$(CONFIG_NATSEMI) += natsemi.o
|
obj-$(CONFIG_NATSEMI) += natsemi.o
|
||||||
obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
|
obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
|
||||||
obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
|
obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
|
||||||
|
4190
drivers/net/mvpp2.c
Normal file
4190
drivers/net/mvpp2.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -315,6 +315,7 @@ static const struct dm_spi_ops mvebu_spi_ops = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
static const struct udevice_id mvebu_spi_ids[] = {
|
static const struct udevice_id mvebu_spi_ids[] = {
|
||||||
|
{ .compatible = "marvell,armada-375-spi" },
|
||||||
{ .compatible = "marvell,armada-380-spi" },
|
{ .compatible = "marvell,armada-380-spi" },
|
||||||
{ .compatible = "marvell,armada-xp-spi" },
|
{ .compatible = "marvell,armada-xp-spi" },
|
||||||
{ }
|
{ }
|
||||||
|
120
include/configs/db-88f6720.h
Normal file
120
include/configs/db-88f6720.h
Normal file
@ -0,0 +1,120 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CONFIG_DB_88F6720_H
|
||||||
|
#define _CONFIG_DB_88F6720_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options (easy to change)
|
||||||
|
*/
|
||||||
|
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
|
||||||
|
* for DDR ECC byte filling in the SPL before loading the main
|
||||||
|
* U-Boot into it.
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0x00800000
|
||||||
|
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Commands configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||||
|
#define CONFIG_CMD_CACHE
|
||||||
|
#define CONFIG_CMD_DHCP
|
||||||
|
#define CONFIG_CMD_ENV
|
||||||
|
#define CONFIG_CMD_EXT2
|
||||||
|
#define CONFIG_CMD_EXT4
|
||||||
|
#define CONFIG_CMD_FAT
|
||||||
|
#define CONFIG_CMD_FS_GENERIC
|
||||||
|
#define CONFIG_CMD_I2C
|
||||||
|
#define CONFIG_CMD_PING
|
||||||
|
#define CONFIG_CMD_SF
|
||||||
|
#define CONFIG_CMD_SPI
|
||||||
|
#define CONFIG_CMD_TFTPPUT
|
||||||
|
#define CONFIG_CMD_TIME
|
||||||
|
|
||||||
|
/* I2C */
|
||||||
|
#define CONFIG_SYS_I2C
|
||||||
|
#define CONFIG_SYS_I2C_MVTWSI
|
||||||
|
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
||||||
|
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||||
|
#define CONFIG_SYS_I2C_SPEED 100000
|
||||||
|
|
||||||
|
/* USB/EHCI configuration */
|
||||||
|
#define CONFIG_EHCI_IS_TDI
|
||||||
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||||
|
|
||||||
|
/* SPI NOR flash default params, used by sf commands */
|
||||||
|
#define CONFIG_SF_DEFAULT_SPEED 1000000
|
||||||
|
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
||||||
|
|
||||||
|
/* Environment in SPI NOR flash */
|
||||||
|
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||||
|
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
|
||||||
|
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
|
||||||
|
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
|
||||||
|
|
||||||
|
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
||||||
|
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
|
||||||
|
#define CONFIG_SYS_ALT_MEMTEST
|
||||||
|
|
||||||
|
/* Additional FS support/configuration */
|
||||||
|
#define CONFIG_SUPPORT_VFAT
|
||||||
|
|
||||||
|
/*
|
||||||
|
* mv-common.h should be defined after CMD configs since it used them
|
||||||
|
* to enable certain macros
|
||||||
|
*/
|
||||||
|
#include "mv-common.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory layout while starting into the bin_hdr via the
|
||||||
|
* BootROM:
|
||||||
|
*
|
||||||
|
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
|
||||||
|
* 0x4000.4030 bin_hdr start address
|
||||||
|
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
|
||||||
|
* 0x4007.fffc BootROM stack top
|
||||||
|
*
|
||||||
|
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
|
||||||
|
* L2 cache thus cannot be used.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* SPL */
|
||||||
|
/* Defines for SPL */
|
||||||
|
#define CONFIG_SPL_FRAMEWORK
|
||||||
|
#define CONFIG_SPL_TEXT_BASE 0x40004030
|
||||||
|
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
||||||
|
|
||||||
|
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
||||||
|
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
#define CONFIG_SYS_MALLOC_SIMPLE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
||||||
|
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
||||||
|
|
||||||
|
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||||
|
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||||
|
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||||
|
#define CONFIG_SPL_I2C_SUPPORT
|
||||||
|
|
||||||
|
/* SPL related SPI defines */
|
||||||
|
#define CONFIG_SPL_SPI_SUPPORT
|
||||||
|
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||||
|
#define CONFIG_SPL_SPI_LOAD
|
||||||
|
#define CONFIG_SPL_SPI_BUS 0
|
||||||
|
#define CONFIG_SPL_SPI_CS 0
|
||||||
|
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||||
|
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
|
||||||
|
|
||||||
|
#endif /* _CONFIG_DB_88F6720_H */
|
19
include/dt-bindings/phy/phy.h
Normal file
19
include/dt-bindings/phy/phy.h
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
/*
|
||||||
|
*
|
||||||
|
* This header provides constants for the phy framework
|
||||||
|
*
|
||||||
|
* Copyright (C) 2014 STMicroelectronics
|
||||||
|
* Author: Gabriel Fernandez <gabriel.fernandez@st.com>
|
||||||
|
* License terms: GNU General Public License (GPL), version 2
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _DT_BINDINGS_PHY
|
||||||
|
#define _DT_BINDINGS_PHY
|
||||||
|
|
||||||
|
#define PHY_NONE 0
|
||||||
|
#define PHY_TYPE_SATA 1
|
||||||
|
#define PHY_TYPE_PCIE 2
|
||||||
|
#define PHY_TYPE_USB2 3
|
||||||
|
#define PHY_TYPE_USB3 4
|
||||||
|
|
||||||
|
#endif /* _DT_BINDINGS_PHY */
|
@ -337,6 +337,8 @@ struct vlan_ethernet_hdr {
|
|||||||
#define PROT_ARP 0x0806 /* IP ARP protocol */
|
#define PROT_ARP 0x0806 /* IP ARP protocol */
|
||||||
#define PROT_RARP 0x8035 /* IP ARP protocol */
|
#define PROT_RARP 0x8035 /* IP ARP protocol */
|
||||||
#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
|
#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
|
||||||
|
#define PROT_IPV6 0x86dd /* IPv6 over bluebook */
|
||||||
|
#define PROT_PPP_SES 0x8864 /* PPPoE session messages */
|
||||||
|
|
||||||
#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */
|
#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */
|
||||||
#define IPPROTO_UDP 17 /* User Datagram Protocol */
|
#define IPPROTO_UDP 17 /* User Datagram Protocol */
|
||||||
|
Loading…
Reference in New Issue
Block a user