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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
This commit is contained in:
commit
7df4ff2c26
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@ -40,7 +40,7 @@ enum {
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#hz "Hz cannot be hit with PLL "\
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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"divisors on line " __stringify(__LINE__));
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/* use interge mode*/
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/* use integer mode*/
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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@ -61,8 +61,8 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/* use interger mode */
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/* use integer mode */
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rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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rk_clrsetreg(&pll->con0,
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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@ -31,7 +31,7 @@
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0xff8effff
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#define CONFIG_SPL_STACK 0xff8effff
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#define CONFIG_SPL_TEXT_BASE 0xff8c2000
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#define CONFIG_SPL_TEXT_BASE 0xff8c2000
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#define CONFIG_SPL_MAX_SIZE 0x30000
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#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000
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/* BSS setup */
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/* BSS setup */
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#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
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#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
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@ -76,7 +76,7 @@ static struct spl_info spl_infos[] = {
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{ "rk3188", "RK31", 0x8000 - 0x800, true, false },
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{ "rk3188", "RK31", 0x8000 - 0x800, true, false },
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{ "rk3288", "RK32", 0x8000, false, false },
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{ "rk3288", "RK32", 0x8000, false, false },
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{ "rk3328", "RK32", 0x8000 - 0x1000, false, false },
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{ "rk3328", "RK32", 0x8000 - 0x1000, false, false },
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{ "rk3399", "RK33", 0x20000, false, true },
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{ "rk3399", "RK33", 0x30000 - 0x2000, false, true },
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{ "rv1108", "RK11", 0x1800, false, false},
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{ "rv1108", "RK11", 0x1800, false, false},
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};
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};
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@ -226,11 +226,6 @@ static inline unsigned rkcommon_offset_to_spi(unsigned offset)
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return ((offset & ~0x7ff) << 1) + (offset & 0x7ff);
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return ((offset & ~0x7ff) << 1) + (offset & 0x7ff);
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}
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}
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static inline unsigned rkcommon_spi_to_offset(unsigned offset)
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{
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return ((offset & ~0x7ff) >> 1) + (offset & 0x7ff);
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}
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static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
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static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
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struct spl_info **spl_info)
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struct spl_info **spl_info)
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{
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{
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