mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
arm: Remove omap3_ha board
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Stefan Roese <sr@denx.de> Cc: Tapani Utriainen <linuxfae@technexion.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
d137604c20
commit
7db3958f07
|
|
@ -165,7 +165,6 @@ source "board/isee/igep00x0/Kconfig"
|
|||
source "board/ti/am3517crane/Kconfig"
|
||||
source "board/logicpd/omap3som/Kconfig"
|
||||
source "board/nokia/rx51/Kconfig"
|
||||
source "board/technexion/tao3530/Kconfig"
|
||||
source "board/lg/sniper/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,12 +0,0 @@
|
|||
if TARGET_TAO3530
|
||||
|
||||
config SYS_BOARD
|
||||
default "tao3530"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "technexion"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "tao3530"
|
||||
|
||||
endif
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
TAO3530 BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/technexion/tao3530/
|
||||
F: include/configs/tao3530.h
|
||||
F: configs/omap3_ha_defconfig
|
||||
|
||||
TAO3530 BOARD
|
||||
M: Tapani Utriainen <linuxfae@technexion.com>
|
||||
S: Maintained
|
||||
F: configs/tao3530_defconfig
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-y := tao3530.o
|
||||
|
|
@ -1,225 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Maintainer :
|
||||
* Tapani Utriainen <linuxfae@technexion.com>
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <bootstage.h>
|
||||
#include <init.h>
|
||||
#include <malloc.h>
|
||||
#include <netdev.h>
|
||||
#include <twl4030.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <usb.h>
|
||||
#include <asm/ehci-omap.h>
|
||||
|
||||
#include "tao3530.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int tao3530_revision(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/* char *label argument is unused in gpio_request() */
|
||||
ret = gpio_request(65, "");
|
||||
if (ret) {
|
||||
puts("Error: GPIO 65 not available\n");
|
||||
goto out;
|
||||
}
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));
|
||||
|
||||
ret = gpio_request(1, "");
|
||||
if (ret) {
|
||||
puts("Error: GPIO 1 not available\n");
|
||||
goto out2;
|
||||
}
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4));
|
||||
|
||||
ret = gpio_direction_input(65);
|
||||
if (ret) {
|
||||
puts("Error: GPIO 65 not available for input\n");
|
||||
goto out3;
|
||||
}
|
||||
|
||||
ret = gpio_direction_input(1);
|
||||
if (ret) {
|
||||
puts("Error: GPIO 1 not available for input\n");
|
||||
goto out3;
|
||||
}
|
||||
|
||||
ret = gpio_get_value(65) << 1 | gpio_get_value(1);
|
||||
|
||||
out3:
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0));
|
||||
gpio_free(1);
|
||||
out2:
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0));
|
||||
gpio_free(65);
|
||||
out:
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* Routine: get_board_mem_timings
|
||||
* Description: If we use SPL then there is no x-loader nor config header
|
||||
* so we have to setup the DDR timings ourself on both banks.
|
||||
*/
|
||||
void get_board_mem_timings(struct board_sdrc_timings *timings)
|
||||
{
|
||||
#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
|
||||
/*
|
||||
* Switch baseboard LED to red upon power-on
|
||||
*/
|
||||
MUX_OMAP3_HA();
|
||||
|
||||
/* Request a gpio before using it */
|
||||
gpio_request(111, "");
|
||||
/* Sets the gpio as output and its value to 1, switch LED to red */
|
||||
gpio_direction_output(111, 1);
|
||||
#endif
|
||||
|
||||
if (tao3530_revision() < 3) {
|
||||
/* 256MB / Bank */
|
||||
timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */
|
||||
timings->ctrla = HYNIX_V_ACTIMA_165;
|
||||
timings->ctrlb = HYNIX_V_ACTIMB_165;
|
||||
} else {
|
||||
/* 128MB / Bank */
|
||||
timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */
|
||||
timings->ctrla = MICRON_V_ACTIMA_165;
|
||||
timings->ctrlb = MICRON_V_ACTIMB_165;
|
||||
}
|
||||
|
||||
timings->mr = MICRON_V_MR_165;
|
||||
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
/* board id for Linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
|
||||
/* boot param addr */
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: misc_init_r
|
||||
* Description: Configure board specific parts
|
||||
*/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
|
||||
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
|
||||
|
||||
twl4030_power_init();
|
||||
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
|
||||
|
||||
/* Configure GPIOs to output */
|
||||
/* GPIO23 */
|
||||
writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
|
||||
writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
|
||||
GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
|
||||
|
||||
/* Set GPIOs */
|
||||
writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
|
||||
&gpio6_base->setdataout);
|
||||
writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
|
||||
GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
|
||||
|
||||
switch (tao3530_revision()) {
|
||||
case 0:
|
||||
puts("TAO-3530 REV Reserve 1\n");
|
||||
break;
|
||||
case 1:
|
||||
puts("TAO-3530 REV Reserve 2\n");
|
||||
break;
|
||||
case 2:
|
||||
puts("TAO-3530 REV Cx\n");
|
||||
break;
|
||||
case 3:
|
||||
puts("TAO-3530 REV Ax/Bx\n");
|
||||
break;
|
||||
default:
|
||||
puts("Unknown board revision\n");
|
||||
}
|
||||
|
||||
omap_die_id_display();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_TAO3530();
|
||||
#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
|
||||
MUX_OMAP3_HA();
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MMC)
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
omap_mmc_init(0, 0, 0, -1, -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MMC)
|
||||
void board_mmc_power_init(void)
|
||||
{
|
||||
twl4030_power_mmc_init(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
|
||||
/* Call usb_stop() before starting the kernel */
|
||||
void show_boot_progress(int val)
|
||||
{
|
||||
if (val == BOOTSTAGE_ID_RUN_OS)
|
||||
usb_stop();
|
||||
}
|
||||
|
||||
static struct omap_usbhs_board_data usbhs_bdata = {
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
|
||||
};
|
||||
|
||||
int ehci_hcd_init(int index, enum usb_init_type init,
|
||||
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
||||
{
|
||||
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
|
||||
}
|
||||
|
||||
int ehci_hcd_stop(int index)
|
||||
{
|
||||
return omap_ehci_hcd_stop();
|
||||
}
|
||||
#endif /* CONFIG_USB_EHCI_HCD */
|
||||
|
|
@ -1,370 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright TechNexion 2010
|
||||
* Edward Lin <linuxfae@technexion.com>
|
||||
*/
|
||||
#ifndef _TAO3530_H_
|
||||
#define _TAO3530_H_
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
DDR_STACKED,
|
||||
#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
|
||||
"HEAD acoustics OMAP3-HA",
|
||||
#else
|
||||
"OMAP3 TAO-3530 board",
|
||||
#endif
|
||||
"NAND",
|
||||
};
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_TAO3530() \
|
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
|
||||
/*DSS*/\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
|
||||
/*CAMERA*/\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \
|
||||
/* - CAM_RESET*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
|
||||
/*Audio Interface */\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
|
||||
/*Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \
|
||||
/* MMC2 WLAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
|
||||
/*Bluetooth*/\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
|
||||
/*LocalBus LAN Reset*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \
|
||||
/*LocalBus LAN IRQ*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
|
||||
/*Modem Interface */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
|
||||
/*Serial Interface*/\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) \
|
||||
/* USB EHCI (port 2) */\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \
|
||||
/*Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \
|
||||
/* - VIO_1V8*/\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M1)) \
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M1)) \
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M1)) \
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0))
|
||||
|
||||
#define MUX_OMAP3_HA() \
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /* GPIO_111 */
|
||||
|
||||
#endif
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
# CONFIG_SYS_THUMB_BUILD is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80008000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SPL_TEXT_BASE=0x40200800
|
||||
CONFIG_TARGET_TAO3530=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_SPL_FS_EXT4 is not set
|
||||
CONFIG_SPL_NAND_DRIVERS=y
|
||||
CONFIG_SPL_NAND_ECC=y
|
||||
CONFIG_SPL_NAND_SIMPLE=y
|
||||
CONFIG_SPL_NAND_BASE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_TWL4030_LED=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
CONFIG_CONS_INDEX=3
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
# CONFIG_SYS_THUMB_BUILD is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80008000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SPL_TEXT_BASE=0x40200800
|
||||
CONFIG_TARGET_TAO3530=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_SPL_FS_EXT4 is not set
|
||||
CONFIG_SPL_NAND_DRIVERS=y
|
||||
CONFIG_SPL_NAND_ECC=y
|
||||
CONFIG_SPL_NAND_SIMPLE=y
|
||||
CONFIG_SPL_NAND_BASE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="TAO-3530 # "
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_TWL4030_LED=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
CONFIG_CONS_INDEX=3
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,222 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuration settings for the TechNexion TAO-3530 SOM
|
||||
* equipped on Thunder baseboard.
|
||||
*
|
||||
* Edward Lin <linuxfae@technexion.com>
|
||||
* Tapani Utriainen <linuxfae@technexion.com>
|
||||
*
|
||||
* Copyright (C) 2013 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <asm/arch/omap.h>
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 << 20)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
||||
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
|
||||
/* commands to include */
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/*
|
||||
* TWL4030
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board NAND Info.
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
|
||||
/* to access nand at */
|
||||
/* CS0 */
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
|
||||
/* devices */
|
||||
/* Environment information */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"console=ttyO2,115200n8\0" \
|
||||
"mpurate=600\0" \
|
||||
"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
|
||||
"tv_mode=omapfb.mode=tv:ntsc\0" \
|
||||
"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
|
||||
"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
|
||||
"extra_options= \0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
"mmcrootfstype=ext3 rootwait\0" \
|
||||
"nandroot=ubi0:rootfs ubi.mtd=4\0" \
|
||||
"nandrootfstype=ubifs\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"${video_mode} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype} " \
|
||||
"${extra_options}\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"${video_mode} " \
|
||||
"${network_setting} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype} "\
|
||||
"${extra_options}\0" \
|
||||
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 280000 400000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run nandboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run nandboot; fi"
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
/* turn on command-line edit/hist/auto */
|
||||
|
||||
/* defaults */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
|
||||
/* load address */
|
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock
|
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
||||
* This rate is divided by a local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
||||
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
|
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/* **** PISMO SUPPORT *** */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
|
||||
#define CONFIG_SYS_FLASH_BASE NAND_BASE
|
||||
|
||||
/* Monitor at start of flash */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
|
||||
|
||||
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
|
||||
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* USB
|
||||
*
|
||||
* Currently only EHCI is enabled, the MUSB OTG controller
|
||||
* is not enabled.
|
||||
*/
|
||||
|
||||
/* USB EHCI */
|
||||
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
|
||||
|
||||
/* Defines for SPL */
|
||||
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
/*
|
||||
* Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
|
||||
* SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13 }
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
|
||||
/*
|
||||
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
|
||||
* older x-loader implementations. And move the BSS area so that it
|
||||
* doesn't overlap with TEXT_BASE.
|
||||
*/
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user