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https://github.com/brain-hackers/u-boot-brain
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ARM: imx: vining2000: Convert to SPL framework
In preparation for use of DDR DRAM fine-tuning upon boot, convert the board to SPL framework instead of using DCD tables to bring up DRAM and pinmux. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
df1b721f60
commit
7d84f4469f
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@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000
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select DM
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select DM_THERMAL
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select MX6SX
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_WANDBOARD
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@ -433,3 +433,185 @@ int checkboard(void)
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <linux/libfdt.h>
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#include <spl.h>
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#include <asm/arch/mx6-ddr.h>
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static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
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static iomux_v3_cfg_t const uart_pads[] = {
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MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static void vining2000_spl_setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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int board_mmc_init(bd_t *bis)
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{
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struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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u32 val;
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u32 port;
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val = readl(&src_regs->sbmr1);
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if ((val & 0xc0) != 0x40) {
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printf("Not boot from USDHC!\n");
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return -EINVAL;
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}
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port = (val >> 11) & 0x3;
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printf("port %d\n", port);
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switch (port) {
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case 3:
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imx_iomux_v3_setup_multiple_pads(
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
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break;
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}
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gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
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return fsl_esdhc_initialize(bis, &usdhc_cfg);
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000028,
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.dram_dqm1 = 0x00000028,
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.dram_dqm2 = 0x00000028,
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.dram_dqm3 = 0x00000028,
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.dram_ras = 0x00000028,
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.dram_cas = 0x00000028,
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.dram_odt0 = 0x00000028,
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.dram_odt1 = 0x00000028,
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.dram_sdba2 = 0x00000000,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdclk_0 = 0x00000030,
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.dram_sdqs0 = 0x00000028,
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.dram_sdqs1 = 0x00000028,
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.dram_sdqs2 = 0x00000028,
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.dram_sdqs3 = 0x00000028,
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.dram_reset = 0x00000028,
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};
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const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000028,
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.grp_b0ds = 0x00000028,
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.grp_b1ds = 0x00000028,
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.grp_b2ds = 0x00000028,
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.grp_b3ds = 0x00000028,
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.grp_ctlds = 0x00000028,
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode = 0x00020000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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};
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const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x0022001C,
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.p0_mpwldectrl1 = 0x001F001A,
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.p0_mpdgctrl0 = 0x01380134,
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.p0_mpdgctrl1 = 0x0124011C,
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.p0_mprddlctl = 0x42404444,
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.p0_mpwrdlctl = 0x36383C38,
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 1600,
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.density = 4,
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.width = 32,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1391,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
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writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
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writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
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writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
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writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
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writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
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writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
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}
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static void vining2000_spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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.dsize = mem_ddr.width / 32,
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.cs_density = 24,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1, /* RTT_wr = RZQ/4 */
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.rtt_nom = 1, /* RTT_Nom = RZQ/4 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 7, /* 8 refresh commands per refresh cycle */
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};
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mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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/* iomux setup */
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vining2000_spl_setup_iomux_uart();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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vining2000_spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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#endif
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@ -1,18 +1,29 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_SYS_TEXT_BASE=0x87800000
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_TARGET_SOFTING_VINING_2000=y
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CONFIG_SPL_MMC_SUPPORT=y
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x80000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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# CONFIG_CMD_BMODE is not set
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CONFIG_SPL_TEXT_BASE=0x00908000
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg"
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CONFIG_BOOTDELAY=0
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_SUPPORT_RAW_INITRD=y
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SPL_FS_EXT4=y
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CONFIG_SPL_I2C_SUPPORT=y
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CONFIG_SPL_WATCHDOG_SUPPORT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_FLASH is not set
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@ -53,7 +64,6 @@ CONFIG_DM_PCI=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_PWM_IMX=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_DM_SERIAL=y
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CONFIG_MXC_UART=y
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CONFIG_USB=y
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@ -91,4 +91,8 @@
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#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#endif
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#endif /* __CONFIG_H */
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