brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

spi: cadence_qspi: Use spi mode at the point it is needed

Browse Source 
Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Phil Edworthy 2016-11-29 12:58:31 +00:00 committed by Jagan Teki
parent 7e76c4b08a
commit 7d403f284c
3 changed files with 5 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/spi/cadence_qspi.c
View File

@ -170,14 +170,12 @@ static int cadence_spi_probe(struct udevice *bus)
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
/* Set SPI mode */
cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
/* Enable QSPI */
cadence_qspi_apb_controller_enable(priv->regbase);

3
drivers/spi/cadence_qspi.h
View File

@ -63,8 +63,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
void cadence_qspi_apb_chipselect(void *reg_base,
unsigned int chip_select, unsigned int decoder_enable);
void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
unsigned int clk_pol, unsigned int clk_pha);
void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
unsigned int ref_clk_hz, unsigned int sclk_hz);
void cadence_qspi_apb_delay(void *reg_base,

7
drivers/spi/cadence_qspi_apb.c
View File

@ -294,8 +294,7 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base,
return;
}
void cadence_qspi_apb_set_clk_mode(void *reg_base,
unsigned int clk_pol, unsigned int clk_pha)
void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
{
unsigned int reg;
@ -303,9 +302,9 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base,
reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
if (clk_pol)
if (mode & SPI_CPOL)
reg |= CQSPI_REG_CONFIG_CLK_POL;
if (clk_pha)
if (mode & SPI_CPHA)
reg |= CQSPI_REG_CONFIG_CLK_PHA;
writel(reg, reg_base + CQSPI_REG_CONFIG);