mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 21:33:24 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-sh
* 'master' of git://git.denx.de/u-boot-sh: sh: tmu: Removed arch/sh/include/asm/clk.h sh: tmu: Changed switch statement to shift operation sh: tmu: Changed TMU driver using array of structures Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
commit
7cddabce59
@ -1,35 +0,0 @@
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/*
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||||
* along with this program; if not, write to the Free Software
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||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_SH_CLK_H__
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#define __ASM_SH_CLK_H__
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static inline unsigned long get_peripheral_clk_rate(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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static inline unsigned long get_tmu0_clk_rate(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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#endif /* __ASM_SH_CLK_H__ */
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@ -41,10 +41,7 @@
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#define SCIF0_BASE SCSMR_2
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#define SCIF0_BASE SCSMR_2
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/* Timer */
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/* Timer */
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#define TSTR0 0xFFFFFE92
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#define TMU_BASE 0xFFFFFE90
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#define TSTR TSTR0
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#define TCNT0 0xFFFFFE98
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#define TCR0 0xFFFFFE9C
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/* On chip oscillator circuits */
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/* On chip oscillator circuits */
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#define WTCNT 0xFFFFFF84
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#define WTCNT 0xFFFFFF84
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@ -51,10 +51,7 @@
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#define SCIF1_BASE SCSMR_1
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#define SCIF1_BASE SCSMR_1
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/* Timer */
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/* Timer */
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#define TSTR0 0xA412FE92
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#define TMU_BASE 0xA412FE90
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#define TSTR TSTR0
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#define TCNT0 0xa412FE98
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#define TCR0 0xa412FE9C
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/* On chip oscillator circuits */
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/* On chip oscillator circuits */
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#define FRQCR 0xA415FF80
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#define FRQCR 0xA415FF80
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@ -105,16 +105,6 @@
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/* TMU */
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/* TMU */
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#define TMU_BASE 0xA412FE90
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#define TMU_BASE 0xA412FE90
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#define TSTR (TMU_BASE + 0x02)
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#define TCOR0 (TMU_BASE + 0x04)
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#define TCNT0 (TMU_BASE + 0x08)
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#define TCR0 (TMU_BASE + 0x0C)
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#define TCOR1 (TMU_BASE + 0x10)
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#define TCNT1 (TMU_BASE + 0x14)
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#define TCR1 (TMU_BASE + 0x18)
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#define TCOR2 (TMU_BASE + 0x1C)
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#define TCNT2 (TMU_BASE + 0x20)
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#define TCR2 (TMU_BASE + 0x24)
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/* TPU */
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/* TPU */
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#define TPU_BASE 0xA4480000
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#define TPU_BASE 0xA4480000
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@ -226,16 +226,7 @@
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/* TMU */
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/* TMU */
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#define TSTR 0xFFD80004
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#define TMU_BASE 0xFFD80000
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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#define TCR0 0xFFD80010
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#define TCOR1 0xFFD80014
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#define TCNT1 0xFFD80018
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#define TCR1 0xFFD8001C
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#define TCOR2 0xFFD80020
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#define TCNT2 0xFFD80024
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#define TCR2 0xFFD80028
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/* TPU */
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/* TPU */
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#define TPU_TSTR 0xA4C90000
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#define TPU_TSTR 0xA4C90000
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@ -95,16 +95,7 @@
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#define WTCNT RWTCNT
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#define WTCNT RWTCNT
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/* TMU */
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/* TMU */
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#define TSTR 0xFFD80004
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#define TMU_BASE 0xFFD80000
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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#define TCR0 0xFFD80010
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#define TCOR1 0xFFD80014
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#define TCNT1 0xFFD80018
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#define TCR1 0xFFD8001C
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#define TCOR2 0xFFD80020
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#define TCNT2 0xFFD80024
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#define TCR2 0xFFD80028
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/* TPU */
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/* TPU */
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@ -116,16 +116,7 @@
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#define WTCNT RWTCNT
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#define WTCNT RWTCNT
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/* TMU */
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/* TMU */
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#define TSTR 0xFFD80004
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#define TMU_BASE 0xFFD80000
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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#define TCR0 0xFFD80010
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#define TCOR1 0xFFD80014
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#define TCNT1 0xFFD80018
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#define TCR1 0xFFD8001C
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#define TCOR2 0xFFD80020
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#define TCNT2 0xFFD80024
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#define TCR2 0xFFD80028
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/* TPU */
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/* TPU */
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@ -36,9 +36,7 @@
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#define SCIF5_BASE 0xFFE45000
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#define SCIF5_BASE 0xFFE45000
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/* Timer */
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/* Timer */
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#define TSTR 0xFFD80004
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#define TMU_BASE 0xFFD80000
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#define TCNT0 0xFFD8000C
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#define TCR0 0xFFD80010
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/* PFC */
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/* PFC */
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#define PMMR (0xFFFC0000)
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#define PMMR (0xFFFC0000)
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@ -143,26 +143,7 @@
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#define CLKSTPCLR 0xFE0A0008
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#define CLKSTPCLR 0xFE0A0008
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/* TMU */
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/* TMU */
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#define TSTR2 0xFE100004
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#define TMU_BASE 0xFFD80000
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#define TCOR3 0xFE100008
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#define TCNT3 0xFE10000C
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#define TCR3 0xFE100010
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#define TCOR4 0xFE100014
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#define TCNT4 0xFE100018
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#define TCR4 0xFE10001C
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#define TOCR 0xFFD80000
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#define TSTR0 0xFFD80004
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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#define TCR0 0xFFD80010
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#define TCOR1 0xFFD80014
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#define TCNT1 0xFFD80018
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#define TCR1 0xFFD8001C
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#define TCOR2 0xFFD80020
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#define TCNT2 0xFFD80024
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#define TCR2 0xFFD80028
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#define TCPR2 0xFFD8002C
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#define TSTR TSTR0
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/* SCI */
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/* SCI */
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#define SCSMR1 0xFFE00000
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#define SCSMR1 0xFFE00000
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@ -51,19 +51,7 @@ struct mmu_regs {
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#define SMR0 0xfe470000
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#define SMR0 0xfe470000
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/* TMU0 */
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/* TMU0 */
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#define TSTR 0xFE430004
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#define TMU_BASE 0xFE430000
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#define TOCR 0xFE430000
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#define TSTR0 0xFE430004
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#define TCOR0 0xFE430008
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#define TCNT0 0xFE43000C
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#define TCR0 0xFE430010
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#define TCOR1 0xFE430014
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#define TCNT1 0xFE430018
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#define TCR1 0xFE43001C
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#define TCOR2 0xFE430020
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#define TCNT2 0xFE430024
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#define TCR2 0xFE430028
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#define TCPR2 0xFE43002C
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/* ETHER, GETHER MAC address */
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/* ETHER, GETHER MAC address */
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struct ether_mac_regs {
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struct ether_mac_regs {
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@ -43,9 +43,6 @@
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#define WDTST 0xFFCC0000
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#define WDTST 0xFFCC0000
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/* TMU */
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/* TMU */
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#define TSTR 0xFFD80004
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#define TMU_BASE 0xFFD80000
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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#define TCR0 0xFFD80010
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#endif /* _ASM_CPU_SH7763_H_ */
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#endif /* _ASM_CPU_SH7763_H_ */
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@ -272,29 +272,7 @@
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#define MSTPCR 0xFFC80030
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#define MSTPCR 0xFFC80030
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/* Timer Unit */
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/* Timer Unit */
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#define TSTR TSTR0
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#define TMU_BASE 0xFFD80000
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#define TOCR 0xFFD80000
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#define TSTR0 0xFFD80004
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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||||||
#define TCR0 0xFFD80010
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||||||
#define TCOR1 0xFFD80014
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#define TCNT1 0xFFD80018
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#define TCR1 0xFFD8001C
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#define TCOR2 0xFFD80020
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#define TCNT2 0xFFD80024
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#define TCR2 0xFFD80028
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#define TCPR2 0xFFD8002C
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#define TSTR1 0xFFDC0004
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#define TCOR3 0xFFDC0008
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#define TCNT3 0xFFDC000C
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#define TCR3 0xFFDC0010
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#define TCOR4 0xFFDC0014
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#define TCNT4 0xFFDC0018
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#define TCR4 0xFFDC001C
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#define TCOR5 0xFFDC0020
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#define TCNT5 0xFFDC0024
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#define TCR5 0xFFDC0028
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/* Timer/Counter */
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/* Timer/Counter */
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#define CMTCFG 0xFFE30000
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#define CMTCFG 0xFFE30000
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@ -46,29 +46,7 @@
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#define WDTBCNT 0xFFCC0018
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#define WDTBCNT 0xFFCC0018
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||||||
|
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/* Timer Unit */
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/* Timer Unit */
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#define TSTR TSTR0
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#define TMU_BASE 0xFFD80000
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#define TOCR 0xFFD80000
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#define TSTR0 0xFFD80004
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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|
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#define TCR0 0xFFD80010
|
|
||||||
#define TCOR1 0xFFD80014
|
|
||||||
#define TCNT1 0xFFD80018
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|
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#define TCR1 0xFFD8001C
|
|
||||||
#define TCOR2 0xFFD80020
|
|
||||||
#define TCNT2 0xFFD80024
|
|
||||||
#define TCR2 0xFFD80028
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|
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#define TCPR2 0xFFD8002C
|
|
||||||
#define TSTR1 0xFFDC0004
|
|
||||||
#define TCOR3 0xFFDC0008
|
|
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#define TCNT3 0xFFDC000C
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|
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#define TCR3 0xFFDC0010
|
|
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#define TCOR4 0xFFDC0014
|
|
||||||
#define TCNT4 0xFFDC0018
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|
||||||
#define TCR4 0xFFDC001C
|
|
||||||
#define TCOR5 0xFFDC0020
|
|
||||||
#define TCNT5 0xFFDC0024
|
|
||||||
#define TCR5 0xFFDC0028
|
|
||||||
|
|
||||||
/* Serial Communication Interface with FIFO */
|
/* Serial Communication Interface with FIFO */
|
||||||
#define SCIF1_BASE 0xffeb0000
|
#define SCIF1_BASE 0xffeb0000
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
* (C) Copyright 2009
|
* (C) Copyright 2009
|
||||||
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||||
*
|
*
|
||||||
* (C) Copyright 2007-2010
|
* (C) Copyright 2007-2012
|
||||||
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
*
|
*
|
||||||
* (C) Copyright 2003
|
* (C) Copyright 2003
|
||||||
@ -30,71 +30,54 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <div64.h>
|
#include <div64.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/clk.h>
|
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
#include <sh_tmu.h>
|
||||||
|
|
||||||
#define TMU_MAX_COUNTER (~0UL)
|
static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
|
||||||
|
|
||||||
static ulong timer_freq;
|
static u16 bit;
|
||||||
static unsigned long last_tcnt;
|
static unsigned long last_tcnt;
|
||||||
static unsigned long long overflow_ticks;
|
static unsigned long long overflow_ticks;
|
||||||
|
|
||||||
|
unsigned long get_tbclk(void)
|
||||||
|
{
|
||||||
|
return get_tmu0_clk_rate() >> ((bit + 1) * 2);
|
||||||
|
}
|
||||||
|
|
||||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||||
{
|
{
|
||||||
tick *= CONFIG_SYS_HZ;
|
tick *= CONFIG_SYS_HZ;
|
||||||
do_div(tick, timer_freq);
|
do_div(tick, get_tbclk());
|
||||||
|
|
||||||
return tick;
|
return tick;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline unsigned long long usec_to_tick(unsigned long long usec)
|
static inline unsigned long long usec_to_tick(unsigned long long usec)
|
||||||
{
|
{
|
||||||
usec *= timer_freq;
|
usec *= get_tbclk();
|
||||||
do_div(usec, 1000000);
|
do_div(usec, 1000000);
|
||||||
|
|
||||||
return usec;
|
return usec;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tmu_timer_start (unsigned int timer)
|
static void tmu_timer_start(unsigned int timer)
|
||||||
{
|
{
|
||||||
if (timer > 2)
|
if (timer > 2)
|
||||||
return;
|
return;
|
||||||
writeb(readb(TSTR) | (1 << timer), TSTR);
|
writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tmu_timer_stop (unsigned int timer)
|
static void tmu_timer_stop(unsigned int timer)
|
||||||
{
|
{
|
||||||
if (timer > 2)
|
if (timer > 2)
|
||||||
return;
|
return;
|
||||||
writeb(readb(TSTR) & ~(1 << timer), TSTR);
|
writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
|
||||||
}
|
}
|
||||||
|
|
||||||
int timer_init (void)
|
int timer_init(void)
|
||||||
{
|
{
|
||||||
/* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
|
bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
|
||||||
u16 bit = 0;
|
writew(readw(&tmu->tcr0) | bit, &tmu->tcr0);
|
||||||
|
|
||||||
switch (CONFIG_SYS_TMU_CLK_DIV) {
|
|
||||||
case 1024:
|
|
||||||
bit = 4;
|
|
||||||
break;
|
|
||||||
case 256:
|
|
||||||
bit = 3;
|
|
||||||
break;
|
|
||||||
case 64:
|
|
||||||
bit = 2;
|
|
||||||
break;
|
|
||||||
case 16:
|
|
||||||
bit = 1;
|
|
||||||
break;
|
|
||||||
case 4:
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
writew(readw(TCR0) | bit, TCR0);
|
|
||||||
|
|
||||||
/* Calc clock rate */
|
|
||||||
timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
|
|
||||||
|
|
||||||
tmu_timer_stop(0);
|
tmu_timer_stop(0);
|
||||||
tmu_timer_start(0);
|
tmu_timer_start(0);
|
||||||
@ -105,9 +88,9 @@ int timer_init (void)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned long long get_ticks (void)
|
unsigned long long get_ticks(void)
|
||||||
{
|
{
|
||||||
unsigned long tcnt = 0 - readl(TCNT0);
|
unsigned long tcnt = 0 - readl(&tmu->tcnt0);
|
||||||
|
|
||||||
if (last_tcnt > tcnt) /* overflow */
|
if (last_tcnt > tcnt) /* overflow */
|
||||||
overflow_ticks++;
|
overflow_ticks++;
|
||||||
@ -116,7 +99,7 @@ unsigned long long get_ticks (void)
|
|||||||
return (overflow_ticks << 32) | tcnt;
|
return (overflow_ticks << 32) | tcnt;
|
||||||
}
|
}
|
||||||
|
|
||||||
void __udelay (unsigned long usec)
|
void __udelay(unsigned long usec)
|
||||||
{
|
{
|
||||||
unsigned long long tmp;
|
unsigned long long tmp;
|
||||||
ulong tmo;
|
ulong tmo;
|
||||||
@ -128,13 +111,20 @@ void __udelay (unsigned long usec)
|
|||||||
/*NOP*/;
|
/*NOP*/;
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned long get_timer (unsigned long base)
|
unsigned long get_timer(unsigned long base)
|
||||||
{
|
{
|
||||||
/* return msec */
|
/* return msec */
|
||||||
return tick_to_time(get_ticks()) - base;
|
return tick_to_time(get_ticks()) - base;
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned long get_tbclk (void)
|
void set_timer(unsigned long t)
|
||||||
{
|
{
|
||||||
return timer_freq;
|
writel((0 - t), &tmu->tcnt0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void reset_timer(void)
|
||||||
|
{
|
||||||
|
tmu_timer_stop(0);
|
||||||
|
set_timer(0);
|
||||||
|
tmu_timer_start(0);
|
||||||
}
|
}
|
||||||
|
75
include/sh_tmu.h
Normal file
75
include/sh_tmu.h
Normal file
@ -0,0 +1,75 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __SH_TMU_H
|
||||||
|
#define __SH_TMU_H
|
||||||
|
|
||||||
|
#include <asm/types.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_SH3)
|
||||||
|
struct tmu_regs {
|
||||||
|
u8 tocr;
|
||||||
|
u8 reserved0;
|
||||||
|
u8 tstr;
|
||||||
|
u8 reserved1;
|
||||||
|
u32 tcor0;
|
||||||
|
u32 tcnt0;
|
||||||
|
u16 tcr0;
|
||||||
|
u16 reserved2;
|
||||||
|
u32 tcor1;
|
||||||
|
u32 tcnt1;
|
||||||
|
u16 tcr1;
|
||||||
|
u16 reserved3;
|
||||||
|
u32 tcor2;
|
||||||
|
u32 tcnt2;
|
||||||
|
u16 tcr2;
|
||||||
|
u16 reserved4;
|
||||||
|
u32 tcpr2;
|
||||||
|
};
|
||||||
|
#endif /* CONFIG_SH3 */
|
||||||
|
|
||||||
|
#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
|
||||||
|
struct tmu_regs {
|
||||||
|
u32 reserved;
|
||||||
|
u8 tstr;
|
||||||
|
u8 reserved2[3];
|
||||||
|
u32 tcor0;
|
||||||
|
u32 tcnt0;
|
||||||
|
u16 tcr0;
|
||||||
|
u16 reserved3;
|
||||||
|
u32 tcor1;
|
||||||
|
u32 tcnt1;
|
||||||
|
u16 tcr1;
|
||||||
|
u16 reserved4;
|
||||||
|
u32 tcor2;
|
||||||
|
u32 tcnt2;
|
||||||
|
u16 tcr2;
|
||||||
|
u16 reserved5;
|
||||||
|
};
|
||||||
|
#endif /* CONFIG_SH4 */
|
||||||
|
|
||||||
|
static inline unsigned long get_tmu0_clk_rate(void)
|
||||||
|
{
|
||||||
|
return CONFIG_SYS_CLK_FREQ;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __SH_TMU_H */
|
Loading…
Reference in New Issue
Block a user