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https://github.com/brain-hackers/u-boot-brain
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arm: dts: k3-j7200: Add R5 specific dts support
Add the basic a72 basic dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication - LPDDR with 1600MTs configuration. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This commit is contained in:
Dave Gerlach
Lokesh Vutla
parent
a7551cf05d
commit
7cc9855f31
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@ -956,7 +956,8 @@ dtb-$(CONFIG_STM32MP15x) += \
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dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
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dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
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k3-j721e-r5-common-proc-board.dtb \
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k3-j7200-common-proc-board.dtb
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k3-j7200-common-proc-board.dtb \
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k3-j7200-r5-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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2195
arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
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2195
arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
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File diff suppressed because it is too large
Load Diff
199
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
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199
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
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@ -0,0 +1,199 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j7200-som-p0.dtsi"
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#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
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#include "k3-j721e-ddr.dtsi"
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/ {
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a72_0;
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};
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chosen {
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stdout-path = &main_uart0;
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tick-timer = &timer1;
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};
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a72_0: a72@0 {
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compatible = "ti,am654-rproc";
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reg = <0x0 0x00a90000 0x0 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 202 0>;
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assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
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assigned-clock-rates = <2000000000>, <200000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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u-boot,dm-spl;
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};
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clk_200mhz: dummy_clock_200mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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u-boot,dm-spl;
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};
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clk_19_2mhz: dummy_clock_19_2mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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u-boot,dm-spl;
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};
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};
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&memorycontroller {
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power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
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<&k3_pds 90 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
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};
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&cbass_mcu_wakeup {
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mcu_secproxy: secproxy@2a380000 {
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u-boot,dm-spl;
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compatible = "ti,am654-secure-proxy";
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reg = <0x0 0x2a380000 0x0 0x80000>,
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<0x0 0x2a400000 0x0 0x80000>,
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<0x0 0x2a480000 0x0 0x80000>;
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reg-names = "rt", "scfg", "target_data";
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#mbox-cells = <1>;
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};
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sysctrler: sysctrler {
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u-boot,dm-spl;
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compatible = "ti,am654-system-controller";
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mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
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mbox-names = "tx", "rx";
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};
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};
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&dmsc {
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mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
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mbox-names = "tx", "rx", "notify";
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ti,host-id = <4>;
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ti,secure-host;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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wkup_uart0_pins_default: wkup_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
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J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
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>;
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};
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mcu_uart0_pins_default: mcu_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
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J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
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J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */
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J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */
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>;
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};
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wkup_i2c0_pins_default: wkup-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
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J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
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>;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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main_uart0_pins_default: main_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
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J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
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J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
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J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
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>;
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};
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main_i2c0_pins_default: main-i2c0-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
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J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
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>;
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};
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};
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&wkup_uart0 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_uart0_pins_default>;
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status = "okay";
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};
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&mcu_uart0 {
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/delete-property/ power-domains;
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/delete-property/ clocks;
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/delete-property/ clock-names;
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_uart0_pins_default>;
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status = "okay";
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clock-frequency = <96000000>;
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};
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&main_uart0 {
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status = "okay";
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&main_sdhci0 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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non-removable;
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bus-width = <8>;
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};
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&main_sdhci1 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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exp2: gpio@22 {
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compatible = "ti,tca6424";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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#include "k3-j7200-common-proc-board-u-boot.dtsi"
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