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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

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This commit is contained in:
Tom Rini 2015-09-24 12:28:02 -04:00
commit 7bb839d672
154 changed files with 4074 additions and 1637 deletions
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5
arch/arm/dts/Makefile
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@ -45,8 +45,11 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
uniphier-ph1-pro5-4kbox.dtb \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-sld8-ref.dtb
uniphier-ph1-sld8-ref.dtb \
uniphier-proxstream2-gentil.dtb \
uniphier-proxstream2-vodka.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \

18
arch/arm/dts/uniphier-ph1-ld4-ref.dts
View File

@ -61,6 +61,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

19
arch/arm/dts/uniphier-ph1-ld6b-ref.dts
View File

@ -3,6 +3,7 @@
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
@ -54,6 +55,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/uniphier-ph1-pro4-ref.dts
View File

@ -68,6 +68,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

64
arch/arm/dts/uniphier-ph1-pro5-4kbox.dts Normal file
View File

@ -0,0 +1,64 @@
/*
* Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "uniphier-ph1-pro5.dtsi"
/ {
model = "UniPhier PH1-Pro5 4KBOX Board";
compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
chosen {
bootargs = "console=ttyS1,115200";
stdout-path = &serial1;
};
aliases {
serial1 = &serial1;
serial2 = &serial2;
i2c0 = &i2c0;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
};
&serial1 {
status = "okay";
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
/* for U-boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial1 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/uniphier-ph1-sld8-ref.dts
View File

@ -65,6 +65,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

38
arch/arm/dts/uniphier-pinctrl.dtsi
View File

@ -3,43 +3,7 @@
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* SPDX-License-Identifier: GPL-2.0+ X11
*/
&pinctrl {

62
arch/arm/dts/uniphier-proxstream2-gentil.dts Normal file
View File

@ -0,0 +1,62 @@
/*
* Device Tree Source for UniPhier ProXstream2 Gentil Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "uniphier-proxstream2.dtsi"
/ {
model = "UniPhier ProXstream2 Gentil Board";
compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
chosen {
bootargs = "console=ttyS2,115200";
stdout-path = &serial2;
};
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
i2c0 = &i2c0;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
/* for U-boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial2 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};

62
arch/arm/dts/uniphier-proxstream2-vodka.dts Normal file
View File

@ -0,0 +1,62 @@
/*
* Device Tree Source for UniPhier ProXstream2 Vodka Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "uniphier-proxstream2.dtsi"
/ {
model = "UniPhier ProXstream2 Vodka Board";
compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
chosen {
bootargs = "console=ttyS2,115200";
stdout-path = &serial2;
};
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
i2c0 = &i2c0;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
/* for U-boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial2 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};

113
arch/arm/mach-uniphier/Kconfig
View File

@ -6,49 +6,68 @@ config SYS_CONFIG_NAME
config UNIPHIER_SMP
bool
choice
prompt "UniPhier SoC select"
default MACH_PH1_PRO4
config MACH_PH1_SLD3
bool "PH1-sLD3"
config ARCH_UNIPHIER_PH1_SLD3
bool "UniPhier PH1-sLD3 SoC"
select UNIPHIER_SMP
config MACH_PH1_LD4
bool "PH1-LD4"
config MACH_PH1_PRO4
bool "PH1-Pro4"
select UNIPHIER_SMP
config MACH_PH1_SLD8
bool "PH1-sLD8"
endchoice
choice
prompt "UniPhier Support Card select"
optional
config PFC_MICRO_SUPPORT_CARD
bool "Support card with PFC CPLD"
help
This option provides support for the expansion board with PFC
original address mapping.
This enables support for UniPhier PH1-sLD3 SoC.
config ARCH_UNIPHIER_PH1_LD4
bool "UniPhier PH1-LD4 SoC"
depends on !ARCH_UNIPHIER_PH1_SLD3
help
This enables support for UniPhier PH1-LD4 SoC.
config ARCH_UNIPHIER_PH1_PRO4
bool "UniPhier PH1-Pro4 SoC"
select UNIPHIER_SMP
depends on !ARCH_UNIPHIER_PH1_SLD3 && \
!ARCH_UNIPHIER_PH1_LD4 && \
!ARCH_UNIPHIER_PH1_SLD8
help
This enables support for UniPhier PH1-Pro4 SoC.
config ARCH_UNIPHIER_PH1_SLD8
bool "UniPhier PH1-sLD8 SoC"
depends on !ARCH_UNIPHIER_PH1_SLD3
help
This enables support for UniPhier PH1-sLD8 SoC.
config ARCH_UNIPHIER_PH1_PRO5
bool "UniPhier PH1-Pro5 SoC"
select UNIPHIER_SMP
depends on !ARCH_UNIPHIER_PH1_SLD3 && \
!ARCH_UNIPHIER_PH1_LD4 && \
!ARCH_UNIPHIER_PH1_SLD8
help
This enables support for UniPhier PH1-Pro5 SoC.
config ARCH_UNIPHIER_PROXSTREAM2
bool "UniPhier ProXstream2 SoC"
select UNIPHIER_SMP
depends on !ARCH_UNIPHIER_PH1_SLD3 && \
!ARCH_UNIPHIER_PH1_LD4 && \
!ARCH_UNIPHIER_PH1_SLD8
help
This enables support for UniPhier ProXstream2 SoC.
config ARCH_UNIPHIER_PH1_LD6B
bool "UniPhier PH1-LD6b SoC"
select UNIPHIER_SMP
depends on !ARCH_UNIPHIER_PH1_SLD3 && \
!ARCH_UNIPHIER_PH1_LD4 && \
!ARCH_UNIPHIER_PH1_SLD8
help
This enables support for UniPhier PH1-LD6b SoC.
config MICRO_SUPPORT_CARD
bool "Use Micro Support Card"
help
This option provides support for the expansion board, available
on some UniPhier reference boards.
Say Y to use the on-board UART, Ether, LED devices.
config DCC_MICRO_SUPPORT_CARD
bool "Support card with DCC CPLD"
help
This option provides support for the expansion board with DCC-
arranged address mapping that is compatible with legacy UniPhier
reference boards.
Say Y to use the on-board UART, Ether, LED devices.
endchoice
config CMD_PINMON
bool "Enable boot mode pins monitor command"
default y
@ -63,22 +82,4 @@ config CMD_DDRPHY_DUMP
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
choice
prompt "DDR3 Frequency select"
config DDR_FREQ_1600
bool "DDR3 1600"
depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
config DDR_FREQ_1333
bool "DDR3 1333"
depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
endchoice
config DDR_FREQ
int
default 1333 if DDR_FREQ_1333
default 1600 if DDR_FREQ_1600
endif

21
arch/arm/mach-uniphier/Makefile
View File

@ -6,9 +6,12 @@ ifdef CONFIG_SPL_BUILD
obj-y += lowlevel_init.o
obj-y += init_page_table.o
obj-y += spl.o
obj-y += memconf.o
obj-y += ddrphy_training.o
obj-y += boards.o
obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
obj-$(CONFIG_DEBUG_LL) += debug_ll.o
else
@ -25,14 +28,12 @@ obj-y += cache_uniphier.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
obj-y += pinctrl/ clk/
endif
obj-y += timer.o
obj-y += soc_info.o
obj-y += boot-mode/
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o

3
arch/arm/mach-uniphier/bcu/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o

8
arch/arm/mach-uniphier/ph1-ld4/bcu_init.c → arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
View File

@ -4,13 +4,13 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/bcu-regs.h>
#include <mach/init.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
void bcu_init(void)
int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
{
int shift;
@ -21,7 +21,7 @@ void bcu_init(void)
writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
/* Specify DDR channel */
shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
@ -29,4 +29,6 @@ void bcu_init(void)
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
return 0;
}

8
arch/arm/mach-uniphier/ph1-sld3/bcu_init.c → arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
View File

@ -4,13 +4,13 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/bcu-regs.h>
#include <mach/init.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
void bcu_init(void)
int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
{
int shift;
@ -25,7 +25,7 @@ void bcu_init(void)
writel(0x24440000, BCSCR5);
/* Specify DDR channel */
shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
@ -33,4 +33,6 @@ void bcu_init(void)
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
return 0;
}

23
arch/arm/mach-uniphier/board_common.c
View File

@ -1,32 +1,15 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mach/led.h>
#include <mach/micro-support-card.h>
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
led_write(U, B, O, O);
led_puts("Uboo");
return 0;
}
#if CONFIG_NR_DRAM_BANKS >= 2
void dram_init_banksize(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
}
#endif

73
arch/arm/mach-uniphier/board_early_init_f.c
View File

@ -1,27 +1,72 @@
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/led.h>
#include <mach/board.h>
void pin_init(void);
void clkrst_init(void);
#include <mach/init.h>
#include <mach/micro-support-card.h>
#include <mach/soc_info.h>
int board_early_init_f(void)
{
led_write(U, 0, , );
led_puts("U0");
pin_init();
switch (uniphier_get_soc_type()) {
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
case SOC_UNIPHIER_PH1_SLD3:
ph1_sld3_pin_init();
led_puts("U1");
ph1_ld4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
case SOC_UNIPHIER_PH1_LD4:
ph1_ld4_pin_init();
led_puts("U1");
ph1_ld4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
case SOC_UNIPHIER_PH1_PRO4:
ph1_pro4_pin_init();
led_puts("U1");
ph1_pro4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
case SOC_UNIPHIER_PH1_SLD8:
ph1_sld8_pin_init();
led_puts("U1");
ph1_ld4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
case SOC_UNIPHIER_PH1_PRO5:
ph1_pro5_pin_init();
led_puts("U1");
ph1_pro5_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
case SOC_UNIPHIER_PROXSTREAM2:
proxstream2_pin_init();
led_puts("U1");
proxstream2_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
case SOC_UNIPHIER_PH1_LD6B:
ph1_ld6b_pin_init();
led_puts("U1");
proxstream2_clk_init();
break;
#endif
default:
break;
}
led_write(U, 1, , );
clkrst_init();
led_write(U, 2, , );
led_puts("U2");
return 0;
}

7
arch/arm/mach-uniphier/board_early_init_r.c
View File

@ -1,15 +1,14 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mach/board.h>
#include <mach/micro-support-card.h>
int board_early_init_r(void)
{
uniphier_board_late_init();
support_card_late_init();
return 0;
}

130
arch/arm/mach-uniphier/boards.c Normal file
View File

@ -0,0 +1,130 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <libfdt.h>
#include <linux/kernel.h>
#include <mach/init.h>
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
static const struct uniphier_board_data ph1_sld3_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x20000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xc0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 16,
.dram_ch2_base = 0xc0000000,
.dram_ch2_size = 0x10000000,
.dram_ch2_width = 16,
.dram_freq = 1600,
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
static const struct uniphier_board_data ph1_ld4_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x10000000,
.dram_ch0_width = 16,
.dram_ch1_base = 0x90000000,
.dram_ch1_size = 0x10000000,
.dram_ch1_width = 16,
.dram_freq = 1600,
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
static const struct uniphier_board_data ph1_pro4_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x20000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xa0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 32,
.dram_freq = 1600,
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
static const struct uniphier_board_data ph1_sld8_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x10000000,
.dram_ch0_width = 16,
.dram_ch1_base = 0x90000000,
.dram_ch1_size = 0x10000000,
.dram_ch1_width = 16,
.dram_freq = 1333,
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
static const struct uniphier_board_data ph1_pro5_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x20000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xa0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 32,
.dram_freq = 1866,
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
static const struct uniphier_board_data proxstream2_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x40000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xc0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 32,
.dram_ch2_base = 0xe0000000,
.dram_ch2_size = 0x20000000,
.dram_ch2_width = 16,
.dram_freq = 1866,
};
#endif
struct uniphier_board_id {
const char *compatible;
const struct uniphier_board_data *param;
};
static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
{ "socionext,ph1-sld3", &ph1_sld3_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
{ "socionext,ph1-ld4", &ph1_ld4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
{ "socionext,ph1-pro4", &ph1_pro4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
{ "socionext,ph1-sld8", &ph1_sld8_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
{ "socionext,ph1-pro5", &ph1_pro5_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
{ "socionext,proxstream2", &proxstream2_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
{ "socionext,ph1-ld6b", &proxstream2_data, },
#endif
};
const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
{
int i;
for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
if (!fdt_node_check_compatible(fdt, 0,
uniphier_boards[i].compatible))
return uniphier_boards[i].param;
}
return NULL;
}

9
arch/arm/mach-uniphier/boot-mode/Makefile Normal file
View File

@ -0,0 +1,9 @@
obj-y += boot-mode.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += boot-mode-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += boot-mode-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o

21
arch/arm/mach-uniphier/ph1-pro4/boot-mode.c → arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c
View File

@ -44,22 +44,31 @@ struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{ /* sentinel */ }
};
int get_boot_mode_sel(void)
static int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 spl_boot_device(void)
u32 ph1_ld4_boot_device(void)
{
int boot_mode;
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
void ph1_ld4_boot_mode_show(void)
{
int mode_sel, i;
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
boot_device_table[i].info);
}

75
arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c Normal file
View File

@ -0,0 +1,75 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <mach/boot-device.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{ /* sentinel */ }
};
static int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 ph1_pro5_boot_device(void)
{
int boot_mode;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
void ph1_pro5_boot_mode_show(void)
{
int mode_sel, i;
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
boot_device_table[i].info);
}

23
arch/arm/mach-uniphier/ph1-sld3/boot-mode.c → arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c
View File

@ -11,7 +11,7 @@
#include <mach/sg-regs.h>
#include <mach/sbc-regs.h>
struct boot_device_info boot_device_table[] = {
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "External Master"},
{BOOT_DEVICE_NONE, "Reserved"},
@ -76,22 +76,31 @@ struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{ /* sentinel */ }
};
int get_boot_mode_sel(void)
static int get_boot_mode_sel(void)
{
return readl(SG_PINMON0) & 0x3f;
}
u32 spl_boot_device(void)
u32 ph1_sld3_boot_device(void)
{
int boot_mode;
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
void ph1_sld3_boot_mode_show(void)
{
int mode_sel, i;
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
boot_device_table[i].info);
}

75
arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c Normal file
View File

@ -0,0 +1,75 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <mach/boot-device.h>
#include <mach/init.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
{BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
{BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
{BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
{BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
{BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
{BOOT_DEVICE_NONE, "Reserved"},
};
int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 proxstream2_boot_device(void)
{
int boot_mode;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
void proxstream2_boot_mode_show(void)
{
int mode_sel, i;
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
boot_device_table[i].info);
}

45
arch/arm/mach-uniphier/boot-mode/boot-mode.c Normal file
View File

@ -0,0 +1,45 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <mach/boot-device.h>
#include <mach/sbc-regs.h>
#include <mach/soc_info.h>
u32 spl_boot_device(void)
{
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
switch (uniphier_get_soc_type()) {
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
case SOC_UNIPHIER_PH1_SLD3:
return ph1_sld3_boot_device();
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
case SOC_UNIPHIER_PH1_LD4:
case SOC_UNIPHIER_PH1_PRO4:
case SOC_UNIPHIER_PH1_SLD8:
return ph1_ld4_boot_device();
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
case SOC_UNIPHIER_PH1_PRO5:
return ph1_pro5_boot_device();
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
case SOC_UNIPHIER_PROXSTREAM2:
case SOC_UNIPHIER_PH1_LD6B:
return proxstream2_boot_device();
#endif
default:
return BOOT_DEVICE_NONE;
}
}

7
arch/arm/mach-uniphier/clk/Makefile Normal file
View File

@ -0,0 +1,7 @@
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += clk-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += clk-ph1-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += clk-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += clk-proxstream2.o

3
arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c → arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
View File

@ -5,9 +5,10 @@
*/
#include <linux/io.h>
#include <mach/init.h>
#include <mach/sc-regs.h>
void clkrst_init(void)
void ph1_ld4_clk_init(void)
{
u32 tmp;

3
arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c → arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
View File

@ -5,9 +5,10 @@
*/
#include <linux/io.h>
#include <mach/init.h>
#include <mach/sc-regs.h>
void clkrst_init(void)
void ph1_pro4_clk_init(void)
{
u32 tmp;

44
arch/arm/mach-uniphier/clk/clk-ph1-pro5.c Normal file
View File

@ -0,0 +1,44 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/init.h>
#include <mach/sc-regs.h>
void ph1_pro5_clk_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp = readl(SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
writel(tmp, SC_RSTCTRL2);
readl(SC_RSTCTRL2); /* dummy read */
#endif
/* privide clocks */
tmp = readl(SC_CLKCTRL);
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

50
arch/arm/mach-uniphier/clk/clk-proxstream2.c Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/init.h>
#include <mach/sc-regs.h>
void proxstream2_clk_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp = readl(SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
writel(tmp, SC_RSTCTRL2);
readl(SC_RSTCTRL2); /* dummy read */
#endif
/* privide clocks */
tmp = readl(SC_CLKCTRL);
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

43
arch/arm/mach-uniphier/cmd_pinmon.c
View File

@ -1,6 +1,5 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -8,20 +7,42 @@
#include <common.h>
#include <mach/boot-device.h>
#include <mach/sbc-regs.h>
#include <mach/soc_info.h>
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int mode_sel, i;
printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (i = 0; boot_device_table[i].info; i++)
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
boot_device_table[i].info);
switch (uniphier_get_soc_type()) {
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
case SOC_UNIPHIER_PH1_SLD3:
ph1_sld3_boot_mode_show();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
case SOC_UNIPHIER_PH1_LD4:
case SOC_UNIPHIER_PH1_PRO4:
case SOC_UNIPHIER_PH1_SLD8:
ph1_ld4_boot_mode_show();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
case SOC_UNIPHIER_PH1_PRO5:
ph1_pro5_boot_mode_show();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
case SOC_UNIPHIER_PROXSTREAM2:
case SOC_UNIPHIER_PH1_LD6B:
proxstream2_boot_mode_show();
break;
#endif
default:
break;
}
return 0;
}

3
arch/arm/mach-uniphier/ddrphy/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o

4
arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c → arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c
View File

@ -8,7 +8,7 @@
#include <linux/io.h>
#include <mach/ddrphy-regs.h>
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
u32 tmp;
@ -67,4 +67,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
return 0;
}

4
arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c → arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c
View File

@ -8,7 +8,7 @@
#include <linux/io.h>
#include <mach/ddrphy-regs.h>
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
u32 tmp;
@ -67,4 +67,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
return 0;
}

4
arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c → arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
View File

@ -9,7 +9,7 @@
#include <linux/io.h>
#include <mach/ddrphy-regs.h>
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
u32 tmp;
@ -72,4 +72,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
return 0;
}

0
arch/arm/mach-uniphier/ddrphy_training.c → arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
View File

185
arch/arm/mach-uniphier/debug_ll.S Normal file
View File

@ -0,0 +1,185 @@
/*
* On-chip UART initializaion for low-level debugging
*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/serial_reg.h>
#include <linux/linkage.h>
#include <mach/bcu-regs.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
#endif
#define BAUDRATE 115200
#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
ENTRY(debug_ll_init)
ldr r0, =SG_REVISION
ldr r1, [r0]
and r1, r1, #SG_REVISION_TYPE_MASK
mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
#define PH1_SLD3_UART_CLK 36864000
cmp r1, #0x25
bne ph1_sld3_end
sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
ldr r0, =BCSCR5
ldr r1, =0x24440000
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
b init_uart
ph1_sld3_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
#define PH1_LD4_UART_CLK 36864000
cmp r1, #0x26
bne ph1_ld4_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
b init_uart
ph1_ld4_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
#define PH1_PRO4_UART_CLK 73728000
cmp r1, #0x28
bne ph1_pro4_end
sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
ldr r0, =SG_LOADPINCTRL
mov r1, #1
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
b init_uart
ph1_pro4_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define PH1_SLD8_UART_CLK 80000000
cmp r1, #0x29
bne ph1_sld8_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
b init_uart
ph1_sld8_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
#define PH1_PRO5_UART_CLK 73728000
cmp r1, #0x2A
bne ph1_pro5_end
sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
ldr r0, =SG_LOADPINCTRL
mov r1, #1
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
b init_uart
ph1_pro5_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
#define PROXSTREAM2_UART_CLK 88900000
cmp r1, #0x2E
bne proxstream2_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
b init_uart
proxstream2_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
#define PH1_LD6B_UART_CLK 88900000
cmp r1, #0x2F
bne ph1_ld6b_end
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
b init_uart
ph1_ld6b_end:
#endif
init_uart:
addruart r0, r1, r2
mov r1, #UART_LCR_WLEN8 << 8
str r1, [r0, #0x10]
str r3, [r0, #0x24]
mov pc, lr
ENDPROC(debug_ll_init)

51
arch/arm/mach-uniphier/dram_init.c
View File

@ -1,16 +1,59 @@
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <libfdt.h>
#include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR;
static const void *get_memory_reg_prop(const void *fdt, int *lenp)
{
int offset;
offset = fdt_path_offset(fdt, "/memory");
if (offset < 0)
return NULL;
return fdt_getprop(fdt, offset, "reg", lenp);
}
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
const fdt32_t *val;
int len;
val = get_memory_reg_prop(gd->fdt_blob, &len);
if (len < sizeof(*val))
return -EINVAL;
gd->ram_size = fdt32_to_cpu(*(val + 1));
debug("DRAM size = %08lx\n", gd->ram_size);
return 0;
}
void dram_init_banksize(void)
{
const fdt32_t *val;
int len, i;
val = get_memory_reg_prop(gd->fdt_blob, &len);
if (len < 0)
return;
len /= sizeof(*val);
len /= 2;
for (i = 0; i < len; i++) {
gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
debug("DRAM bank %d: start = %08lx, size = %08lx\n",
i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
}
}

7
arch/arm/mach-uniphier/early-clk/Makefile Normal file
View File

@ -0,0 +1,7 @@
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += early-clk-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += early-clk-ph1-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += early-clk-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += early-clk-proxstream2.o

5
arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c → arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
View File

@ -7,9 +7,10 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <mach/init.h>
#include <mach/sc-regs.h>
void early_clkrst_init(void)
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
{
u32 tmp;
@ -27,4 +28,6 @@ void early_clkrst_init(void)
tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
return 0;
}

39
arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c Normal file
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@ -0,0 +1,39 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/init.h>
#include <mach/sc-regs.h>
int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
{
u32 tmp;
/*
* deassert reset
* UMCA2: Ch1 (DDR3)
* UMCA1, UMC31: Ch0 (WIO1)
* UMCA0, UMC30: Ch0 (WIO0)
*/
tmp = readl(SC_RSTCTRL4);
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
writel(tmp, SC_RSTCTRL4);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
tmp = readl(SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
SC_CLKCTRL4_CEN_UMC0;
writel(tmp, SC_CLKCTRL4);
readl(SC_CLKCTRL4); /* dummy read */
return 0;
}

44
arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c Normal file
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@ -0,0 +1,44 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <mach/init.h>
#include <mach/sc-regs.h>
int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
{
u32 tmp;
/* deassert reset */
if (spl_boot_device() != BOOT_DEVICE_NAND) {
tmp = readl(SC_RSTCTRL);
tmp &= ~SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
};
tmp = readl(SC_RSTCTRL4);
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
SC_RSTCTRL4_NRST_UMC30;
writel(tmp, SC_RSTCTRL4);
readl(SC_RSTCTRL4); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
tmp = readl(SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
writel(tmp, SC_CLKCTRL4);
readl(SC_CLKCTRL4); /* dummy read */
return 0;
}

1
arch/arm/mach-uniphier/early-pinctrl/Makefile Normal file
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@ -0,0 +1 @@
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o

26
arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/init.h>
#include <mach/sg-regs.h>
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
#endif
return 0;
}

42
arch/arm/mach-uniphier/include/mach/board.h
View File

@ -1,42 +0,0 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_BOARD_H
#define ARCH_BOARD_H
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
void support_card_late_init(void);
int check_support_card(void);
#else
#define support_card_reset() do {} while (0)
#define support_card_init() do {} while (0)
#define support_card_late_init() do {} while (0)
static inline int check_support_card(void)
{
return 0;
}
#endif
static inline void uniphier_board_reset(void)
{
support_card_reset();
}
static inline void uniphier_board_init(void)
{
support_card_init();
}
static inline void uniphier_board_late_init(void)
{
support_card_late_init();
}
#endif /* ARCH_BOARD_H */

15
arch/arm/mach-uniphier/include/mach/boot-device.h
View File

@ -1,6 +1,5 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -8,13 +7,19 @@
#ifndef _ASM_BOOT_DEVICE_H_
#define _ASM_BOOT_DEVICE_H_
int get_boot_mode_sel(void);
struct boot_device_info {
u32 type;
char *info;
};
extern struct boot_device_info boot_device_table[];
u32 ph1_sld3_boot_device(void);
u32 ph1_ld4_boot_device(void);
u32 ph1_pro5_boot_device(void);
u32 proxstream2_boot_device(void);
void ph1_sld3_boot_mode_show(void);
void ph1_ld4_boot_mode_show(void);
void ph1_pro5_boot_mode_show(void);
void proxstream2_boot_mode_show(void);
#endif /* _ASM_BOOT_DEVICE_H_ */

7
arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
View File

@ -156,7 +156,8 @@ struct ddrphy {
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define NR_DDRPHY_PER_CH 1
#else
#define NR_DDRPHY_PER_CH 2
@ -167,7 +168,9 @@ struct ddrphy {
#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
#ifndef __ASSEMBLY__
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif

23
arch/arm/mach-uniphier/include/mach/debug-uart.S
View File

@ -1,23 +0,0 @@
/*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/serial_reg.h>
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
#endif
#define BAUDRATE 115200
#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE)
.macro init_debug_uart, ra, rb, rc
addruart \ra, \rb, \rc
mov \rb, #UART_LCR_WLEN8 << 8
str \rb, [\ra, #0x10]
ldr \rb, =DIVISOR
str \rb, [\ra, #0x24]
.endm

99
arch/arm/mach-uniphier/include/mach/init.h Normal file
View File

@ -0,0 +1,99 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_INIT_H
#define __MACH_INIT_H
struct uniphier_board_data {
unsigned long dram_ch0_base;
unsigned long dram_ch0_size;
unsigned long dram_ch0_width;
unsigned long dram_ch1_base;
unsigned long dram_ch1_size;
unsigned long dram_ch1_width;
unsigned long dram_ch2_base;
unsigned long dram_ch2_size;
unsigned long dram_ch2_width;
unsigned int dram_freq;
};
const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
int ph1_sld3_init(const struct uniphier_board_data *bd);
int ph1_ld4_init(const struct uniphier_board_data *bd);
int ph1_pro4_init(const struct uniphier_board_data *bd);
int ph1_sld8_init(const struct uniphier_board_data *bd);
int ph1_pro5_init(const struct uniphier_board_data *bd);
int proxstream2_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
int proxstream2_sbc_init(const struct uniphier_board_data *bd);
#else
static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
{
return 0;
}
static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
{
return 0;
}
static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
{
return 0;
}
static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
{
return 0;
}
#endif
int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
int memconf_init(const struct uniphier_board_data *bd);
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
int proxstream2_memconf_init(const struct uniphier_board_data *bd);
int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
void ph1_sld3_pin_init(void);
void ph1_ld4_pin_init(void);
void ph1_pro4_pin_init(void);
void ph1_sld8_pin_init(void);
void ph1_pro5_pin_init(void);
void proxstream2_pin_init(void);
void ph1_ld6b_pin_init(void);
void ph1_ld4_clk_init(void);
void ph1_pro4_clk_init(void);
void ph1_pro5_clk_init(void);
void proxstream2_clk_init(void);
#define pr_err(fmt, args...) printf(fmt, ##args)
#endif /* __MACH_INIT_H */

100
arch/arm/mach-uniphier/include/mach/led.h
View File

@ -1,100 +0,0 @@
/*
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_LED_H
#define ARCH_LED_H
#include <config.h>
#define LED_CHAR_0 0x7e
#define LED_CHAR_1 0x0c
#define LED_CHAR_2 0xb6
#define LED_CHAR_3 0x9e
#define LED_CHAR_4 0xcc
#define LED_CHAR_5 0xda
#define LED_CHAR_6 0xfa
#define LED_CHAR_7 0x4e
#define LED_CHAR_8 0xfe
#define LED_CHAR_9 0xde
#define LED_CHAR_A 0xee
#define LED_CHAR_B 0xf8
#define LED_CHAR_C 0x72
#define LED_CHAR_D 0xbc
#define LED_CHAR_E 0xf2
#define LED_CHAR_F 0xe2
#define LED_CHAR_G 0x7a
#define LED_CHAR_H 0xe8
#define LED_CHAR_I 0x08
#define LED_CHAR_J 0x3c
#define LED_CHAR_K 0xea
#define LED_CHAR_L 0x70
#define LED_CHAR_M 0x6e
#define LED_CHAR_N 0xa8
#define LED_CHAR_O 0xb8
#define LED_CHAR_P 0xe6
#define LED_CHAR_Q 0xce
#define LED_CHAR_R 0xa0
#define LED_CHAR_S 0xc8
#define LED_CHAR_T 0x8c
#define LED_CHAR_U 0x7c
#define LED_CHAR_V 0x54
#define LED_CHAR_W 0xfc
#define LED_CHAR_X 0xec
#define LED_CHAR_Y 0xdc
#define LED_CHAR_Z 0xa4
#define LED_CHAR_SPACE 0x00
#define LED_CHAR_DOT 0x01
#define LED_CHAR_ (LED_CHAR_SPACE)
/** Macro to translate 4 characters into integer to display led */
#define LED_C2I(C0, C1, C2, C3) \
(~( \
(LED_CHAR_##C0 << 24) | \
(LED_CHAR_##C1 << 16) | \
(LED_CHAR_##C2 << 8) | \
(LED_CHAR_##C3) \
))
#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE
#ifdef __ASSEMBLY__
#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3)
.macro raw_led_write data
ldr r0, =\data
ldr r1, =LED_ADDR
str r0, [r1]
.endm
#else /* __ASSEMBLY__ */
#include <linux/io.h>
#define led_write(C0, C1, C2, C3) \
do { \
raw_led_write(LED_C2I(C0, C1, C2, C3)); \
} while (0)
static inline void raw_led_write(u32 data)
{
writel(data, LED_ADDR);
}
#endif /* __ASSEMBLY__ */
#else /* CONFIG_SUPPORT_CARD_LED_BASE */
#define led_write(C0, C1, C2, C3)
#define raw_led_write(x)
#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
#endif /* ARCH_LED_H */

39
arch/arm/mach-uniphier/include/mach/micro-support-card.h Normal file
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@ -0,0 +1,39 @@
/*
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_BOARD_H
#define ARCH_BOARD_H
#if defined(CONFIG_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
void support_card_late_init(void);
int check_support_card(void);
void led_puts(const char *s);
#else
static inline void support_card_reset(void)
{
}
static inline void support_card_init(void)
{
}
static inline void support_card_late_init(void)
{
}
static inline int check_support_card(void)
{
return 0;
}
static inline void led_puts(const char *s)
{
}
#endif
#endif /* ARCH_BOARD_H */

24
arch/arm/mach-uniphier/include/mach/platdevice.h
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@ -1,24 +0,0 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_PLATDEVICE_H
#define ARCH_PLATDEVICE_H
#include <dm/platdata.h>
#include <dm/platform_data/serial-uniphier.h>
#define SERIAL_DEVICE(n, ba, clk) \
static struct uniphier_serial_platform_data serial_device##n = { \
.base = ba, \
.uartclk = clk \
}; \
U_BOOT_DEVICE(serial##n) = { \
.name = DRIVER_NAME, \
.platdata = &serial_device##n \
};
#endif /* ARCH_PLATDEVICE_H */

25
arch/arm/mach-uniphier/include/mach/sc-regs.h
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@ -9,12 +9,16 @@
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
#if defined(CONFIG_MACH_PH1_SLD3)
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
#define SC_BASE_ADDR 0xf1840000
#else
#define SC_BASE_ADDR 0x61840000
#endif
#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
@ -43,6 +47,7 @@
#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
/* Pro4 or older */
#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
@ -53,6 +58,16 @@
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
/* Pro5 or newer */
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
@ -60,11 +75,19 @@
#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
/* Pro4 or older */
#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
/* Pro5 or newer */
#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
/* System reset control register */
#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)

50
arch/arm/mach-uniphier/include/mach/sg-regs.h
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@ -25,53 +25,43 @@
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
/* PH1-LD6b, ProXstream2 only */
#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
#if defined(CONFIG_MACH_PH1_PRO4)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
defined(CONFIG_MACH_PH1_SLD8)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
#endif
#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4)
#define SG_PINSELBITS 4
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#define SG_PINSELBITS 8
#endif
#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
((n) * (SG_PINSELBITS) % 32)))
#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
/* Only for PH1-Pro4 */
/* PH1-Pro4, PH1-Pro5 */
#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
/* Input Enable */
@ -98,11 +88,11 @@
#ifdef __ASSEMBLY__
.macro set_pinsel, n, value, ra, rd
ldr \ra, =SG_PINSEL_ADDR(\n)
.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
ldr \rd, [\ra]
and \rd, \rd, #SG_PINSEL_MASK(\n)
orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
str \rd, [\ra]
.endm
@ -111,10 +101,18 @@
#include <linux/types.h>
#include <linux/io.h>
static inline void sg_set_pinsel(int n, int value)
static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
unsigned mux_bits, unsigned reg_stride)
{
writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
| SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
unsigned shift = pin * mux_bits % 32;
unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
u32 mask = (1U << mux_bits) - 1;
u32 tmp;
tmp = readl(reg);
tmp &= ~(mask << shift);
tmp |= (mask & muxval) << shift;
writel(tmp, reg);
}
#endif /* __ASSEMBLY__ */

63
arch/arm/mach-uniphier/include/mach/soc_info.h Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_SOC_INFO_H__
#define __MACH_SOC_INFO_H__
enum uniphier_soc_id {
SOC_UNIPHIER_PH1_SLD3,
SOC_UNIPHIER_PH1_LD4,
SOC_UNIPHIER_PH1_PRO4,
SOC_UNIPHIER_PH1_SLD8,
SOC_UNIPHIER_PH1_PRO5,
SOC_UNIPHIER_PROXSTREAM2,
SOC_UNIPHIER_PH1_LD6B,
SOC_UNIPHIER_UNKNOWN,
};
#define UNIPHIER_NR_ENABLED_SOCS \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
#if UNIPHIER_MULTI_SOC
enum uniphier_soc_id uniphier_get_soc_type(void);
#else
static inline enum uniphier_soc_id uniphier_get_soc_type(void)
{
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
return SOC_UNIPHIER_PH1_SLD3;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
return SOC_UNIPHIER_PH1_LD4;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
return SOC_UNIPHIER_PH1_PRO4;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
return SOC_UNIPHIER_PH1_SLD8;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
return SOC_UNIPHIER_PH1_PRO5;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
return SOC_UNIPHIER_PROXSTREAM2;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
return SOC_UNIPHIER_PH1_LD6B;
#endif
return SOC_UNIPHIER_UNKNOWN;
}
#endif
#endif /* __MACH_SOC_INFO_H__ */

9
arch/arm/mach-uniphier/init/Makefile Normal file
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@ -0,0 +1,9 @@
obj-y += init.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += init-ph1-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += init-ph1-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += init-ph1-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += init-ph1-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += init-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += init-proxstream2.o

60
arch/arm/mach-uniphier/init/init-ph1-ld4.c Normal file
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@ -0,0 +1,60 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/compiler.h>
#include <mach/init.h>
#include <mach/micro-support-card.h>
int ph1_ld4_init(const struct uniphier_board_data *bd)
{
ph1_ld4_bcu_init(bd);
ph1_ld4_sbc_init(bd);
support_card_reset();
ph1_ld4_pll_init(bd);
support_card_init();
led_puts("L0");
memconf_init(bd);
led_puts("L1");
ph1_ld4_early_clk_init(bd);
led_puts("L2");
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L4");
{
int res;
res = ph1_ld4_umc_init(bd);
if (res < 0) {
while (1)
;
}
}
led_puts("L5");
ph1_ld4_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

58
arch/arm/mach-uniphier/init/init-ph1-pro4.c Normal file
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@ -0,0 +1,58 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/compiler.h>
#include <mach/init.h>
#include <mach/micro-support-card.h>
int ph1_pro4_init(const struct uniphier_board_data *bd)
{
ph1_pro4_sbc_init(bd);
support_card_reset();
ph1_pro4_pll_init(bd);
support_card_init();
led_puts("L0");
memconf_init(bd);
led_puts("L1");
ph1_ld4_early_clk_init(bd);
led_puts("L2");
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L4");
{
int res;
res = ph1_pro4_umc_init(bd);
if (res < 0) {
while (1)
;
}
}
led_puts("L5");
ph1_ld4_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

42
arch/arm/mach-uniphier/init/init-ph1-pro5.c Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/compiler.h>
#include <mach/init.h>
#include <mach/micro-support-card.h>
int ph1_pro5_init(const struct uniphier_board_data *bd)
{
ph1_pro4_sbc_init(bd);
support_card_reset();
support_card_init();
led_puts("L0");
memconf_init(bd);
led_puts("L1");
ph1_pro5_early_clk_init(bd);
led_puts("L2");
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L4");
led_puts("L5");
return 0;
}

53
arch/arm/mach-uniphier/init/init-ph1-sld3.c Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/compiler.h>
#include <mach/init.h>
#include <mach/micro-support-card.h>
int ph1_sld3_init(const struct uniphier_board_data *bd)
{
ph1_sld3_bcu_init(bd);
ph1_sld3_sbc_init(bd);
support_card_reset();
ph1_sld3_pll_init(bd);
support_card_init();
led_puts("L0");
memconf_init(bd);
ph1_sld3_memconf_init(bd);
led_puts("L1");
ph1_ld4_early_clk_init(bd);
led_puts("L2");
ph1_sld3_early_pin_init(bd);
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L4");
led_puts("L5");
ph1_sld3_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

60
arch/arm/mach-uniphier/init/init-ph1-sld8.c Normal file
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@ -0,0 +1,60 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/compiler.h>
#include <mach/init.h>
#include <mach/micro-support-card.h>
int ph1_sld8_init(const struct uniphier_board_data *bd)
{
ph1_ld4_bcu_init(bd);
ph1_ld4_sbc_init(bd);
support_card_reset();
ph1_sld8_pll_init(bd);
support_card_init();
led_puts("L0");
memconf_init(bd);
led_puts("L1");
ph1_ld4_early_clk_init(bd);
led_puts("L2");
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L4");
{
int res;
res = ph1_sld8_umc_init(bd);
if (res < 0) {
while (1)
;
}
}
led_puts("L5");
ph1_ld4_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

41
arch/arm/mach-uniphier/init/init-proxstream2.c Normal file
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@ -0,0 +1,41 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/compiler.h>
#include <mach/init.h>
#include <mach/micro-support-card.h>
int proxstream2_init(const struct uniphier_board_data *bd)
{
proxstream2_sbc_init(bd);
support_card_reset();
support_card_init();
led_puts("L0");
memconf_init(bd);
proxstream2_memconf_init(bd);
led_puts("L1");
proxstream2_early_clk_init(bd);
led_puts("L2");
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L4");
return 0;
}

58
arch/arm/mach-uniphier/init/init.c Normal file
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@ -0,0 +1,58 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <mach/init.h>
#include <mach/soc_info.h>
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
const struct uniphier_board_data *param;
param = uniphier_get_board_param(gd->fdt_blob);
if (!param)
hang();
switch (uniphier_get_soc_type()) {
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
case SOC_UNIPHIER_PH1_SLD3:
ph1_sld3_init(param);
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
case SOC_UNIPHIER_PH1_LD4:
ph1_ld4_init(param);
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
case SOC_UNIPHIER_PH1_PRO4:
ph1_pro4_init(param);
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
case SOC_UNIPHIER_PH1_SLD8:
ph1_sld8_init(param);
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
case SOC_UNIPHIER_PH1_PRO5:
ph1_pro5_init(param);
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
case SOC_UNIPHIER_PROXSTREAM2:
case SOC_UNIPHIER_PH1_LD6B:
proxstream2_init(param);
break;
#endif
default:
break;
}
}

6
arch/arm/mach-uniphier/init_page_table.S
View File

@ -1,7 +1,5 @@
/*
* Copyright (C) 2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -23,7 +21,7 @@
ENTRY(init_page_table)
section = 0
.rept NR_SECTIONS
.if section == TEXT_SECTION || section == STACK_SECTION
.if section == 0 || section == 1 || section == STACK_SECTION
attr = NORMAL
.else
attr = DEVICE

3
arch/arm/mach-uniphier/lowlevel_init.S
View File

@ -8,7 +8,6 @@
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
#include <mach/led.h>
#include <mach/arm-mpcore.h>
#include <mach/sbc-regs.h>
#include <mach/ssc-regs.h>
@ -28,7 +27,7 @@ ENTRY(lowlevel_init)
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_DEBUG_LL
bl setup_lowlevel_debug
bl debug_ll_init
#endif
/*

103
arch/arm/mach-uniphier/memconf.c
View File

@ -1,103 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/sizes.h>
#include <linux/io.h>
#include <mach/sg-regs.h>
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH0_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH0_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH0_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH0_SZ_512M;
break;
case SZ_1G:
ret = SG_MEMCONF_CH0_SZ_1G;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH0_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH0_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH1_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH1_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH1_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH1_SZ_512M;
break;
case SZ_1G:
ret = SG_MEMCONF_CH1_SZ_1G;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH1_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH1_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
void memconf_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
}

4
arch/arm/mach-uniphier/memconf/Makefile Normal file
View File

@ -0,0 +1,4 @@
obj-y += memconf.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += memconf-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += memconf-proxstream2.o

59
arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <mach/init.h>
#include <mach/sg-regs.h>
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
{
u32 tmp;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
switch (bd->dram_ch2_width) {
case 16:
tmp |= SG_MEMCONF_CH2_NUM_1;
size_per_word = bd->dram_ch2_size;
break;
case 32:
tmp |= SG_MEMCONF_CH2_NUM_2;
size_per_word = bd->dram_ch2_size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch2 width\n");
return -EINVAL;
}
/* Set DDR size */
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH2_SZ_512M;
break;
default:
pr_err("error: unsupported DRAM Ch2 size\n");
return -EINVAL;
}
writel(tmp, SG_MEMCONF);
return 0;
}

64
arch/arm/mach-uniphier/memconf/memconf-proxstream2.c Normal file
View File

@ -0,0 +1,64 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <mach/init.h>
#include <mach/sg-regs.h>
int proxstream2_memconf_init(const struct uniphier_board_data *bd)
{
u32 tmp;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
switch (bd->dram_ch2_width) {
case 16:
tmp |= SG_MEMCONF_CH2_NUM_1;
size_per_word = bd->dram_ch2_size;
break;
case 32:
tmp |= SG_MEMCONF_CH2_NUM_2;
size_per_word = bd->dram_ch2_size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch2 width\n");
return -EINVAL;
}
/* Set DDR size */
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH2_SZ_512M;
break;
default:
pr_err("error: unsupported DRAM Ch2 size\n");
return -EINVAL;
}
if (size_per_word)
tmp &= ~SG_MEMCONF_CH2_DISABLE;
else
tmp |= SG_MEMCONF_CH2_DISABLE;
writel(tmp, SG_MEMCONF);
return 0;
}

104
arch/arm/mach-uniphier/memconf/memconf.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <mach/init.h>
#include <mach/sg-regs.h>
int memconf_init(const struct uniphier_board_data *bd)
{
u32 tmp = 0;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
switch (bd->dram_ch0_width) {
case 16:
tmp |= SG_MEMCONF_CH0_NUM_1;
size_per_word = bd->dram_ch0_size;
break;
case 32:
tmp |= SG_MEMCONF_CH0_NUM_2;
size_per_word = bd->dram_ch0_size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch0 width\n");
return -EINVAL;
}
/* Set DDR size */
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH0_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH0_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH0_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH0_SZ_512M;
break;
case SZ_1G:
tmp |= SG_MEMCONF_CH0_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM Ch0 size\n");
return -EINVAL;
}
tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
switch (bd->dram_ch1_width) {
case 16:
tmp |= SG_MEMCONF_CH1_NUM_1;
size_per_word = bd->dram_ch1_size;
break;
case 32:
tmp |= SG_MEMCONF_CH1_NUM_2;
size_per_word = bd->dram_ch1_size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch1 width\n");
return -EINVAL;
}
switch (size_per_word) {
case SZ_64M:
tmp |= SG_MEMCONF_CH1_SZ_64M;
break;
case SZ_128M:
tmp |= SG_MEMCONF_CH1_SZ_128M;
break;
case SZ_256M:
tmp |= SG_MEMCONF_CH1_SZ_256M;
break;
case SZ_512M:
tmp |= SG_MEMCONF_CH1_SZ_512M;
break;
case SZ_1G:
tmp |= SG_MEMCONF_CH1_SZ_1G;
break;
default:
pr_err("error: unsupported DRAM Ch1 size\n");
return -EINVAL;
}
if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
tmp |= SG_MEMCONF_SPARSEMEM;
else
tmp &= ~SG_MEMCONF_SPARSEMEM;
writel(tmp, SG_MEMCONF);
return 0;
}

169
arch/arm/mach-uniphier/support_card.c → arch/arm/mach-uniphier/micro-support-card.c
View File

@ -5,15 +5,17 @@
*/
#include <common.h>
#include <linux/ctype.h>
#include <linux/io.h>
#include <mach/board.h>
#include <mach/micro-support-card.h>
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
#define MICRO_SUPPORT_CARD_BASE 0x43f00000
#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
#define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
#define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
#define PFC_MICRO_SUPPORT_CARD_RESET \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
#define PFC_MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
/*
* 0: reset deassert, 1: reset
*
@ -22,65 +24,22 @@
*/
void support_card_reset_deassert(void)
{
writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
writel(0, MICRO_SUPPORT_CARD_RESET);
}
void support_card_reset(void)
{
writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
writel(3, MICRO_SUPPORT_CARD_RESET);
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
revision = readl(MICRO_SUPPORT_CARD_REVISION);
printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
return 0;
}
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
#define DCC_MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
void support_card_reset_deassert(void)
{
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
void support_card_reset(void)
{
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
if (revision >= 0x67) {
printf("(DCC CPLD version 3.%d.%d)\n",
revision >> 4, revision & 0xf);
return 0;
} else {
printf("(DCC CPLD unknown version)\n");
return -1;
}
}
#endif
int check_support_card(void)
{
@ -104,7 +63,7 @@ void support_card_init(void)
int board_eth_init(bd_t *bis)
{
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
return smc911x_initialize(0, SMC911X_BASE);
}
#endif
@ -146,28 +105,11 @@ static int mem_is_flash(const struct memory_bank *mem)
return ret;
}
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
/* {address, size} */
static const struct memory_bank memory_banks_boot_swap_off[] = {
{0x02000000, 0x01f00000},
/* {address, size} */
static const struct memory_bank memory_banks[] = {
{0x42000000, 0x01f00000},
};
static const struct memory_bank memory_banks_boot_swap_on[] = {
{0x00000000, 0x01f00000},
};
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
static const struct memory_bank memory_banks_boot_swap_off[] = {
{0x04000000, 0x02000000},
};
static const struct memory_bank memory_banks_boot_swap_on[] = {
{0x00000000, 0x02000000},
{0x04000000, 0x02000000},
};
#endif
static const struct memory_bank
*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
@ -187,13 +129,8 @@ static void detect_num_flash_banks(void)
cfi_flash_num_flash_banks = 0;
if (boot_is_swapped()) {
memory_bank = memory_banks_boot_swap_on;
end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
} else {
memory_bank = memory_banks_boot_swap_off;
end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
}
memory_bank = memory_banks;
end = memory_bank + ARRAY_SIZE(memory_banks);
for (; memory_bank < end; memory_bank++) {
if (cfi_flash_num_flash_banks >=
@ -222,3 +159,73 @@ void support_card_late_init(void)
{
detect_num_flash_banks();
}
static const u8 ledval_num[] = {
0x7e, /* 0 */
0x0c, /* 1 */
0xb6, /* 2 */
0x9e, /* 3 */
0xcc, /* 4 */
0xda, /* 5 */
0xfa, /* 6 */
0x4e, /* 7 */
0xfe, /* 8 */
0xde, /* 9 */
};
static const u8 ledval_alpha[] = {
0xee, /* A */
0xf8, /* B */
0x72, /* C */
0xbc, /* D */
0xf2, /* E */
0xe2, /* F */
0x7a, /* G */
0xe8, /* H */
0x08, /* I */
0x3c, /* J */
0xea, /* K */
0x70, /* L */
0x6e, /* M */
0xa8, /* N */
0xb8, /* O */
0xe6, /* P */
0xce, /* Q */
0xa0, /* R */
0xc8, /* S */
0x8c, /* T */
0x7c, /* U */
0x54, /* V */
0xfc, /* W */
0xec, /* X */
0xdc, /* Y */
0xa4, /* Z */
};
static u8 char2ledval(char c)
{
if (isdigit(c))
return ledval_num[c - '0'];
else if (isalpha(c))
return ledval_alpha[toupper(c) - 'A'];
return 0;
}
void led_puts(const char *s)
{
int i;
u32 val = 0;
if (!s)
return;
for (i = 0; i < 4; i++) {
val <<= 8;
val |= char2ledval(*s);
if (*s != '\0')
s++;
}
writel(~val, LED_BASE);
}

15
arch/arm/mach-uniphier/ph1-ld4/Makefile
View File

@ -1,15 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
endif
obj-y += boot-mode.o

1
arch/arm/mach-uniphier/ph1-ld4/boot-mode.c
View File

@ -1 +0,0 @@
#include "../ph1-pro4/boot-mode.c"

1
arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c
View File

@ -1 +0,0 @@
#include "../ph1-pro4/early_clkrst_init.c"

27
arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
View File

@ -1,27 +0,0 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/sg-regs.h>
void early_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
#endif
}

29
arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S
View File

@ -1,29 +0,0 @@
/*
* On-chip UART initializaion for low-level debugging
*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
#include <mach/sg-regs.h>
#define UART_CLK 36864000
#include <mach/debug-uart.S>
ENTRY(setup_lowlevel_debug)
init_debug_uart r0, r1, r2
/* UART Port 0 */
set_pinsel 85, 1, r0, r1
set_pinsel 88, 1, r0, r1
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
mov pc, lr
ENDPROC(setup_lowlevel_debug)

48
arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
View File

@ -1,48 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/sg-regs.h>
void pin_init(void)
{
u32 tmp;
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
/* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
/* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
#endif
tmp = readl(SG_IECTRL);
tmp |= 0x41;
writel(tmp, SG_IECTRL);
}

1
arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c
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@ -1 +0,0 @@
#include "../ph1-pro4/pll_spectrum.c"

49
arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
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@ -1,49 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
u32 tmp;
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE3);
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}

18
arch/arm/mach-uniphier/ph1-ld4/sg_init.c
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@ -1,18 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
}

15
arch/arm/mach-uniphier/ph1-pro4/Makefile
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@ -1,15 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += sg_init.o pll_init.o early_clkrst_init.o \
early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
endif
obj-y += boot-mode.o

26
arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
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@ -1,26 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/sg-regs.h>
void early_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
#endif
writel(1, SG_LOADPINCTRL);
}

39
arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
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@ -1,39 +0,0 @@
/*
* On-chip UART initializaion for low-level debugging
*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#define UART_CLK 73728000
#include <mach/debug-uart.S>
ENTRY(setup_lowlevel_debug)
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
init_debug_uart r0, r1, r2
/* UART Port 0 */
set_pinsel 127, 0, r0, r1
set_pinsel 128, 0, r0, r1
ldr r0, =SG_LOADPINCTRL
mov r1, #1
str r1, [r0]
ldr r0, =SG_IECTRL
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
mov pc, lr
ENDPROC(setup_lowlevel_debug)

49
arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
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@ -1,49 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/sg-regs.h>
void pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
sg_set_pinsel(48, 0); /* NFALE -> NFALE */
sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
/* sg_set_pinsel(131, 1); */ /* RXD2 -> NRYBY1 */
/* sg_set_pinsel(132, 1); */ /* TXD2 -> XNFCE1 */
#endif
#ifdef CONFIG_USB_XHCI_UNIPHIER
sg_set_pinsel(180, 0); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(181, 0); /* USB0OD -> USB0OD */
sg_set_pinsel(182, 0); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(183, 0); /* USB1OD -> USB1OD */
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
#endif
writel(1, SG_LOADPINCTRL);
}

42
arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
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@ -1,42 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0400bc01, SBBASE1); /* sub memory */
writel(0x0800bf01, SBBASE3); /* peripherals */
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
writel(0x00000001, SG_LOADPINCTRL);
}

18
arch/arm/mach-uniphier/ph1-pro4/sg_init.c
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@ -1,18 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include <mach/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 1 << 6;
writel(tmp, SG_IECTRL);
}

15
arch/arm/mach-uniphier/ph1-sld3/Makefile
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@ -1,15 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
early_pinctrl.o pll_spectrum.o umc_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
endif
obj-y += boot-mode.o

1
arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c
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@ -1 +0,0 @@
#include "../ph1-pro4/clkrst_init.c"

1
arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c
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@ -1 +0,0 @@
#include "../ph1-pro4/early_clkrst_init.c"

23
arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c
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@ -1,23 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/sg-regs.h>
void early_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(63, 0); /* RXD0 */
sg_set_pinsel(64, 1); /* TXD0 */
sg_set_pinsel(65, 0); /* RXD1 */
sg_set_pinsel(66, 1); /* TXD1 */
sg_set_pinsel(96, 2); /* RXD2 */
sg_set_pinsel(102, 2); /* TXD2 */
#endif
}

33
arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
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@ -1,33 +0,0 @@
/*
* On-chip UART initializaion for low-level debugging
*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
#include <mach/bcu-regs.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#define UART_CLK 36864000
#include <mach/debug-uart.S>
ENTRY(setup_lowlevel_debug)
ldr r0, =BCSCR5
ldr r1, =0x24440000
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
init_debug_uart r0, r1, r2
set_pinsel 63, 0, r0, r1
set_pinsel 64, 1, r0, r1
mov pc, lr
ENDPROC(setup_lowlevel_debug)

52
arch/arm/mach-uniphier/ph1-sld3/memconf.c
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@ -1,52 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
#include <linux/sizes.h>
#include <mach/sg-regs.h>
static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH2_SZ_512M;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH2_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH2_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
u32 memconf_additional_val(void)
{
return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2);
}

24
arch/arm/mach-uniphier/ph1-sld3/pinctrl.c
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@ -1,24 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/sg-regs.h>
void pin_init(void)
{
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(13, 0); /* USB0OC */
sg_set_pinsel(14, 1); /* USB0VBUS */
sg_set_pinsel(15, 0); /* USB1OC */
sg_set_pinsel(16, 1); /* USB1VBUS */
sg_set_pinsel(17, 0); /* USB2OC */
sg_set_pinsel(18, 1); /* USB2VBUS */
sg_set_pinsel(19, 0); /* USB3OC */
sg_set_pinsel(20, 1); /* USB3VBUS */
#endif
}

37
arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
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@ -1,37 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* only address/data multiplex mode is supported */
/* XECS0 : boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
/* XECS1 : sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
/* XECS2 : peripherals */
writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE2);
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
}

9
arch/arm/mach-uniphier/ph1-sld3/sg_init.c
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@ -1,9 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
void sg_init(void)
{
}

15
arch/arm/mach-uniphier/ph1-sld3/umc_init.c
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@ -1,15 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int umc_init(void)
{
/* add UMC init code here */
printf("Implement memory init code\n");
return 0;
}

1
arch/arm/mach-uniphier/ph1-sld8/Makefile
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@ -1 +0,0 @@
include $(src)/../ph1-ld4/Makefile

1
arch/arm/mach-uniphier/ph1-sld8/bcu_init.c
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@ -1 +0,0 @@
#include "../ph1-ld4/bcu_init.c"

1
arch/arm/mach-uniphier/ph1-sld8/boot-mode.c
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@ -1 +0,0 @@
#include "../ph1-pro4/boot-mode.c"

1
arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
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@ -1 +0,0 @@
#include "../ph1-ld4/clkrst_init.c"

1
arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c
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@ -1 +0,0 @@
#include "../ph1-ld4/early_clkrst_init.c"

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