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armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

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SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.

So Avoid RCWSR28 register hard-coding.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Prabhakar Kushwaha 2017-02-15 20:40:35 +05:30 committed by York Sun
parent 1b7dba990f
commit 7b45b383fd
2 changed files with 25 additions and 12 deletions
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28
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View File

@ -51,20 +51,22 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[28]); u32 cfg = 0;
int i; int i;
switch (sd) { switch (sd) {
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
case FSL_SRDS_1: case FSL_SRDS_1:
cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
break; break;
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
case FSL_SRDS_2: case FSL_SRDS_2:
cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
break; break;
#endif #endif
default: default:
@ -83,8 +85,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
return -ENODEV; return -ENODEV;
} }
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg; u32 cfg;
@ -95,7 +97,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift; cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
@ -152,15 +154,17 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1, serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map); serdes1_prtcl_map);
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2, serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map); serdes2_prtcl_map);
#endif #endif
} }

9
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -230,10 +230,19 @@ struct ccsr_gur {
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
#if defined(CONFIG_ARCH_LS2080A)
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#endif
#define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400 #define RCW_SB_EN_MASK 0x00000400