mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ARM: dts: dra7xx: sync DT with latest Linux
Sync all dra7xx based dts files with latest Linux Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
b4b060066f
commit
7aa1a40876
27
arch/arm/dts/dra7-dspeve-thermal.dtsi
Normal file
27
arch/arm/dts/dra7-dspeve-thermal.dtsi
Normal file
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@ -0,0 +1,27 @@
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/*
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* Device Tree Source for DRA7x SoC DSPEVE thermal
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*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/thermal/thermal.h>
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dspeve_thermal: dspeve_thermal {
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polling-delay-passive = <250>; /* milliseconds */
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polling-delay = <500>; /* milliseconds */
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/* sensor ID */
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thermal-sensors = <&bandgap 3>;
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trips {
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dspeve_crit: dspeve_crit {
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temperature = <125000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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@ -9,6 +9,8 @@
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#include "dra74x.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clk/ti-dra7-atl.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "TI DRA742";
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@ -19,9 +21,9 @@
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tick-timer = &timer2;
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};
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memory {
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memory@0 {
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device_type = "memory";
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reg = <0x80000000 0x60000000>; /* 1536 MB */
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reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
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};
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evm_3v3_sd: fixedregulator-sd {
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@ -33,13 +35,23 @@
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gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
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};
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mmc2_3v3: fixedregulator-mmc2 {
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evm_3v3_sw: fixedregulator-evm_3v3_sw {
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compatible = "regulator-fixed";
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regulator-name = "mmc2_3v3";
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regulator-name = "evm_3v3_sw";
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vin-supply = <&sysen1>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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aic_dvdd: fixedregulator-aic_dvdd {
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/* TPS77018DBVT */
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compatible = "regulator-fixed";
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regulator-name = "aic_dvdd";
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vin-supply = <&evm_3v3_sw>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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extcon_usb1: extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
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@ -58,8 +70,89 @@
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regulator-always-on;
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regulator-boot-on;
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enable-active-high;
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vin-supply = <&sysen2>;
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gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
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};
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sound0: sound0 {
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compatible = "simple-audio-card";
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simple-audio-card,name = "DRA7xx-EVM";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line Out",
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"Microphone", "Mic Jack",
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"Line", "Line In";
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simple-audio-card,routing =
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"Headphone Jack", "HPLOUT",
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"Headphone Jack", "HPROUT",
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"Line Out", "LLOUT",
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"Line Out", "RLOUT",
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"MIC3L", "Mic Jack",
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"MIC3R", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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simple-audio-card,format = "dsp_b";
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simple-audio-card,bitclock-master = <&sound0_master>;
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simple-audio-card,frame-master = <&sound0_master>;
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simple-audio-card,bitclock-inversion;
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sound0_master: simple-audio-card,cpu {
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sound-dai = <&mcasp3>;
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system-clock-frequency = <5644800>;
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};
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simple-audio-card,codec {
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sound-dai = <&tlv320aic3106>;
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clocks = <&atl_clkin2_ck>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led0 {
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label = "dra7:usr1";
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gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led1 {
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label = "dra7:usr2";
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gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led2 {
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label = "dra7:usr3";
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gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led3 {
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label = "dra7:usr4";
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gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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USER1 {
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label = "btnUser1";
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linux,code = <BTN_0>;
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gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
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};
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USER2 {
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label = "btnUser2";
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linux,code = <BTN_1>;
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gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&dra7_pmx_core {
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@ -68,163 +161,149 @@
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vtt_pin: pinmux_vtt_pin {
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pinctrl-single,pins = <
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0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
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DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
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0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
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DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
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DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
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>;
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};
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i2c2_pins: pinmux_i2c2_pins {
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pinctrl-single,pins = <
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0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
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0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
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DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
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DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
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>;
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};
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i2c3_pins: pinmux_i2c3_pins {
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pinctrl-single,pins = <
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0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
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0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
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DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
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DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
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>;
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};
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mcspi1_pins: pinmux_mcspi1_pins {
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pinctrl-single,pins = <
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0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
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0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
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0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
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0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
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0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
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0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
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DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
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DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
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DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
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DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
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DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
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DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
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>;
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};
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mcspi2_pins: pinmux_mcspi2_pins {
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pinctrl-single,pins = <
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0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
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0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
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DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
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DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
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>;
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};
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
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0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
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0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
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0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
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DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
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DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
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DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
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DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
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>;
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};
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
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0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
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0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
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0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
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DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
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DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
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DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
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DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
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0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
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>;
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};
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qspi1_pins: pinmux_qspi1_pins {
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pinctrl-single,pins = <
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0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
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0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
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0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
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0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
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0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
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0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
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0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
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0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
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0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
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0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
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DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
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DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
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>;
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};
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usb1_pins: pinmux_usb1_pins {
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pinctrl-single,pins = <
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0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
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DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
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>;
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};
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usb2_pins: pinmux_usb2_pins {
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pinctrl-single,pins = <
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0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
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DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
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>;
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};
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nand_flash_x16: nand_flash_x16 {
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/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
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* So NAND flash requires following switch settings:
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* SW5.9 (GPMC_WPN) = LOW
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* SW5.1 (NAND_BOOTn) = HIGH */
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* SW5.1 (NAND_BOOTn) = ON (LOW)
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* SW5.9 (GPMC_WPN) = OFF (HIGH)
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*/
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pinctrl-single,pins = <
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0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
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0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
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0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
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0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
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0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
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0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
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0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
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DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
|
||||
DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
|
||||
DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
|
||||
DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
|
||||
DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
|
||||
DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
|
||||
DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
|
||||
0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
|
||||
0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
|
||||
0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
|
||||
0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
|
||||
0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
|
||||
0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
|
||||
0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
|
||||
0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
|
||||
0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
|
||||
0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
|
||||
0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
|
||||
DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
|
||||
DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
|
||||
DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
|
||||
DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
|
||||
DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
|
||||
DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
|
||||
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
|
||||
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
|
||||
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
|
||||
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
|
||||
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
|
||||
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
|
||||
0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
|
||||
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
|
||||
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
|
||||
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
|
||||
0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
|
||||
0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
|
||||
0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
|
||||
0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
|
||||
0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
|
||||
0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
|
||||
0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
|
||||
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
|
||||
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
|
||||
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
|
||||
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
|
||||
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
|
||||
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
|
||||
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
|
||||
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
|
||||
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
|
||||
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
|
||||
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
|
||||
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
|
||||
>;
|
||||
|
||||
};
|
||||
|
|
@ -232,60 +311,85 @@
|
|||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (MUX_MODE15)
|
||||
0x254 (MUX_MODE15)
|
||||
0x258 (MUX_MODE15)
|
||||
0x25c (MUX_MODE15)
|
||||
0x260 (MUX_MODE15)
|
||||
0x264 (MUX_MODE15)
|
||||
0x268 (MUX_MODE15)
|
||||
0x26c (MUX_MODE15)
|
||||
0x270 (MUX_MODE15)
|
||||
0x274 (MUX_MODE15)
|
||||
0x278 (MUX_MODE15)
|
||||
0x27c (MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (MUX_MODE15)
|
||||
0x19c (MUX_MODE15)
|
||||
0x1a0 (MUX_MODE15)
|
||||
0x1a4 (MUX_MODE15)
|
||||
0x1a8 (MUX_MODE15)
|
||||
0x1ac (MUX_MODE15)
|
||||
0x1b0 (MUX_MODE15)
|
||||
0x1b4 (MUX_MODE15)
|
||||
0x1b8 (MUX_MODE15)
|
||||
0x1bc (MUX_MODE15)
|
||||
0x1c0 (MUX_MODE15)
|
||||
0x1c4 (MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
|
||||
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
|
||||
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x23c (MUX_MODE15)
|
||||
0x240 (MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_sleep: dcan1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
|
||||
atl_pins: pinmux_atl_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
|
||||
DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcasp3_pins: pinmux_mcasp3_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
|
||||
DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
|
||||
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
|
||||
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
|
||||
DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -317,7 +421,7 @@
|
|||
/* VDD_DSPEVE */
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
|
@ -335,7 +439,7 @@
|
|||
/* CORE_VDD */
|
||||
regulator-name = "smps7";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1060000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
|
@ -363,6 +467,7 @@
|
|||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
|
|
@ -392,6 +497,7 @@
|
|||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
|
||||
ldoln_reg: ldoln {
|
||||
|
|
@ -410,12 +516,48 @@
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* REGEN1 is unused */
|
||||
|
||||
regen2: regen2 {
|
||||
/* Needed for PMIC internal resources */
|
||||
regulator-name = "regen2";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* REGEN3 is unused */
|
||||
|
||||
sysen1: sysen1 {
|
||||
/* PMIC_REGEN_3V3 */
|
||||
regulator-name = "sysen1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sysen2: sysen2 {
|
||||
/* PMIC_REGEN_DDR */
|
||||
regulator-name = "sysen2";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcf_lcd: gpio@20 {
|
||||
compatible = "ti,pcf8575", "nxp,pcf8575";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcf_gpio_21: gpio@21 {
|
||||
compatible = "ti,pcf8575";
|
||||
compatible = "ti,pcf8575", "nxp,pcf8575";
|
||||
reg = <0x21>;
|
||||
lines-initial-states = <0x1408>;
|
||||
gpio-controller;
|
||||
|
|
@ -427,6 +569,20 @@
|
|||
u-boot,i2c-offset-len = <0>;
|
||||
};
|
||||
|
||||
tlv320aic3106: tlv320aic3106@19 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x19>;
|
||||
adc-settle-ms = <40>;
|
||||
ai3x-micbias-vg = <1>; /* 2.0V */
|
||||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&evm_3v3_sw>;
|
||||
IOVDD-supply = <&evm_3v3_sw>;
|
||||
DRVDD-supply = <&evm_3v3_sw>;
|
||||
DVDD-supply = <&aic_dvdd>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
|
|
@ -434,6 +590,20 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pcf_hdmi: gpio@26 {
|
||||
compatible = "ti,pcf8575", "nxp,pcf8575";
|
||||
reg = <0x26>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
p1 {
|
||||
/* vin6_sel_s0: high: VIN6, low: audio */
|
||||
gpio-hog;
|
||||
gpios = <1 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "vin6_sel_s0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
|
|
@ -489,7 +659,7 @@
|
|||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc2_3v3>;
|
||||
vmmc-supply = <&evm_3v3_sw>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
|
|
@ -499,12 +669,10 @@
|
|||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi1_pins>;
|
||||
|
||||
spi-max-frequency = <76800000>;
|
||||
m25p80@0 {
|
||||
compatible = "s25fl256s1","spi-flash";
|
||||
compatible = "s25fl256s1", "spi-flash";
|
||||
spi-max-frequency = <76800000>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
|
|
@ -588,9 +756,14 @@
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x16>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
|
|
@ -613,7 +786,6 @@
|
|||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
|
|
@ -710,3 +882,64 @@
|
|||
pinctrl-1 = <&dcan1_pins_sleep>;
|
||||
pinctrl-2 = <&dcan1_pins_default>;
|
||||
};
|
||||
|
||||
&atl {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&atl_pins>;
|
||||
|
||||
assigned-clocks = <&abe_dpll_sys_clk_mux>,
|
||||
<&atl_gfclk_mux>,
|
||||
<&dpll_abe_ck>,
|
||||
<&dpll_abe_m2x2_ck>,
|
||||
<&atl_clkin2_ck>;
|
||||
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
|
||||
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
atl2 {
|
||||
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
||||
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcasp3 {
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mcasp3_pins>;
|
||||
pinctrl-1 = <&mcasp3_sleep_pins>;
|
||||
|
||||
assigned-clocks = <&mcasp3_ahclkx_mux>;
|
||||
assigned-clock-parents = <&atl_clkin2_ck>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
/* 4 serializer */
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
1 2 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&mailbox5 {
|
||||
status = "okay";
|
||||
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox6 {
|
||||
status = "okay";
|
||||
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
27
arch/arm/dts/dra7-iva-thermal.dtsi
Normal file
27
arch/arm/dts/dra7-iva-thermal.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Device Tree Source for DRA7x SoC IVA thermal
|
||||
*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
iva_thermal: iva_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 4>;
|
||||
|
||||
trips {
|
||||
iva_crit: iva_crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -9,24 +9,82 @@
|
|||
|
||||
#include "dra72x.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clk/ti-dra7-atl.h>
|
||||
|
||||
/ {
|
||||
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
|
||||
|
||||
aliases {
|
||||
display0 = &hdmi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
tick-timer = &timer2;
|
||||
};
|
||||
|
||||
aliases {
|
||||
display0 = &hdmi0;
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
evm_3v3: fixedregulator-evm_3v3 {
|
||||
evm_5v0: fixedregulator-evm5v0 {
|
||||
/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
|
||||
/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: fixedregulator-vsys3v3 {
|
||||
/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
|
||||
/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
evm_3v3_sw: fixedregulator-evm_3v3 {
|
||||
/* TPS22965DSG */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
aic_dvdd: fixedregulator-aic_dvdd {
|
||||
/* TPS77018DBVT */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "aic_dvdd";
|
||||
vin-supply = <&evm_3v3_sw>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
evm_3v3_sd: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_3v3_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_3v3_sw>;
|
||||
enable-active-high;
|
||||
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
|
|
@ -80,46 +138,81 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound0: sound0 {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "DRA7xx-EVM";
|
||||
simple-audio-card,widgets =
|
||||
"Headphone", "Headphone Jack",
|
||||
"Line", "Line Out",
|
||||
"Microphone", "Mic Jack",
|
||||
"Line", "Line In";
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"Line Out", "LLOUT",
|
||||
"Line Out", "RLOUT",
|
||||
"MIC3L", "Mic Jack",
|
||||
"MIC3R", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"LINE1L", "Line In",
|
||||
"LINE1R", "Line In";
|
||||
simple-audio-card,format = "dsp_b";
|
||||
simple-audio-card,bitclock-master = <&sound0_master>;
|
||||
simple-audio-card,frame-master = <&sound0_master>;
|
||||
simple-audio-card,bitclock-inversion;
|
||||
|
||||
sound0_master: simple-audio-card,cpu {
|
||||
sound-dai = <&mcasp3>;
|
||||
system-clock-frequency = <5644800>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&tlv320aic3106>;
|
||||
clocks = <&atl_clkin2_ck>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
mmc1_pins_default: mmc1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
|
||||
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
|
||||
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
|
||||
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
|
||||
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
|
||||
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
|
||||
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
|
||||
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
|
||||
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins_default: mmc2_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
|
||||
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
|
||||
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
|
||||
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
|
||||
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
|
||||
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
|
||||
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
|
||||
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
|
||||
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
|
||||
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
|
||||
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
|
||||
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
|
||||
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
|
||||
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
|
||||
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_sleep: dcan1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -128,123 +221,31 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps65917: tps65917@58 {
|
||||
compatible = "ti,tps65917";
|
||||
reg = <0x58>;
|
||||
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
tps65917_pmic {
|
||||
compatible = "ti,tps65917-pmic";
|
||||
|
||||
tps65917_regulators: regulators {
|
||||
smps1_reg: smps1 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps1";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps2_reg: smps2 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "smps2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1060000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_GPU IVA DSPEVE */
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps4_reg: smps4 {
|
||||
/* VDDS1V8 */
|
||||
regulator-name = "smps4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps5_reg: smps5 {
|
||||
/* VDD_DDR */
|
||||
regulator-name = "smps5";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* LDO1_OUT --> SDIO */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDA_1V8_PHY */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps65917_power_button {
|
||||
compatible = "ti,palmas-pwrbutton";
|
||||
interrupt-parent = <&tps65917>;
|
||||
interrupts = <1 IRQ_TYPE_NONE>;
|
||||
wakeup-source;
|
||||
ti,palmas-long-press-seconds = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
pcf_gpio_21: gpio@21 {
|
||||
compatible = "ti,pcf8575";
|
||||
compatible = "ti,pcf8575", "nxp,pcf8575";
|
||||
u-boot,i2c-offset-len = <0>;
|
||||
reg = <0x21>;
|
||||
lines-initial-states = <0x1408>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
tlv320aic3106: tlv320aic3106@19 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x19>;
|
||||
adc-settle-ms = <40>;
|
||||
ai3x-micbias-vg = <1>; /* 2.0V */
|
||||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&evm_3v3_sw>;
|
||||
IOVDD-supply = <&evm_3v3_sw>;
|
||||
DRVDD-supply = <&evm_3v3_sw>;
|
||||
DVDD-supply = <&aic_dvdd>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
|
|
@ -252,7 +253,7 @@
|
|||
clock-frequency = <400000>;
|
||||
|
||||
pcf_hdmi: pcf8575@26 {
|
||||
compatible = "nxp,pcf8575";
|
||||
compatible = "ti,pcf8575", "nxp,pcf8575";
|
||||
u-boot,i2c-offset-len = <0>;
|
||||
reg = <0x26>;
|
||||
gpio-controller;
|
||||
|
|
@ -286,12 +287,7 @@
|
|||
};
|
||||
|
||||
&gpmc {
|
||||
/*
|
||||
* For the existing IOdelay configuration via U-Boot we don't
|
||||
* support NAND on dra72-evm. Keep it disabled. Enabling it
|
||||
* requires a different configuration by U-Boot.
|
||||
*/
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
/* To use NAND, DIP switch SW5 must be set like so:
|
||||
|
|
@ -299,11 +295,11 @@
|
|||
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
||||
*/
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
|
|
@ -326,7 +322,6 @@
|
|||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
|
|
@ -377,14 +372,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&ldo4_reg>;
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
phy-supply = <&ldo4_reg>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
|
@ -394,7 +381,7 @@
|
|||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "otg";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
|
|
@ -405,7 +392,7 @@
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins_default>;
|
||||
vmmc_aux-supply = <&ldo1_reg>;
|
||||
vmmc-supply = <&evm_3v3_sd>;
|
||||
bus-width = <4>;
|
||||
/*
|
||||
* SDCD signal is not being used here - using the fact that GPIO mode
|
||||
|
|
@ -421,7 +408,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins_default>;
|
||||
|
||||
vmmc-supply = <&evm_3v3>;
|
||||
vmmc-supply = <&evm_3v3_sw>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
max-frequency = <192000000>;
|
||||
|
|
@ -433,6 +420,10 @@
|
|||
|
||||
&dcan1 {
|
||||
status = "ok";
|
||||
pinctrl-names = "default", "sleep", "active";
|
||||
pinctrl-0 = <&dcan1_pins_sleep>;
|
||||
pinctrl-1 = <&dcan1_pins_sleep>;
|
||||
pinctrl-2 = <&dcan1_pins_default>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
|
|
@ -498,8 +489,6 @@
|
|||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
vdda_video-supply = <&ldo5_reg>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
|
|
@ -511,3 +500,55 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&atl {
|
||||
assigned-clocks = <&abe_dpll_sys_clk_mux>,
|
||||
<&atl_gfclk_mux>,
|
||||
<&dpll_abe_ck>,
|
||||
<&dpll_abe_m2x2_ck>,
|
||||
<&atl_clkin2_ck>;
|
||||
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
|
||||
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
atl2 {
|
||||
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
||||
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcasp3 {
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
assigned-clocks = <&mcasp3_ahclkx_mux>;
|
||||
assigned-clock-parents = <&atl_clkin2_ck>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
/* 4 serializer */
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
1 2 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&mailbox5 {
|
||||
status = "okay";
|
||||
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox6 {
|
||||
status = "okay";
|
||||
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,25 +11,35 @@
|
|||
/ {
|
||||
model = "TI DRA722 Rev C EVM";
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
|
||||
};
|
||||
};
|
||||
|
||||
&tps65917_regulators {
|
||||
ldo2_reg: ldo2 {
|
||||
/* LDO2_OUT --> VDDA_1V8_PHY2 */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
&i2c1 {
|
||||
tps65917: tps65917@58 {
|
||||
reg = <0x58>;
|
||||
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
|
||||
};
|
||||
};
|
||||
|
||||
#include "dra72-evm-tps65917.dtsi"
|
||||
|
||||
&ldo2_reg {
|
||||
/* LDO2_OUT --> VDDA_1V8_PHY2 */
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
vdda_video-supply = <&ldo2_reg>;
|
||||
vdda-supply = <&ldo2_reg>;
|
||||
};
|
||||
|
||||
&pcf_gpio_21 {
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
|
|
|
|||
134
arch/arm/dts/dra72-evm-tps65917.dtsi
Normal file
134
arch/arm/dts/dra72-evm-tps65917.dtsi
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Integrated Power Management Chip
|
||||
* http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
|
||||
*/
|
||||
|
||||
&tps65917 {
|
||||
compatible = "ti,tps65917";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
tps65917_pmic {
|
||||
compatible = "ti,tps65917-pmic";
|
||||
|
||||
smps1-in-supply = <&vsys_3v3>;
|
||||
smps2-in-supply = <&vsys_3v3>;
|
||||
smps3-in-supply = <&vsys_3v3>;
|
||||
smps4-in-supply = <&vsys_3v3>;
|
||||
smps5-in-supply = <&vsys_3v3>;
|
||||
ldo1-in-supply = <&vsys_3v3>;
|
||||
ldo2-in-supply = <&vsys_3v3>;
|
||||
ldo3-in-supply = <&vsys_3v3>;
|
||||
ldo4-in-supply = <&evm_5v0>;
|
||||
ldo5-in-supply = <&vsys_3v3>;
|
||||
|
||||
tps65917_regulators: regulators {
|
||||
smps1_reg: smps1 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps1";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps2_reg: smps2 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "smps2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_GPU IVA DSPEVE */
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps4_reg: smps4 {
|
||||
/* VDDS1V8 */
|
||||
regulator-name = "smps4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps5_reg: smps5 {
|
||||
/* VDD_DDR */
|
||||
regulator-name = "smps5";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* LDO1_OUT --> SDIO */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDA_1V8_PHY */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps65917_power_button {
|
||||
compatible = "ti,palmas-pwrbutton";
|
||||
interrupt-parent = <&tps65917>;
|
||||
interrupts = <1 IRQ_TYPE_NONE>;
|
||||
wakeup-source;
|
||||
ti,palmas-long-press-seconds = <6>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,38 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <dra72-evm-common.dtsi>
|
||||
|
||||
#include "dra72-evm-common.dtsi"
|
||||
/ {
|
||||
model = "TI DRA722";
|
||||
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1024 MB */
|
||||
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
tps65917: tps65917@58 {
|
||||
reg = <0x58>;
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <3>;
|
||||
phy-mode = "rgmii";
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
vdda_video-supply = <&ldo5_reg>;
|
||||
};
|
||||
#include "dra72-evm-tps65917.dtsi"
|
||||
|
||||
&hdmi {
|
||||
vdda-supply = <&ldo3_reg>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
|
||||
&pcf_gpio_21 {
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
slaves = <1>;
|
||||
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <3>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
40
include/dt-bindings/clk/ti-dra7-atl.h
Normal file
40
include/dt-bindings/clk/ti-dra7-atl.h
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* This header provides constants for DRA7 ATL (Audio Tracking Logic)
|
||||
*
|
||||
* The constants defined in this header are used in dts files
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* Peter Ujfalusi <peter.ujfalusi@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
|
||||
#define _DT_BINDINGS_CLK_DRA7_ATL_H
|
||||
|
||||
#define DRA7_ATL_WS_MCASP1_FSR 0
|
||||
#define DRA7_ATL_WS_MCASP1_FSX 1
|
||||
#define DRA7_ATL_WS_MCASP2_FSR 2
|
||||
#define DRA7_ATL_WS_MCASP2_FSX 3
|
||||
#define DRA7_ATL_WS_MCASP3_FSX 4
|
||||
#define DRA7_ATL_WS_MCASP4_FSX 5
|
||||
#define DRA7_ATL_WS_MCASP5_FSX 6
|
||||
#define DRA7_ATL_WS_MCASP6_FSX 7
|
||||
#define DRA7_ATL_WS_MCASP7_FSX 8
|
||||
#define DRA7_ATL_WS_MCASP8_FSX 9
|
||||
#define DRA7_ATL_WS_MCASP8_AHCLKX 10
|
||||
#define DRA7_ATL_WS_XREF_CLK3 11
|
||||
#define DRA7_ATL_WS_XREF_CLK0 12
|
||||
#define DRA7_ATL_WS_XREF_CLK1 13
|
||||
#define DRA7_ATL_WS_XREF_CLK2 14
|
||||
#define DRA7_ATL_WS_OSC1_X1 15
|
||||
|
||||
#endif
|
||||
|
|
@ -30,6 +30,26 @@
|
|||
#define MUX_MODE14 0xe
|
||||
#define MUX_MODE15 0xf
|
||||
|
||||
/* Certain pins need virtual mode, but note: they may glitch */
|
||||
#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
|
||||
#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
|
||||
#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
|
||||
#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
|
||||
#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
|
||||
#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
|
||||
#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
|
||||
#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
|
||||
#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
|
||||
#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
|
||||
#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
|
||||
#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
|
||||
#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
|
||||
#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
|
||||
#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
|
||||
#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
|
||||
|
||||
#define MODE_SELECT (1 << 8)
|
||||
|
||||
#define PULL_ENA (0 << 16)
|
||||
#define PULL_DIS (1 << 16)
|
||||
#define PULL_UP (1 << 17)
|
||||
|
|
@ -47,5 +67,11 @@
|
|||
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
|
||||
#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
|
||||
|
||||
/*
|
||||
* Macro to allow using the absolute physical address instead of the
|
||||
* padconf registers instead of the offset from padconf base.
|
||||
*/
|
||||
#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user