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rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
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parent
7f0cfe478b
commit
7a25a63c13
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@ -269,14 +269,17 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
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switch (periph) {
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switch (periph) {
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case HCLK_EMMC:
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case HCLK_EMMC:
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case SCLK_EMMC:
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con = readl(&cru->cru_clksel_con[12]);
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con = readl(&cru->cru_clksel_con[12]);
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div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
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div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
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break;
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break;
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case HCLK_SDMMC:
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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con = readl(&cru->cru_clksel_con[11]);
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con = readl(&cru->cru_clksel_con[11]);
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div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
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div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
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break;
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break;
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case HCLK_SDIO:
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case HCLK_SDIO:
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case SCLK_SDIO:
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con = readl(&cru->cru_clksel_con[12]);
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con = readl(&cru->cru_clksel_con[12]);
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div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
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div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
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break;
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break;
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@ -298,16 +301,19 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
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switch (periph) {
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switch (periph) {
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case HCLK_EMMC:
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case HCLK_EMMC:
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case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_DIV_MASK << EMMC_DIV_SHIFT,
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EMMC_DIV_MASK << EMMC_DIV_SHIFT,
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src_clk_div << EMMC_DIV_SHIFT);
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src_clk_div << EMMC_DIV_SHIFT);
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break;
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break;
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case HCLK_SDMMC:
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_DIV_MASK << MMC0_DIV_SHIFT,
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MMC0_DIV_MASK << MMC0_DIV_SHIFT,
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src_clk_div << MMC0_DIV_SHIFT);
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src_clk_div << MMC0_DIV_SHIFT);
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break;
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break;
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case HCLK_SDIO:
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case HCLK_SDIO:
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case SCLK_SDIO:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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rk_clrsetreg(&cru->cru_clksel_con[12],
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SDIO_DIV_MASK << SDIO_DIV_SHIFT,
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SDIO_DIV_MASK << SDIO_DIV_SHIFT,
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src_clk_div << SDIO_DIV_SHIFT);
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src_clk_div << SDIO_DIV_SHIFT);
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@ -466,6 +472,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk)
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case HCLK_EMMC:
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case HCLK_EMMC:
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case HCLK_SDMMC:
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case HCLK_SDMMC:
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case HCLK_SDIO:
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case HCLK_SDIO:
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case SCLK_EMMC:
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case SCLK_SDMMC:
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case SCLK_SDIO:
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new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
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new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
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clk->id);
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clk->id);
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break;
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break;
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@ -505,6 +514,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
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case HCLK_EMMC:
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case HCLK_EMMC:
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case HCLK_SDMMC:
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case HCLK_SDMMC:
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case HCLK_SDIO:
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case HCLK_SDIO:
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case SCLK_EMMC:
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case SCLK_SDMMC:
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case SCLK_SDIO:
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new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
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new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
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clk->id, rate);
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clk->id, rate);
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break;
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break;
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