riscv: Move Andes PLMT driver to drivers/timer

This is a regular timer driver, and should live with the other timer
drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Sean Anderson 2020-10-25 21:46:56 -04:00 committed by Andes
parent 963911e9e1
commit 79b135f1f9
6 changed files with 9 additions and 8 deletions

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@ -938,6 +938,7 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/ F: arch/riscv/
F: cmd/riscv/ F: cmd/riscv/
F: drivers/timer/andes_plmt_timer.c
F: tools/prelink-riscv.c F: tools/prelink-riscv.c
RISC-V KENDRYTE RISC-V KENDRYTE

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@ -170,13 +170,6 @@ config ANDES_PLIC
The Andes PLIC block holds memory-mapped claim and pending registers The Andes PLIC block holds memory-mapped claim and pending registers
associated with software interrupt. associated with software interrupt.
config ANDES_PLMT
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
config SYS_MALLOC_F_LEN config SYS_MALLOC_F_LEN
default 0x1000 default 0x1000

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@ -13,7 +13,6 @@ obj-y += cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
else else
obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o

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@ -53,6 +53,13 @@ config ALTERA_TIMER
Select this to enable a timer for Altera devices. Please find Select this to enable a timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera. details on the "Embedded Peripherals IP User Guide" of Altera.
config ANDES_PLMT
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
config ARC_TIMER config ARC_TIMER
bool "ARC timer support" bool "ARC timer support"
depends on TIMER && ARC && CLK depends on TIMER && ARC && CLK

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@ -5,6 +5,7 @@
obj-y += timer-uclass.o obj-y += timer-uclass.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_ANDES_PLMT) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o