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Merge branch 'master' of git://www.denx.de/git/u-boot

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This commit is contained in:
Markus Klotzbuecher 2008-07-10 10:26:07 +02:00
commit 794a592497
1087 changed files with 26876 additions and 11600 deletions
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4065
CHANGELOG
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9
CREDITS
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@ -424,6 +424,10 @@ N: Paolo Scaffardi
E: arsenio@tin.it
D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
N: Andre Schwarz
E: andre.schwarz@matrix-vision.de
D: Support for Matrix Vision boards (MVBLM7)
N: Robert Schwebel
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
@ -533,3 +537,8 @@ N: Timo Tuunainen
E: timo.tuunainen@sysart.fi
D: Support for Artila M-501 starter kit
W: http://www.sysart.fi/
N: Philip Balister
E: philip@opensdr.com
D: Port to Lyrtech SFFSDR development board.
W: www.opensdr.com

13
MAINTAINERS
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@ -204,6 +204,10 @@ Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
KUP4X MPC859
Gary Jennejohn <garyj@denx.de>
quad100hd PPC405EP
Murray Jensen <Murray.Jensen@csiro.au>
cogent_mpc8xx MPC8xx
@ -367,6 +371,10 @@ Peter De Schrijver <p2@mind.be>
ML2 PPC4xx
Andre Schwarz <andre.schwarz@matrix-vision.de>
mvblm7 MPC8343
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
@ -538,6 +546,9 @@ Stelian Pop <stelian.pop@leadtechdesign.com>
at91cap9adk ARM926EJS (AT91CAP9 SoC)
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
Stefan Roese <sr@denx.de>
@ -695,6 +706,7 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
ATSTK1002 AT32AP7000
ATSTK1003 AT32AP7001
ATSTK1004 AT32AP7002
ATSTK1006 AT32AP7000
ATNGW100 AT32AP7000
#########################################################################
@ -710,6 +722,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
MS7722SE SH7722
R7780MP SH7780
R2DPlus SH7751R
SH7763RDP SH7763
Mark Jonas <mark.jonas@de.bosch.com>

31
MAKEALL
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@ -219,6 +219,7 @@ LIST_4xx=" \
PMC405 \
PMC440 \
PPChameleonEVB \
quad100hd \
rainier \
sbc405 \
sc3 \
@ -330,6 +331,7 @@ LIST_83xx=" \
MPC8360ERDK_66 \
MPC837XEMDS \
MPC837XERDB \
MVBLM7 \
sbc8349 \
TQM834x \
"
@ -359,6 +361,7 @@ LIST_85xx=" \
stxssa \
TQM8540 \
TQM8541 \
TQM8548 \
TQM8555 \
TQM8560 \
"
@ -461,6 +464,9 @@ LIST_ARM9=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9rlek \
cmc_pu2 \
ap920t \
ap922_XA10 \
@ -497,6 +503,7 @@ LIST_ARM9=" \
voiceblue \
davinci_dvevm \
davinci_schmoogie \
davinci_sffsdr \
davinci_sonata \
"
@ -520,6 +527,24 @@ LIST_ARM11=" \
mx31ads \
"
#########################################################################
## AT91 Systems
#########################################################################
LIST_at91=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9rlek \
cmc_pu2 \
csb637 \
kb9202 \
mp2usb \
m501sk \
"
#########################################################################
## Xscale Systems
#########################################################################
@ -697,6 +722,7 @@ LIST_avr32=" \
atstk1002 \
atstk1003 \
atstk1004 \
atstk1006 \
atngw100 \
"
@ -723,9 +749,10 @@ LIST_sh3=" \
LIST_sh4=" \
ms7750se \
ms7722se \
Migo-R \
MigoR \
r7780mp \
r2dplus \
sh7763rdp \
"
LIST_sh=" \
@ -765,7 +792,7 @@ build_target() {
for arg in $@
do
case "$arg" in
arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa \
arm|SA|ARM7|ARM9|ARM10|ARM11|at91|ixp|pxa \
|avr32 \
|blackfin \
|coldfire \

85
Makefile
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@ -220,10 +220,12 @@ LIBS += drivers/hwmon/libhwmon.a
LIBS += drivers/i2c/libi2c.a
LIBS += drivers/input/libinput.a
LIBS += drivers/misc/libmisc.a
LIBS += drivers/mmc/libmmc.a
LIBS += drivers/mtd/libmtd.a
LIBS += drivers/mtd/nand/libnand.a
LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
LIBS += drivers/mtd/onenand/libonenand.a
LIBS += drivers/mtd/spi/libspi_flash.a
LIBS += drivers/net/libnet.a
LIBS += drivers/net/sk98lin/libsk98lin.a
LIBS += drivers/pci/libpci.a
@ -386,10 +388,12 @@ TAG_SUBDIRS += drivers/hwmon
TAG_SUBDIRS += drivers/i2c
TAG_SUBDIRS += drivers/input
TAG_SUBDIRS += drivers/misc
TAG_SUBDIRS += drivers/mmc
TAG_SUBDIRS += drivers/mtd
TAG_SUBDIRS += drivers/mtd/nand
TAG_SUBDIRS += drivers/mtd/nand_legacy
TAG_SUBDIRS += drivers/mtd/onenand
TAG_SUBDIRS += drivers/mtd/spi
TAG_SUBDIRS += drivers/net
TAG_SUBDIRS += drivers/net/sk98lin
TAG_SUBDIRS += drivers/pci
@ -484,7 +488,7 @@ PATI_config: unconfig
#########################################################################
aev_config: unconfig
@$(MKCONFIG) -a aev ppc mpc5xxx tqm5200
@$(MKCONFIG) -a aev ppc mpc5xxx tqm5200 tqc
BC3450_config: unconfig
@$(MKCONFIG) -a BC3450 ppc mpc5xxx bc3450
@ -638,13 +642,13 @@ PM520_ROMBOOT_DDR_config: unconfig
@$(MKCONFIG) -a PM520 ppc mpc5xxx pm520
smmaco4_config: unconfig
@$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200
@$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 tqc
cm5200_config: unconfig
@$(MKCONFIG) -a cm5200 ppc mpc5xxx cm5200
spieval_config: unconfig
@$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200
@$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 tqc
TB5200_B_config \
TB5200_config: unconfig
@ -653,7 +657,7 @@ TB5200_config: unconfig
{ echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
$(XECHO) "... with MPC5200B processor" ; \
}
@$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200
@$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200 tqc
MINI5200_config \
EVAL5200_config \
@ -702,7 +706,7 @@ TQM5200_B_HIGHBOOT_config \
TQM5200_config \
TQM5200_STK100_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/tqm5200
@mkdir -p $(obj)board/tqc/tqm5200
@[ -z "$(findstring cam5200,$@)" ] || \
{ echo "#define CONFIG_CAM5200" >>$(obj)include/config.h ; \
echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \
@ -735,7 +739,7 @@ TQM5200_STK100_config: unconfig
@[ -z "$(findstring HIGHBOOT,$@)" ] || \
{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 tqc
uc101_config: unconfig
@$(MKCONFIG) uc101 ppc mpc5xxx uc101
motionpro_config: unconfig
@ -828,7 +832,7 @@ hermes_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx hermes
HMI10_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc
IAD210_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx IAD210 siemens
@ -1057,7 +1061,7 @@ RRvision_LCD_config: unconfig
@$(MKCONFIG) -a RRvision ppc mpc8xx RRvision
SM850_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc
spc1920_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920
@ -1107,13 +1111,13 @@ virtlab2_config: unconfig
echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
$(XECHO) "... with LCD display" ; \
}
@$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
@$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx tqc
TTTech_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc
uc100_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx uc100
@ -1128,7 +1132,7 @@ wtk_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>$(obj)include/config.h
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc
#########################################################################
## PPC4xx Systems
@ -1391,6 +1395,9 @@ PPChameleonEVB_HI_33_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
quad100hd_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
@ -1779,10 +1786,10 @@ TQM8265_AA_config: unconfig
echo "#undef CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
$(XECHO) "... without 60x Bus Mode" ; \
fi
@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260
@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260 tqc
TQM8272_config: unconfig
@$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272
@$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272 tqc
VoVPN-GW_66MHz_config \
VoVPN-GW_100MHz_config: unconfig
@ -2102,11 +2109,14 @@ MPC837XEMDS_HOST_config: unconfig
MPC837XERDB_config: unconfig
@$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
MVBLM7_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
#########################################################################
@ -2225,6 +2235,7 @@ stxssa_4M_config: unconfig
TQM8540_config \
TQM8541_config \
TQM8548_config \
TQM8555_config \
TQM8560_config: unconfig
@mkdir -p $(obj)include
@ -2233,9 +2244,8 @@ TQM8560_config: unconfig
echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
#########################################################################
## MPC86xx Systems
@ -2335,6 +2345,15 @@ shannon_config : unconfig
at91rm9200dk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
at91sam9261ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
at91sam9263ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
at91sam9rlek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@ -2411,6 +2430,9 @@ davinci_dvevm_config : unconfig
davinci_schmoogie_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci
davinci_sffsdr_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs sffsdr davinci davinci
davinci_sonata_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
@ -2879,6 +2901,9 @@ atstk1003_config : unconfig
atstk1004_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
atstk1006_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
atngw100_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x
@ -2890,40 +2915,48 @@ atngw100_config : unconfig
## sh3 (Renesas SuperH)
#########################################################################
mpr2_config: unconfig
@ >include/config.h
@echo "#define CONFIG_MPR2 1" >> include/config.h
@mkdir -p $(obj)include
@echo "#define CONFIG_MPR2 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh3 mpr2
ms7720se_config: unconfig
@echo "#define CONFIG_MS7720SE 1" > include/config.h
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se
#########################################################################
## sh4 (Renesas SuperH)
#########################################################################
ms7750se_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 ms7750se
ms7722se_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se
MigoR_config : unconfig
@ >include/config.h
@echo "#define CONFIG_MIGO_R 1" >> include/config.h
@mkdir -p $(obj)include
@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 MigoR
r7780mp_config: unconfig
@ >include/config.h
@echo "#define CONFIG_R7780MP 1" >> include/config.h
@mkdir -p $(obj)include
@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 r7780mp
r2dplus_config : unconfig
@ >include/config.h
@echo "#define CONFIG_R2DPLUS 1" >> include/config.h
@mkdir -p $(obj)include
@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 r2dplus
sh7763rdp_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 sh7763rdp
#========================================================================
# SPARC
#========================================================================

169
README
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@ -74,7 +74,7 @@ git://www.denx.de/git/u-boot.git ; you can browse it online at
http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
The "snapshot" links on this page allow you to download tarballs of
any version you might be interested in. Ofifcial releases are also
any version you might be interested in. Official releases are also
available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
directory.
@ -94,7 +94,7 @@ Where we come from:
* Provide extended interface to Linux boot loader
* S-Record download
* network boot
* PCMCIA / CompactFLash / ATA disk / SCSI ... boot
* PCMCIA / CompactFlash / ATA disk / SCSI ... boot
- create ARMBoot project (http://sourceforge.net/projects/armboot)
- add other CPU families (starting with ARM)
- create U-Boot project (http://sourceforge.net/projects/u-boot)
@ -230,7 +230,7 @@ Example: For a TQM823L module type:
cd u-boot
make TQM823L_config
For the Cogent platform, you need to specify the cpu type as well;
For the Cogent platform, you need to specify the CPU type as well;
e.g. "make cogent_mpc8xx_config". And also configure the cogent
directory according to the instructions in cogent/README.
@ -278,7 +278,7 @@ The following options need to be configured:
- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
Define one or more of
CONFIG_LCD_HEARTBEAT - update a character position on
the lcd display every second with
the LCD display every second with
a "rotator" |\-/|\-/
- Board flavour: (if CONFIG_MPC8260ADS is defined)
@ -293,7 +293,7 @@ The following options need to be configured:
Define exactly one of
CONFIG_MPC8240, CONFIG_MPC8245
- 8xx CPU Options: (if using an MPC8xx cpu)
- 8xx CPU Options: (if using an MPC8xx CPU)
CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
get_gclk_freq() cannot work
e.g. if there is no 32KHz
@ -346,11 +346,11 @@ The following options need to be configured:
CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
When transfering memsize parameter to linux, some versions
When transferring memsize parameter to linux, some versions
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
CONFIG_OF_LIBFDT / CONFIG_OF_FLAT_TREE
CONFIG_OF_LIBFDT
New kernel versions are expecting firmware settings to be
passed using flattened device trees (based on open firmware
@ -361,19 +361,13 @@ The following options need to be configured:
* Adds the "fdt" command
* The bootm command automatically updates the fdt
CONFIG_OF_FLAT_TREE
* Deprecated, see CONFIG_OF_LIBFDT
* Original ft_build.c-based support
* Automatically modifies the dft as part of the bootm command
* The environment variable "disable_of", when set,
disables this functionality.
OF_CPU - The proper name of the cpus node.
OF_SOC - The proper name of the soc node.
OF_TBCLK - The timebase frequency.
OF_STDOUT_PATH - The path to the console device
boards with QUICC Engines require OF_QE to set UCC mac addresses
boards with QUICC Engines require OF_QE to set UCC MAC
addresses
CONFIG_OF_BOARD_SETUP
@ -382,7 +376,7 @@ The following options need to be configured:
CONFIG_OF_BOOT_CPU
This define fills in the correct boot cpu in the boot
This define fills in the correct boot CPU in the boot
param header, the default value is zero if undefined.
- Serial Ports:
@ -452,7 +446,7 @@ The following options need to be configured:
linux_logo.h for logo.
Requires CONFIG_VIDEO_LOGO
CONFIG_CONSOLE_EXTRA_INFO
addional board info beside
additional board info beside
the logo
When CONFIG_CFB_CONSOLE is defined, video console is
@ -522,7 +516,7 @@ The following options need to be configured:
The value of these goes into the environment as
"ramboot" and "nfsboot" respectively, and can be used
as a convenience, when switching between booting from
ram and nfs.
RAM and NFS.
- Pre-Boot Commands:
CONFIG_PREBOOT
@ -742,11 +736,11 @@ The following options need to be configured:
Support for Intel 8254x gigabit chips.
CONFIG_E1000_FALLBACK_MAC
default MAC for empty eeprom after production.
default MAC for empty EEPROM after production.
CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
write routine for first time initialisation.
CONFIG_TULIP
@ -786,6 +780,21 @@ The following options need to be configured:
Define this to use i/o functions instead of macros
(some hardware wont work with macros)
CONFIG_DRIVER_SMC911X
Support for SMSC's LAN911x and LAN921x chips
CONFIG_DRIVER_SMC911X_BASE
Define this to hold the physical address
of the device (I/O space)
CONFIG_DRIVER_SMC911X_32_BIT
Define this if data bus is 32 bits
CONFIG_DRIVER_SMC911X_16_BIT
Define this if data bus is 16 bits. If your processor
automatically converts one 32 bit word to two 16 bit
words you may also try CONFIG_DRIVER_SMC911X_32_BIT.
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
@ -810,7 +819,7 @@ The following options need to be configured:
Define the below if you wish to use the USB console.
Once firmware is rebuilt from a serial console issue the
command "setenv stdin usbtty; setenv stdout usbtty" and
attach your usb cable. The Unix command "dmesg" should print
attach your USB cable. The Unix command "dmesg" should print
it has found a new device. The environment variable usbtty
can be set to gserial or cdc_acm to enable your device to
appear to a USB host as a Linux gserial device or a
@ -924,7 +933,7 @@ The following options need to be configured:
assumed.
For the CT69000 and SMI_LYNXEM drivers, videomode is
selected via environment 'videomode'. Two diferent ways
selected via environment 'videomode'. Two different ways
are possible:
- "videomode=num" 'num' is a standard LiLo mode numbers.
Following standard modes are supported (* is default):
@ -961,6 +970,10 @@ The following options need to be configured:
display); also select one of the supported displays
by defining one of these:
CONFIG_ATMEL_LCD:
HITACHI TX09D70VM1CCA, 3.5", 240x320.
CONFIG_NEC_NL6448AC33:
NEC NL6448AC33-18. Active, color, single scan.
@ -1043,7 +1056,7 @@ The following options need to be configured:
CONFIG_PHY_GIGE
If this option is set, support for speed/duplex
detection of Gigabit PHY is included.
detection of gigabit PHY is included.
CONFIG_PHY_RESET_DELAY
@ -1062,21 +1075,21 @@ The following options need to be configured:
CONFIG_ETH2ADDR
CONFIG_ETH3ADDR
Define a default value for ethernet address to use
for the respective ethernet interface, in case this
Define a default value for Ethernet address to use
for the respective Ethernet interface, in case this
is not determined automatically.
- IP address:
CONFIG_IPADDR
Define a default value for the IP address to use for
the default ethernet interface, in case this is not
the default Ethernet interface, in case this is not
determined through e.g. bootp.
- Server IP address:
CONFIG_SERVERIP
Defines a default value for theIP address of a TFTP
Defines a default value for the IP address of a TFTP
server to contact when using the "tftboot" command.
- Multicast TFTP Mode:
@ -1084,7 +1097,7 @@ The following options need to be configured:
Defines whether you want to support multicast TFTP as per
rfc-2090; for example to work with atftp. Lets lots of targets
tftp down the same boot image concurrently. Note: the ethernet
tftp down the same boot image concurrently. Note: the Ethernet
driver in use must provide a function: mcast() to join/leave a
multicast group.
@ -1172,7 +1185,7 @@ The following options need to be configured:
A printf format string which contains the ascii name of
the port. Normally is set to "eth%d" which sets
eth0 for the first ethernet, eth1 for the second etc.
eth0 for the first Ethernet, eth1 for the second etc.
CONFIG_CDP_CAPABILITIES
@ -1221,7 +1234,7 @@ The following options need to be configured:
These enable I2C serial bus commands. Defining either of
(but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will
include the appropriate I2C driver for the selected cpu.
include the appropriate I2C driver for the selected CPU.
This will allow you to use i2c commands at the u-boot
command line (as long as you set CONFIG_CMD_I2C in
@ -1246,10 +1259,10 @@ The following options need to be configured:
In both cases you will need to define CFG_I2C_SPEED
to be the frequency (in Hz) at which you wish your i2c bus
to run and CFG_I2C_SLAVE to be the address of this node (ie
the cpu's i2c node address).
the CPU's i2c node address).
Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
sets the cpu up as a master node and so its address should
sets the CPU up as a master node and so its address should
therefore be cleared to 0 (See, eg, MPC823e User's Manual
p.16-473). So, set CFG_I2C_SLAVE to 0.
@ -1468,17 +1481,17 @@ The following options need to be configured:
Maximum time to wait for the INIT_B line to deassert
after PROB_B has been deasserted during a Virtex II
FPGA configuration sequence. The default time is 500
mS.
ms.
CFG_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to deassert during
Virtex II FPGA configuration. The default is 5 mS.
Virtex II FPGA configuration. The default is 5 ms.
CFG_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is
200 mS.
200 ms.
- Configuration Management:
CONFIG_IDENT_STRING
@ -1495,7 +1508,7 @@ The following options need to be configured:
protects these variables from casual modification by
the user. Once set, these variables are read-only,
and write or delete attempts are rejected. You can
change this behviour:
change this behaviour:
If CONFIG_ENV_OVERWRITE is #defined in your config
file, the write protection for vendor parameters is
@ -1504,7 +1517,7 @@ The following options need to be configured:
Alternatively, if you #define _both_ CONFIG_ETHADDR
_and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
ethernet address is installed in the environment,
Ethernet address is installed in the environment,
which can be changed exactly ONCE by the user. [The
serial# is unaffected by this, i. e. it remains
read-only.]
@ -1548,7 +1561,7 @@ The following options need to be configured:
Define this variable to stop the system in case of a
fatal error, so that you have to reset it manually.
This is probably NOT a good idea for an embedded
system where you want to system to reboot
system where you want the system to reboot
automatically as fast as possible, but it may be
useful during development since you can try to debug
the conditions that lead to the situation.
@ -1615,7 +1628,7 @@ The following options need to be configured:
- Commandline Editing and History:
CONFIG_CMDLINE_EDITING
Enable editiong and History functions for interactive
Enable editing and History functions for interactive
commandline input operations
- Default Environment:
@ -1656,7 +1669,7 @@ The following options need to be configured:
Adding this option adds support for Xilinx SystemACE
chips attached via some sort of local bus. The address
of the chip must alsh be defined in the
of the chip must also be defined in the
CFG_SYSTEMACE_BASE macro. For example:
#define CONFIG_SYSTEMACE
@ -1722,7 +1735,7 @@ Legacy uImage format:
-12 common/image.c Ramdisk data has bad checksum
11 common/image.c Ramdisk data has correct checksum
12 common/image.c Ramdisk verification complete, start loading
-13 common/image.c Wrong Image Type (not PPC Linux Ramdisk)
-13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
13 common/image.c Start multifile image verification
14 common/image.c No initial ramdisk, no multifile, continue.
@ -1782,13 +1795,13 @@ Legacy uImage format:
-60 common/env_common.c Environment has a bad CRC, using default
64 net/eth.c starting with Ethernetconfiguration.
64 net/eth.c starting with Ethernet configuration.
-64 net/eth.c no Ethernet found.
65 net/eth.c Ethernet found.
-80 common/cmd_net.c usage wrong
80 common/cmd_net.c before calling NetLoop()
-81 common/cmd_net.c some error in NetLoop() occured
-81 common/cmd_net.c some error in NetLoop() occurred
81 common/cmd_net.c NetLoop() back without error
-82 common/cmd_net.c size == 0 (File with size 0 loaded)
82 common/cmd_net.c trying automatic boot
@ -1811,8 +1824,8 @@ FIT uImage format:
105 common/cmd_bootm.c Kernel subimage hash verification OK
-105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
106 common/cmd_bootm.c Architecture check OK
-106 common/cmd_bootm.c Kernel subimage has wrong typea
107 common/cmd_bootm.c Kernel subimge type OK
-106 common/cmd_bootm.c Kernel subimage has wrong type
107 common/cmd_bootm.c Kernel subimage type OK
-107 common/cmd_bootm.c Can't get kernel subimage data/size
108 common/cmd_bootm.c Got kernel subimage data/size
-108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
@ -1825,7 +1838,7 @@ FIT uImage format:
120 common/image.c Start initial ramdisk verification
-120 common/image.c Ramdisk FIT image has incorrect format
121 common/image.c Ramdisk FIT image has correct format
122 common/image.c No Ramdisk subimage unit name, using configuration
122 common/image.c No ramdisk subimage unit name, using configuration
-122 common/image.c Can't get configuration for ramdisk subimage
123 common/image.c Ramdisk unit name specified
-124 common/image.c Can't get ramdisk subimage node offset
@ -1839,13 +1852,13 @@ FIT uImage format:
129 common/image.c Can't get ramdisk load address
-129 common/image.c Got ramdisk load address
-130 common/cmd_doc.c Icorrect FIT image format
-130 common/cmd_doc.c Incorrect FIT image format
131 common/cmd_doc.c FIT image format OK
-140 common/cmd_ide.c Icorrect FIT image format
-140 common/cmd_ide.c Incorrect FIT image format
141 common/cmd_ide.c FIT image format OK
-150 common/cmd_nand.c Icorrect FIT image format
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
@ -1854,7 +1867,7 @@ Modem Support:
[so far only for SMDK2400 and TRAB boards]
- Modem support endable:
- Modem support enable:
CONFIG_MODEM_SUPPORT
- RTS/CTS Flow control enable:
@ -1870,11 +1883,11 @@ Modem Support:
There are common interrupt_init() and timer_interrupt()
for all PPC archs. interrupt_init() calls interrupt_init_cpu()
for cpu specific initialization. interrupt_init_cpu()
for CPU specific initialization. interrupt_init_cpu()
should set decrementer_count to appropriate value. If
cpu resets decrementer automatically after interrupt
CPU resets decrementer automatically after interrupt
(ppc4xx) it should set decrementer_count to zero.
timer_interrupt() calls timer_interrupt_cpu() for cpu
timer_interrupt() calls timer_interrupt_cpu() for CPU
specific handling. If board has watchdog / status_led
/ other_activity_monitor it works automatically from
general timer_interrupt().
@ -1884,7 +1897,7 @@ Modem Support:
In the target system modem support is enabled when a
specific key (key combination) is pressed during
power-on. Otherwise U-Boot will boot normally
(autoboot). The key_pressed() fuction is called from
(autoboot). The key_pressed() function is called from
board_init(). Currently key_pressed() is a dummy
function, returning 1 and thus enabling modem
initialization.
@ -1892,7 +1905,7 @@ Modem Support:
If there are no modem init strings in the
environment, U-Boot proceed to autoboot; the
previous output (banner, info printfs) will be
supressed, though.
suppressed, though.
See also: doc/README.Modem
@ -1948,7 +1961,7 @@ Configuration Settings:
- CFG_MEM_TOP_HIDE (PPC only):
If CFG_MEM_TOP_HIDE is defined in the board config header,
this specified memory area will get subtracted from the top
(end) of ram and won't get "touched" at all by U-Boot. By
(end) of RAM and won't get "touched" at all by U-Boot. By
fixing up gd->ram_size the Linux kernel should gets passed
the now "corrected" memory size and won't touch it either.
This should work for arch/ppc and arch/powerpc. Only Linux
@ -2043,8 +2056,8 @@ Configuration Settings:
The two-step approach is usually more reliable, since
you can check if the download worked before you erase
the flash, but in some situations (when sytem RAM is
too limited to allow for a tempory copy of the
the flash, but in some situations (when system RAM is
too limited to allow for a temporary copy of the
downloaded image) this option may be very useful.
- CFG_FLASH_CFI:
@ -2074,11 +2087,11 @@ Configuration Settings:
column displays, 15 (3..1) for 40 column displays.
- CFG_RX_ETH_BUFFER:
Defines the number of ethernet receive buffers. On some
ethernet controllers it is recommended to set this value
Defines the number of Ethernet receive buffers. On some
Ethernet controllers it is recommended to set this value
to 8 or even higher (EEPRO100 or 405 EMAC), since all
buffers can be full shortly after enabling the interface
on high ethernet traffic.
on high Ethernet traffic.
Defaults to 4 if not defined.
The following definitions that deal with the placement and management
@ -2146,7 +2159,7 @@ following configurations:
CFG_ENV_SIZE_REDUND
These settings describe a second storage area used to hold
a redundand copy of the environment data, so that there is
a redundant copy of the environment data, so that there is
a valid backup copy in case there is a power failure during
a "saveenv" operation.
@ -2164,14 +2177,14 @@ accordingly!
- CFG_ENV_ADDR:
- CFG_ENV_SIZE:
These two #defines are used to determin the memory area you
These two #defines are used to determine the memory area you
want to use for environment. It is assumed that this memory
can just be read and written to, without any special
provision.
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initalization (when we try to get the setting of for the
console baudrate). You *MUST* have mappend your NVRAM area then, or
console baudrate). You *MUST* have mapped your NVRAM area then, or
U-Boot will hang.
Please note that even with NVRAM we still use a copy of the
@ -2320,14 +2333,14 @@ Low Level (hardware related) configuration options:
CFG_ISA_IO_STRIDE
defines the spacing between fdc chipset registers
defines the spacing between FDC chipset registers
(default value 1)
CFG_ISA_IO_OFFSET
defines the offset of register from address. It
depends on which part of the data bus is connected to
the fdc chipset. (default value 0)
the FDC chipset. (default value 0)
If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and
CFG_FDC_DRIVE_NUMBER are undefined, they take their
@ -2523,7 +2536,7 @@ Low Level (hardware related) configuration options:
Normally these variables MUST NOT be defined. The
only exception is when U-Boot is loaded (to RAM) by
some other boot loader or by a debugger which
performs these intializations itself.
performs these initializations itself.
Building the Software:
@ -2558,7 +2571,7 @@ Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for
instance, the TQM823L systems are available without (standard)
or with LCD support. You can select such additional "features"
when chosing the configuration, i. e.
when choosing the configuration, i. e.
make TQM823L_config
- will configure for a plain TQM823L, i. e. no LCD support
@ -2761,7 +2774,7 @@ Some configuration options can be set using Environment Variables:
for use by the bootm command. See also "bootm_size"
environment variable. Address defined by "bootm_low" is
also the base of the initial memory mapping for the Linux
kernel -- see the descripton of CFG_BOOTMAPSZ.
kernel -- see the description of CFG_BOOTMAPSZ.
bootm_size - Memory range available for image processing in the bootm
command can be restricted. This variable is given as
@ -2868,7 +2881,7 @@ Some configuration options can be set using Environment Variables:
themselves.
npe_ucode - see CONFIG_IXP4XX_NPE_EXT_UCOD
if set load address for the npe microcode
if set load address for the NPE microcode
tftpsrcport - If this is set, the value is used for TFTP's
UDP source port.
@ -2877,7 +2890,7 @@ Some configuration options can be set using Environment Variables:
destination port instead of the Well Know Port 69.
vlan - When set to a value < 4095 the traffic over
ethernet is encapsulated/received over 802.1q
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
The following environment variables may be used and automatically
@ -2955,14 +2968,14 @@ General rules:
executed anyway.
(2) If you execute several variables with one call to run (i. e.
calling run with a list af variables as arguments), any failing
calling run with a list of variables as arguments), any failing
command will cause "run" to terminate, i. e. the remaining
variables are not executed.
Note for Redundant Ethernet Interfaces:
=======================================
Some boards come with redundant ethernet interfaces; U-Boot supports
Some boards come with redundant Ethernet interfaces; U-Boot supports
such configurations and is capable of automatic selection of a
"working" interface when needed. MAC assignment works as follows:
@ -3303,7 +3316,7 @@ parameters. You can check and modify this variable using the
Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000]
...
If you want to boot a Linux kernel with initial ram disk, you pass
If you want to boot a Linux kernel with initial RAM disk, you pass
the memory addresses of both the kernel and the initrd image (PPBCOOT
format!) to the "bootm" command:
@ -3613,13 +3626,13 @@ locked as (mis-) used as memory, etc.
require any physical RAM backing up the cache. The cleverness
is that the cache is being used as a temporary supply of
necessary storage before the SDRAM controller is setup. It's
beyond the scope of this list to expain the details, but you
beyond the scope of this list to explain the details, but you
can see how this works by studying the cache architecture and
operation in the architecture and processor-specific manuals.
OCM is On Chip Memory, which I believe the 405GP has 4K. It
is another option for the system designer to use as an
initial stack/ram area prior to SDRAM being available. Either
initial stack/RAM area prior to SDRAM being available. Either
option should work for you. Using CS 4 should be fine if your
board designers haven't used it for something that would
cause you grief during the initial boot! It is frequently not
@ -3644,7 +3657,7 @@ code for the initialization procedures:
* Initialized global data (data segment) is read-only. Do not attempt
to write it.
* Do not use any unitialized global data (or implicitely initialized
* Do not use any uninitialized global data (or implicitely initialized
as zero data - BSS segment) at all - this is undefined, initiali-
zation is performed later (when relocating to RAM).
@ -3756,7 +3769,7 @@ System Initialization:
----------------------
In the reset configuration, U-Boot starts at the reset entry point
(on most PowerPC systens at address 0x00000100). Because of the reset
(on most PowerPC systems at address 0x00000100). Because of the reset
configuration for CS0# this is a mirror of the onboard Flash memory.
To be able to re-map memory U-Boot then jumps to its link address.
To be able to implement the initialization code in C, a (small!)

2
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
View File

@ -39,7 +39,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int size,i;

4
board/LEOX/elpt860/elpt860.c
View File

@ -35,7 +35,7 @@
** ------
** int board_early_init_f(void)
** int checkboard(void)
** long int initdram(int board_type)
** phys_size_t initdram(int board_type)
** called from 'board_init_f()' into 'common/board.c'
**
** void reset_phy(void)
@ -179,7 +179,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

2
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
View File

@ -81,7 +81,7 @@ int checkboard (void)
return 0;
}
long initdram (int board_type)
phys_size_t initdram (int board_type)
{
return articiaS_ram_init ();
}

2
board/Marvell/db64360/sdram_init.c
View File

@ -1728,7 +1728,7 @@ long int dram_size (long int *base, long int maxsize)
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };

2
board/Marvell/db64460/sdram_init.c
View File

@ -1737,7 +1737,7 @@ long int dram_size (long int *base, long int maxsize)
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };

18
board/MigoR/Makefile
View File

@ -24,25 +24,29 @@
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
LIB = $(obj)lib$(BOARD).a
OBJS := migo_r.o
COBJS := migo_r.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
-include .depend
sinclude $(obj).depend
#########################################################################

2
board/RPXClassic/RPXClassic.c
View File

@ -165,7 +165,7 @@ void rpxclassic_init (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

2
board/RPXlite/RPXlite.c
View File

@ -102,7 +102,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

2
board/RPXlite_dw/RPXlite_dw.c
View File

@ -104,7 +104,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

2
board/RRvision/RRvision.c
View File

@ -110,7 +110,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

2
board/a3000/a3000.c
View File

@ -38,7 +38,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;

2
board/actux1/Makefile
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/actux2/Makefile
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/actux3/Makefile
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/actux4/Makefile
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/adder/Makefile
View File

@ -41,7 +41,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/adder/adder.c
View File

@ -65,7 +65,7 @@ static uint sdram_table[] = {
0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
};
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;

2
board/ads5121/Makefile
View File

@ -45,7 +45,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/ads5121/ads5121.c
View File

@ -112,7 +112,7 @@ int board_early_init_f (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
u32 msize = 0;

2
board/adsvix/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/alaska/Makefile
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/alaska/alaska.c
View File

@ -131,7 +131,7 @@ void setupBat (ulong size)
mtspr (DBAT7U, batu);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong size;

2
board/altera/dk1c20/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/altera/dk1c20/dk1c20.c
View File

@ -50,7 +50,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

2
board/altera/dk1s10/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/altera/dk1s10/dk1s10.c
View File

@ -54,7 +54,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

2
board/altera/ep1c20/Makefile
View File

@ -43,7 +43,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/altera/ep1c20/ep1c20.c
View File

@ -34,7 +34,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

2
board/altera/ep1s10/Makefile
View File

@ -43,7 +43,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/altera/ep1s10/ep1s10.c
View File

@ -34,7 +34,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

2
board/altera/ep1s40/Makefile
View File

@ -43,7 +43,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/altera/ep1s40/ep1s40.c
View File

@ -29,7 +29,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

2
board/amcc/acadia/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

17
board/amcc/acadia/memory.c
View File

@ -33,14 +33,6 @@
extern void board_pll_init_f(void);
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
@ -67,7 +59,7 @@ static void cram_bcr_write(u32 wr_val)
}
#endif
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;
@ -116,10 +108,3 @@ long int initdram(int board_type)
return (CFG_MBYTES_RAM << 20);
}
#ifndef CONFIG_NAND_SPL
int testdram(void)
{
return (0);
}
#endif

2
board/amcc/bamboo/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

69
board/amcc/bamboo/bamboo.c
View File

@ -453,7 +453,7 @@ int checkboard(void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
@ -466,73 +466,6 @@ long int initdram (int board_type)
#endif
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n, *p32, ctr;
const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
mtmsr(0);
for (k = 0; k < CFG_MBYTES_SDRAM*1024;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
/*
* Perform a sequence test to ensure that all
* memory locations are uniquely addressable
*/
ctr = 0;
p32 = 0;
while ((unsigned long)p32 != bend) {
if (0 == ((unsigned long)p32 & ((1<<20)-1)))
printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
*p32++ = ctr++;
}
ctr = 0;
p32 = 0;
while ((unsigned long)p32 != bend) {
if (0 == ((unsigned long)p32 & ((1<<20)-1)))
printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
if (*p32 != ctr) {
printf("SDRAM test fails at: %08x\n", p32);
return 1;
}
ctr++;
p32++;
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*

2
board/amcc/bubinga/Makefile
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

18
board/amcc/bubinga/bubinga.c
View File

@ -66,30 +66,14 @@ int checkboard(void)
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long int ret;
ret = spd_sdram();
return ret;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}

2
board/amcc/canyonlands/Makefile
View File

@ -40,7 +40,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

51
board/amcc/canyonlands/canyonlands.c
View File

@ -22,6 +22,7 @@
#include <ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
@ -205,50 +206,12 @@ u32 ddr_clktr(u32 default_val) {
* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
* code.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return CFG_MBYTES_SDRAM << 20;
}
#endif
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*
* pci_target_init
*
@ -431,6 +394,7 @@ int misc_init_r(void)
u32 sdr0_srst1 = 0;
u32 eth_cfg;
u32 pvr = get_pvr();
u8 val;
/*
* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
@ -458,6 +422,15 @@ int misc_init_r(void)
sdr0_srst1 &= ~SDR0_SRST1_AHB;
mtsdr(SDR0_SRST1, sdr0_srst1);
/*
* RTC/M41T62:
* Disable square wave output: Batterie will be drained
* quickly, when this output is not disabled
*/
val = i2c_reg_read(CFG_I2C_RTC_ADDR, 0xa);
val &= ~0x40;
i2c_reg_write(CFG_I2C_RTC_ADDR, 0xa, val);
return 0;
}

2
board/amcc/ebony/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

32
board/amcc/ebony/ebony.c
View File

@ -104,7 +104,7 @@ int checkboard(void)
return (0);
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long dram_size = 0;
@ -116,36 +116,6 @@ long int initdram(int board_type)
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.

2
board/amcc/katmai/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

30
board/amcc/katmai/katmai.c
View File

@ -258,36 +258,6 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*

5
board/amcc/kilauea/Makefile
View File

@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_pll.o memory.o
SOBJS = init.o
COBJS = $(BOARD).o cmd_pll.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@ -38,7 +37,7 @@ clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

154
board/amcc/kilauea/init.S
View File

@ -1,154 +0,0 @@
/*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on code provided from UDTech and AMCC
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
mtdcr memcfga,r4 ; \
addis r4,0,value@h ; \
ori r4,r4,value@l ; \
mtdcr memcfgd,r4 ;
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
/*
* DDR2 setup
*/
/* Following the DDR Core Manual, here is the initialization */
/* Step 1 */
/* Step 2 */
/* Step 3 */
/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
mtsdram_as(SDRAM_MB0CF, 0x00006701);
/* SET SDRAM_MB1CF - Not enabled */
mtsdram_as(SDRAM_MB1CF, 0x00000000);
/* SET SDRAM_MB2CF - Not enabled */
mtsdram_as(SDRAM_MB2CF, 0x00000000);
/* SET SDRAM_MB3CF - Not enabled */
mtsdram_as(SDRAM_MB3CF, 0x00000000);
/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
mtsdram_as(SDRAM_CLKTR, 0x80000000);
/* Refresh Time register (0x30) Refresh every 7.8125uS */
mtsdram_as(SDRAM_RTR, 0x06180000);
/* SDRAM_SDTR1 */
mtsdram_as(SDRAM_SDTR1, 0x80201000);
/* SDRAM_SDTR2 */
mtsdram_as(SDRAM_SDTR2, 0x32204232);
/* SDRAM_SDTR3 */
mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
mtsdram_as(SDRAM_MMODE, 0x00000442);
mtsdram_as(SDRAM_MEMODE, 0x00000404);
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
mtsdram_as(SDRAM_MCOPT1, 0x04322000);
/* NOP */
mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR1, 0x81900400);
/* EMR2 twr = 2tck */
mtsdram_as(SDRAM_INITPLR2, 0x81020000);
/* EMR3 twr = 2tck */
mtsdram_as(SDRAM_INITPLR3, 0x81030000);
/* EMR DLL ENABLE twr = 2tck */
mtsdram_as(SDRAM_INITPLR4, 0x81010404);
/* MR w/ DLL reset
* Note: 5 is CL. May need to be changed
*/
mtsdram_as(SDRAM_INITPLR5, 0x81000542);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR6, 0x81900400);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
mtsdram_as(SDRAM_INITPLR11, 0x81000442);
mtsdram_as(SDRAM_INITPLR12, 0x81010780);
mtsdram_as(SDRAM_INITPLR13, 0x81010400);
mtsdram_as(SDRAM_INITPLR14, 0x00000000);
mtsdram_as(SDRAM_INITPLR15, 0x00000000);
/* SET MCIF0_CODT Die Termination On */
mtsdram_as(SDRAM_CODT, 0x0080f837);
mtsdram_as(SDRAM_MODT0, 0x01800000);
mtsdram_as(SDRAM_MODT1, 0x00000000);
mtsdram_as(SDRAM_WRDTR, 0x00000000);
/* SDRAM0_MCOPT2 (0X21) Start initialization */
mtsdram_as(SDRAM_MCOPT2, 0x20000000);
/* Step 5 */
lis r3,0x1 /* 400000 = wait 100ms */
mtctr r3
pll_wait:
bdnz pll_wait
/* Step 6 */
/* SDRAM_DLCR */
mtsdram_as(SDRAM_DLCR, 0x030000a5);
/* SDRAM_RDCC */
mtsdram_as(SDRAM_RDCC, 0x40000000);
/* SDRAM_RQDC */
mtsdram_as(SDRAM_RQDC, 0x80000038);
/* SDRAM_RFDC */
mtsdram_as(SDRAM_RFDC, 0x00000209);
/* Enable memory controller */
mtsdram_as(SDRAM_MCOPT2, 0x28000000);
#endif /* #ifndef CONFIG_NAND_U_BOOT */
blr

79
board/amcc/kilauea/memory.c
View File

@ -1,79 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <i2c.h>
void sdram_init(void)
{
return;
}
long int initdram(int board_type)
{
return (CFG_MBYTES_SDRAM << 20);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
printf ("testdram\n");
#if defined (CONFIG_NAND_U_BOOT)
return 0;
#endif
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x00001000;
uint *p;
for (p = pstart; p < pend; p++) {
*p = 0xaaaaaaaa;
}
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
for (p = pstart; p < pend; p++) {
*p = 0x55555555;
}
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test passed!!!\n");
#endif
return 0;
}
#endif

2
board/amcc/luan/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

44
board/amcc/luan/luan.c
View File

@ -125,50 +125,6 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
}
/*************************************************************************
* int testdram()
*
************************************************************************/
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *) 0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*

4
board/amcc/makalu/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_pll.o memory.o
COBJS = $(BOARD).o cmd_pll.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
@ -38,7 +38,7 @@ clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

125
board/amcc/makalu/init.S
View File

@ -1,8 +1,11 @@
/*
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on code provided from Senao and AMCC
* Originally based on code provided from Senao and AMCC
*
* See file CREDITS for list of people who contributed to this
* project.
@ -23,126 +26,6 @@
* MA 02111-1307 USA
*/
#include <config.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
mtdcr memcfga,r4 ; \
addis r4,0,value@h ; \
ori r4,r4,value@l ; \
mtdcr memcfgd,r4 ;
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
/*
* DDR2 setup
*/
/* Following the DDR Core Manual, here is the initialization */
/* Step 1 */
/* Step 2 */
/* Step 3 */
/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
mtsdram_as(SDRAM_MB0CF, 0x00005201);
/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
mtsdram_as(SDRAM_CLKTR,0x80000000);
/* Refresh Time register (0x30) Refresh every 7.8125uS */
mtsdram_as(SDRAM_RTR, 0x06180000);
/* SDRAM_SDTR1 */
mtsdram_as(SDRAM_SDTR1, 0x80201000);
/* SDRAM_SDTR2 */
mtsdram_as(SDRAM_SDTR2, 0x32204232);
/* SDRAM_SDTR3 */
mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
mtsdram_as(SDRAM_MMODE, 0x00000442);
mtsdram_as(SDRAM_MEMODE, 0x00000404);
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
mtsdram_as(SDRAM_MCOPT1, 0x04322000);
/* NOP */
mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR1, 0x81900400);
/* EMR2 twr = 2tck */
mtsdram_as(SDRAM_INITPLR2, 0x81020000);
/* EMR3 twr = 2tck */
mtsdram_as(SDRAM_INITPLR3, 0x81030000);
/* EMR DLL ENABLE twr = 2tck */
mtsdram_as(SDRAM_INITPLR4, 0x81010404);
/* MR w/ DLL reset
* Note: 5 is CL. May need to be changed
*/
mtsdram_as(SDRAM_INITPLR5, 0x81000542);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR6, 0x81900400);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
mtsdram_as(SDRAM_INITPLR11, 0x81000442);
mtsdram_as(SDRAM_INITPLR12, 0x81010780);
mtsdram_as(SDRAM_INITPLR13, 0x81010400);
mtsdram_as(SDRAM_INITPLR14, 0x00000000);
mtsdram_as(SDRAM_INITPLR15, 0x00000000);
/* SET MCIF0_CODT Die Termination On */
mtsdram_as(SDRAM_CODT, 0x0080f837);
mtsdram_as(SDRAM_MODT0, 0x01800000);
#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
mtsdram_as(SDRAM_MODT1, 0x00000000);
#endif
mtsdram_as(SDRAM_WRDTR, 0x00000000);
/* SDRAM0_MCOPT2 (0X21) Start initialization */
mtsdram_as(SDRAM_MCOPT2, 0x20000000);
/* Step 5 */
lis r3,0x1 /* 400000 = wait 100ms */
mtctr r3
pll_wait:
bdnz pll_wait
/* Step 6 */
/* SDRAM_DLCR */
mtsdram_as(SDRAM_DLCR, 0x030000a5);
/* SDRAM_RDCC */
mtsdram_as(SDRAM_RDCC, 0x40000000);
/* SDRAM_RQDC */
mtsdram_as(SDRAM_RQDC, 0x80000038);
/* SDRAM_RFDC */
mtsdram_as(SDRAM_RFDC, 0x00000209);
/* Enable memory controller */
mtsdram_as(SDRAM_MCOPT2, 0x28000000);
blr

188
board/amcc/makalu/memory.c
View File

@ -1,188 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
void sdram_init(void)
{
return;
}
long int initdram(int board_type)
{
/*
* Same as on Kilauea, Makalu generates exception 0x200
* (machine check) after trap_init() in board_init_f,
* when SDRAM is initialized here (late) and d-cache is
* used earlier as INIT_RAM.
* So for now, initialize DDR2 in init.S very early and
* also use it for INIT_RAM. Then this exception doesn't
* occur.
*/
#if 0
u32 val;
/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
mtsdram(SDRAM_MB0CF, 0x00005201);
/* SET SDRAM_MB1CF - Not enabled */
mtsdram(SDRAM_MB1CF, 0x00000000);
/* SET SDRAM_MB2CF - Not enabled */
mtsdram(SDRAM_MB2CF, 0x00000000);
/* SET SDRAM_MB3CF - Not enabled */
mtsdram(SDRAM_MB3CF, 0x00000000);
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
mtsdram(SDRAM_CLKTR, 0x80000000);
/* Refresh Time register (0x30) Refresh every 7.8125uS */
mtsdram(SDRAM_RTR, 0x06180000);
/* SDRAM_SDTR1 */
mtsdram(SDRAM_SDTR1, 0x80201000);
/* SDRAM_SDTR2 */
mtsdram(SDRAM_SDTR2, 0x32204232);
/* SDRAM_SDTR3 */
mtsdram(SDRAM_SDTR3, 0x080b0d1a);
mtsdram(SDRAM_MMODE, 0x00000442);
mtsdram(SDRAM_MEMODE, 0x00000404);
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
mtsdram(SDRAM_MCOPT1, 0x04322000);
/* NOP */
mtsdram(SDRAM_INITPLR0, 0xa8380000);
/* precharge 3 DDR clock cycle */
mtsdram(SDRAM_INITPLR1, 0x81900400);
/* EMR2 twr = 2tck */
mtsdram(SDRAM_INITPLR2, 0x81020000);
/* EMR3 twr = 2tck */
mtsdram(SDRAM_INITPLR3, 0x81030000);
/* EMR DLL ENABLE twr = 2tck */
mtsdram(SDRAM_INITPLR4, 0x81010404);
/* MR w/ DLL reset
* Note: 5 is CL. May need to be changed
*/
mtsdram(SDRAM_INITPLR5, 0x81000542);
/* precharge 3 DDR clock cycle */
mtsdram(SDRAM_INITPLR6, 0x81900400);
/* Auto-refresh trfc = 26tck */
mtsdram(SDRAM_INITPLR7, 0x8D080000);
/* Auto-refresh trfc = 26tck */
mtsdram(SDRAM_INITPLR8, 0x8D080000);
/* Auto-refresh */
mtsdram(SDRAM_INITPLR9, 0x8D080000);
/* Auto-refresh */
mtsdram(SDRAM_INITPLR10, 0x8D080000);
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
mtsdram(SDRAM_INITPLR11, 0x81000442);
mtsdram(SDRAM_INITPLR12, 0x81010780);
mtsdram(SDRAM_INITPLR13, 0x81010400);
mtsdram(SDRAM_INITPLR14, 0x00000000);
mtsdram(SDRAM_INITPLR15, 0x00000000);
/* SET MCIF0_CODT Die Termination On */
mtsdram(SDRAM_CODT, 0x0080f837);
mtsdram(SDRAM_MODT0, 0x01800000);
mtsdram(SDRAM_MODT1, 0x00000000);
mtsdram(SDRAM_WRDTR, 0x00000000);
/* SDRAM0_MCOPT2 (0X21) Start initialization */
mtsdram(SDRAM_MCOPT2, 0x20000000);
/* Step 5 */
do {
mfsdram(SDRAM_MCSTAT, val);
} while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
/* Step 6 */
/* SDRAM_DLCR */
mtsdram(SDRAM_DLCR, 0x030000a5);
/* SDRAM_RDCC */
mtsdram(SDRAM_RDCC, 0x40000000);
/* SDRAM_RQDC */
mtsdram(SDRAM_RQDC, 0x80000038);
/* SDRAM_RFDC */
mtsdram(SDRAM_RFDC, 0x00000209);
/* Enable memory controller */
mfsdram(SDRAM_MCOPT2, val);
val |= SDRAM_MCOPT2_DCEN_ENABLE;
mtsdram(SDRAM_MCOPT2, val);
#endif
return (CFG_MBYTES_SDRAM << 20);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
printf ("testdram\n");
#if defined (CONFIG_NAND_U_BOOT)
return 0;
#endif
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x00001000;
uint *p;
for (p = pstart; p < pend; p++) {
*p = 0xaaaaaaaa;
}
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
for (p = pstart; p < pend; p++) {
*p = 0x55555555;
}
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test passed!!!\n");
#endif
return 0;
}
#endif

2
board/amcc/ocotea/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

32
board/amcc/ocotea/ocotea.c
View File

@ -201,7 +201,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long dram_size = 0;
@ -214,36 +214,6 @@ long int initdram (int board_type)
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.

2
board/amcc/sequoia/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

4
board/amcc/sequoia/config.mk
View File

@ -28,6 +28,10 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFA0000
#
# When defining CONFIG_VIDEO, TEXT_BASE needs to be 0xFFF80000
# TEXT_BASE = 0xFFF80000
#
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1

2
board/amcc/sequoia/sdram.c
View File

@ -52,7 +52,7 @@ extern void denali_core_search_data_eye(void);
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL)

38
board/amcc/sequoia/sequoia.c
View File

@ -329,44 +329,6 @@ int checkboard(void)
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_MBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
/*
* Assign interrupts to PCI devices.

2
board/amcc/taihu/Makefile
View File

@ -37,7 +37,7 @@ clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

62
board/amcc/taihu/taihu.c
View File

@ -78,10 +78,10 @@ int checkboard(void)
}
/*************************************************************************
* long int initdram
* phys_size_t initdram
*
************************************************************************/
long int initdram(int board)
phys_size_t initdram(int board)
{
return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
}
@ -165,16 +165,20 @@ unsigned char spi_read(void)
return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
}
void taihu_spi_chipsel(int cs)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
gpio_write_bit(SPI_CS_GPIO0, cs);
return bus == 0 && cs == 0;
}
spi_chipsel_type spi_chipsel[]= {
taihu_spi_chipsel
};
void spi_cs_activate(struct spi_slave *slave)
{
gpio_write_bit(SPI_CS_GPIO0, 1);
}
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
void spi_cs_deactivate(struct spi_slave *slave)
{
gpio_write_bit(SPI_CS_GPIO0, 0);
}
#ifdef CONFIG_PCI
static unsigned char int_lines[32] = {
@ -196,45 +200,3 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* CONFIG_PCI */
#ifdef CFG_DRAM_TEST
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
unsigned long msr;
unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
msr = mfmsr();
mtmsr(msr & ~(MSR_EE));
for (k = 0; k < total_kbytes ;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0)
printf("%3d MB\r", k / 1024);
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
mtmsr(msr);
return 0;
}
#endif /* CFG_DRAM_TEST */

2
board/amcc/taishan/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

30
board/amcc/taishan/taishan.c
View File

@ -196,36 +196,6 @@ int checkboard (void)
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x04000000;
uint *pend = (uint *) 0x0fc00000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*

2
board/amcc/walnut/Makefile
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

18
board/amcc/walnut/walnut.c
View File

@ -85,27 +85,11 @@ int checkboard(void)
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/*
* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return spd_sdram();
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}

2
board/amcc/yosemite/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

52
board/amcc/yosemite/yosemite.c
View File

@ -200,7 +200,7 @@ int checkboard(void)
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
* initdram -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
void sdram_init(void)
phys_size_t initdram(int board)
{
register uint reg;
int tr1_bank1, tr1_bank2;
@ -327,57 +327,11 @@ void sdram_init(void)
sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
}
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*

2
board/amcc/yucca/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

30
board/amcc/yucca/yucca.c
View File

@ -586,36 +586,6 @@ u32 ddr_clktr(u32 default_val) {
return default_val;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*

2
board/amirix/ap1000/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/amirix/ap1000/ap1000.c
View File

@ -133,7 +133,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
char *s = getenv ("dramsize");

4
board/amirix/ap1000/init.S
View File

@ -28,7 +28,3 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr

2
board/amirix/ap1000/serial.c
View File

@ -19,9 +19,9 @@
*
*/
#include <common.h>
#include <asm/u-boot.h>
#include <asm/processor.h>
#include <common.h>
#include <command.h>
#include <config.h>

2
board/apollon/Makefile
View File

@ -39,7 +39,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

8
board/apollon/apollon.c
View File

@ -153,10 +153,8 @@ void ether_init(void)
do {
__raw_writew(0x1, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0) {
printf("1. eth reset err\n");
if (cnt == 0)
goto eth_reset_err_out;
}
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
@ -165,10 +163,8 @@ void ether_init(void)
do {
__raw_writew(0x0, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0) {
printf("2. eth reset err\n");
if (cnt == 0)
goto eth_reset_err_out;
}
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
udelay(1000);

2
board/apollon/mem.h
View File

@ -67,7 +67,7 @@
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
/* CS1: Ethernet */
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011200
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011203
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a

2
board/armadillo/Makefile
View File

@ -43,7 +43,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/assabet/Makefile
View File

@ -41,7 +41,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

2
board/atc/atc.c
View File

@ -340,7 +340,7 @@ int misc_init_r(void)
return (0);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;

6
board/atmel/at91cap9adk/Makefile
View File

@ -2,6 +2,10 @@
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
@ -41,7 +45,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

107
board/atmel/at91cap9adk/at91cap9adk.c
View File

@ -30,6 +30,8 @@
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
@ -70,6 +72,33 @@ static void at91cap9_serial_hw_init(void)
#endif
}
static void at91cap9_slowclock_hw_init(void)
{
/*
* On AT91CAP9 revC CPUs, the slow clock can be based on an
* internal impreciseRC oscillator or an external 32kHz oscillator.
* Switch to the latter.
*/
#define ARCH_ID_AT91CAP9_REVB 0x399
#define ARCH_ID_AT91CAP9_REVC 0x601
if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
unsigned i, tmp = at91_sys_read(AT91_SCKCR);
if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
extern void timer_init(void);
timer_init();
tmp |= AT91CAP9_SCKCR_OSC32EN;
at91_sys_write(AT91_SCKCR, tmp);
for (i = 0; i < 1200; i++)
udelay(1000);
tmp |= AT91CAP9_SCKCR_OSCSEL_32;
at91_sys_write(AT91_SCKCR, tmp);
udelay(200);
tmp &= ~AT91CAP9_SCKCR_RCEN;
at91_sys_write(AT91_SCKCR, tmp);
}
}
}
static void at91cap9_nor_hw_init(void)
{
unsigned long csa;
@ -116,7 +145,12 @@ static void at91cap9_nand_hw_init(void)
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
@ -162,7 +196,7 @@ static void at91cap9_macb_hw_init(void)
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
@ -170,6 +204,11 @@ static void at91cap9_macb_hw_init(void)
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0 << 8)) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PB22) |
pin_to_mask(AT91_PIN_PB25) |
@ -228,6 +267,65 @@ static void at91cap9_uhp_hw_init(void)
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91CAP9_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
}
static void at91cap9_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
gd->fb_base = 0;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
@ -239,6 +337,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91cap9_serial_hw_init();
at91cap9_slowclock_hw_init();
at91cap9_nor_hw_init();
#ifdef CONFIG_CMD_NAND
at91cap9_nand_hw_init();
@ -252,7 +351,9 @@ int board_init(void)
#ifdef CONFIG_USB_OHCI_NEW
at91cap9_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
at91cap9_lcd_hw_init();
#endif
return 0;
}

3
board/atmel/at91cap9adk/nand.c
View File

@ -63,6 +63,9 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20;

2
board/atmel/at91rm9200dk/Makefile Executable file → Normal file
View File

@ -38,7 +38,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

6
board/atmel/at91sam9260ek/Makefile
View File

@ -2,6 +2,10 @@
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
@ -41,7 +45,7 @@ clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

15
board/atmel/at91sam9260ek/at91sam9260ek.c
View File

@ -80,8 +80,8 @@ static void at91sam9260ek_nand_hw_init(void)
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
@ -90,7 +90,12 @@ static void at91sam9260ek_nand_hw_init(void)
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
@ -144,7 +149,7 @@ static void at91sam9260ek_macb_hw_init(void)
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
@ -154,7 +159,7 @@ static void at91sam9260ek_macb_hw_init(void)
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0 << 8) |
(AT91_RSTC_ERSTL & (0x0 << 8)) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */

3
board/atmel/at91sam9260ek/nand.c
View File

@ -68,6 +68,9 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
nand->dev_ready = at91sam9260ek_nand_ready;
nand->chip_delay = 20;

57
board/atmel/at91sam9261ek/Makefile Normal file
View File

@ -0,0 +1,57 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9261ek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

258
board/atmel/at91sam9261ek/at91sam9261ek.c Normal file
View File

@ -0,0 +1,258 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9261ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PC15, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PC14, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9261ek_spi_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
}
#endif
#ifdef CONFIG_DRIVER_DM9000
static void at91sam9261ek_dm9000_hw_init(void)
{
/* Configure SMC CS2 for DM9000 */
at91_sys_write(AT91_SMC_SETUP(2),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(2),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
at91_sys_write(AT91_SMC_CYCLE(2),
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(2),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
AT91_SMC_TDF_(1));
/* Configure Reset signal as output */
at91_set_gpio_output(AT91_PIN_PC10, 0);
/* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PC11, 0);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9261_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
}
static void at91sam9261ek_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
gd->fb_base = AT91SAM9261_SRAM_BASE;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9261EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9261ek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9261ek_spi_hw_init();
#endif
#ifdef CONFIG_DRIVER_DM9000
at91sam9261ek_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9261ek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

1
board/atmel/at91sam9261ek/config.mk Normal file
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@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

78
board/atmel/at91sam9261ek/led.c Normal file
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@ -0,0 +1,78 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PA23 /* this is the power led */
#define GREEN_LED AT91_PIN_PA13 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
at91_set_gpio_value(YELLOW_LED, 1);
}

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board/atmel/at91sam9261ek/nand.c Normal file
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/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PC14, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PC14, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PC15);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
nand->dev_ready = at91sam9261ek_nand_ready;
nand->chip_delay = 20;
return 0;
}

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board/atmel/at91sam9261ek/partition.c Normal file
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/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

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board/atmel/at91sam9263ek/Makefile Normal file
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#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9263ek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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board/atmel/at91sam9263ek/at91sam9263ek.c Normal file
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/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9263ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9263ek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA,
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOCDE);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PA22, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PD15, 1);
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9263ek_spi_hw_init(void)
{
at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
}
#endif
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PC25) => PHY normal mode (not Test mode)
* ERX0 (PE25) => PHY ADDR0
* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0 << 8)) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
#endif
}
#endif
#ifdef CONFIG_USB_OHCI_NEW
static void at91sam9263ek_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
at91_set_gpio_output(AT91_PIN_PA21, 0);
at91_set_gpio_output(AT91_PIN_PA24, 0);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9263_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
}
static void at91sam9263ek_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
gd->fb_base = AT91SAM9263_SRAM0_BASE;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9263ek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9263ek_spi_hw_init();
#endif
#ifdef CONFIG_MACB
at91sam9263ek_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
at91sam9263ek_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9263ek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

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TEXT_BASE = 0x23f00000

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