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riscv: board: Add nx25-ae250 to support RISC-V
Add nx25-ae250 board to do platform initializations. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
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24
board/AndesTech/nx25-ae250/Kconfig
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board/AndesTech/nx25-ae250/Kconfig
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if TARGET_NX25_AE250
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config SYS_CPU
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default "nx25"
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config SYS_BOARD
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default "nx25-ae250"
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config SYS_VENDOR
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default "AndesTech"
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config SYS_SOC
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default "ae250"
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config SYS_CONFIG_NAME
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default "nx25-ae250"
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config ENV_SIZE
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default 0x2000 if ENV_IS_IN_SPI_FLASH
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config ENV_OFFSET
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default 0x140000 if ENV_IS_IN_SPI_FLASH
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endif
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board/AndesTech/nx25-ae250/MAINTAINERS
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board/AndesTech/nx25-ae250/MAINTAINERS
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NX25-AE250 BOARD
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M: Rick Chen <rick@andestech.com>
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S: Maintained
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F: board/AndesTech/nx25-ae250/
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F: include/configs/nx25-ae250.h
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F: configs/nx25-ae250_defconfig
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board/AndesTech/nx25-ae250/Makefile
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board/AndesTech/nx25-ae250/Makefile
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#
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# Copyright (C) 2017 Andes Technology Corporation.
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# Rick Chen, Andes Technology Corporation <rick@andestech.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := nx25-ae250.o
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77
board/AndesTech/nx25-ae250/nx25-ae250.c
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board/AndesTech/nx25-ae250/nx25-ae250.c
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/mach-types.h>
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#include <common.h>
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#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
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#include <netdev.h>
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#endif
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#include <linux/io.h>
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#include <faraday/ftsdc010.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initializations
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*/
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_AE250;
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gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
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return 0;
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}
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int dram_init(void)
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{
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unsigned long sdram_base = PHYS_SDRAM_0;
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unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
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unsigned long actual_size;
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actual_size = get_ram_size((void *)sdram_base, expected_size);
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gd->ram_size = actual_size;
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if (expected_size != actual_size) {
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
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actual_size >> 20, expected_size >> 20);
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}
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
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int board_eth_init(bd_t *bd)
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{
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return ftmac100_initialize(bd);
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}
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#endif
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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#ifndef CONFIG_DM_MMC
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#ifdef CONFIG_FTSDC010
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ftsdc010_mmc_init(0);
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#endif
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#endif
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return 0;
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}
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