imx: Add basic support for the NXP IMXRT10xx SoC family

Add i.IMXRT family basic support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
This commit is contained in:
Giulio Benetti 2020-01-10 15:51:47 +01:00 committed by Stefano Babic
parent 6a63a873b7
commit 77eb9a90dd
11 changed files with 140 additions and 3 deletions

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@ -807,6 +807,14 @@ config ARCH_IMX8M
select SUPPORT_SPL
imply CMD_DM
config ARCH_IMXRT
bool "NXP i.MXRT platform"
select CPU_V7M
select DM
select DM_SERIAL
select SUPPORT_SPL
imply CMD_DM
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
@ -1732,6 +1740,8 @@ source "arch/arm/mach-imx/imx8/Kconfig"
source "arch/arm/mach-imx/imx8m/Kconfig"
source "arch/arm/mach-imx/imxrt/Kconfig"
source "arch/arm/mach-imx/mxs/Kconfig"
source "arch/arm/mach-omap2/Kconfig"

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@ -104,11 +104,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif

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@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#endif /* __ASM_ARCH_CLOCK_H */

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@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 gpio_psr; /* pad satus */
};
#endif
#endif /* __ASM_ARCH_GPIO_H__ */

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@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright(C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef __ASM_ARCH_IMX_REGS_H__
#define __ASM_ARCH_IMX_REGS_H__
#define ARCH_MXC
#define GPIO1_BASE_ADDR 0x401B8000
#define GPIO2_BASE_ADDR 0x401BC000
#define GPIO3_BASE_ADDR 0x401C0000
#define GPIO4_BASE_ADDR 0x401C4000
#define GPIO5_BASE_ADDR 0x400C0000
#define ANATOP_BASE_ADDR 0x400d8000
#endif /* __ASM_ARCH_IMX_REGS_H__ */

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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef _ASM_ARCH_IMXRT_H
#define _ASM_ARCH_IMXRT_H
#endif /* _ASM_ARCH_IMXRT_H */

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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 NXP
*/
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>
#endif /* _ASM_ARCH_SYS_PROTO_H */

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@ -27,7 +27,7 @@ endif
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
@ -226,5 +226,6 @@ obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o

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@ -0,0 +1,13 @@
if ARCH_IMXRT
config IMXRT
bool
config IMXRT1050
bool
select IMXRT
config SYS_SOC
default "imxrt"
endif

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@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2019
# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
#
obj-y := soc.o

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@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/armv7_mpu.h>
int arch_cpu_init(void)
{
int i;
struct mpu_region_config imxrt1050_region_config[] = {
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_4GB },
{ PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
{ DMAMEM_BASE,
REGION_2, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
};
/*
* Configure the memory protection unit (MPU) to allow full access to
* the whole 4GB address space.
*/
disable_mpu();
for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
mpu_config(&imxrt1050_region_config[i]);
enable_mpu();
return 0;
}