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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 15:38:51 +09:00
ppc4xx: Fix size setup in Kilauea DDR2 init routine
The size was initilized wrong. Instead of 256MB, the DDR2 controller was setup to 512MB. Now the correct values is used. This patch also does a little cleanup and adds a comment here. Signed-off-by: Stefan Roese <sr@denx.de>
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@ -51,8 +51,8 @@ ext_bus_cntlr_init:
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/* Step 3 */
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/* Step 3 */
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/* SET SDRAM_MB0CF base addr 00000000 - 128MB */
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/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
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mtsdram_as(SDRAM_MB0CF, 0x00007701); /* 8 -- 7*/
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mtsdram_as(SDRAM_MB0CF, 0x00006701);
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/* SET SDRAM_MB1CF - Not enabled */
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/* SET SDRAM_MB1CF - Not enabled */
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mtsdram_as(SDRAM_MB1CF, 0x00000000);
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mtsdram_as(SDRAM_MB1CF, 0x00000000);
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@ -64,19 +64,19 @@ ext_bus_cntlr_init:
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mtsdram_as(SDRAM_MB3CF, 0x00000000);
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mtsdram_as(SDRAM_MB3CF, 0x00000000);
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/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
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/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
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mtsdram_as(SDRAM_CLKTR,0x80000000);
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mtsdram_as(SDRAM_CLKTR, 0x80000000);
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/* Refresh Time register (0x30) Refresh every 7.8125uS */
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/* Refresh Time register (0x30) Refresh every 7.8125uS */
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mtsdram_as(SDRAM_RTR, 0x06180000);
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mtsdram_as(SDRAM_RTR, 0x06180000);
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/* SDRAM_SDTR1 */
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/* SDRAM_SDTR1 */
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mtsdram_as(SDRAM_SDTR1,0x80201000);
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mtsdram_as(SDRAM_SDTR1, 0x80201000);
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/* SDRAM_SDTR2 */
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/* SDRAM_SDTR2 */
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mtsdram_as(SDRAM_SDTR2,0x32204232);
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mtsdram_as(SDRAM_SDTR2, 0x32204232);
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/* SDRAM_SDTR3 */
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/* SDRAM_SDTR3 */
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mtsdram_as(SDRAM_SDTR3,0x080b0d1a);
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mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
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mtsdram_as(SDRAM_MMODE, 0x00000442);
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mtsdram_as(SDRAM_MMODE, 0x00000442);
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mtsdram_as(SDRAM_MEMODE, 0x00000404);
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mtsdram_as(SDRAM_MEMODE, 0x00000404);
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@ -135,16 +135,16 @@ pll_wait:
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/* Step 6 */
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/* Step 6 */
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/* SDRAM_DLCR */
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/* SDRAM_DLCR */
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mtsdram_as(SDRAM_DLCR,0x030000a5);
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mtsdram_as(SDRAM_DLCR, 0x030000a5);
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/* SDRAM_RDCC */
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/* SDRAM_RDCC */
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mtsdram_as(SDRAM_RDCC,0x40000000);
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mtsdram_as(SDRAM_RDCC, 0x40000000);
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/* SDRAM_RQDC */
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/* SDRAM_RQDC */
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mtsdram_as(SDRAM_RQDC,0x80000038);
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mtsdram_as(SDRAM_RQDC, 0x80000038);
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/* SDRAM_RFDC */
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/* SDRAM_RFDC */
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mtsdram_as(SDRAM_RFDC,0x00000209);
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mtsdram_as(SDRAM_RFDC, 0x00000209);
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/* Enable memory controller */
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/* Enable memory controller */
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mtsdram_as(SDRAM_MCOPT2, 0x28000000);
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mtsdram_as(SDRAM_MCOPT2, 0x28000000);
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