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drivers: mmc: iproc_sdhci: enable HS200 mode
Add tuning functionality which is needed for HS200 mode. For HS200, program the correct needed 1.8 voltage Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
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@ -10,8 +10,11 @@
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#include <malloc.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <sdhci.h>
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#include <asm/global_data.h>
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#include <asm/global_data.h>
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#include "mmc_private.h"
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#include <linux/delay.h>
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#include <linux/delay.h>
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#define MAX_TUNING_LOOP 40
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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struct sdhci_iproc_host {
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struct sdhci_iproc_host {
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@ -140,17 +143,89 @@ static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
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static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
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static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
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{
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{
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u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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struct mmc *mmc = (struct mmc *)host->mmc;
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u32 ctrl;
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/* Reset UHS mode bits */
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if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
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ctrl &= ~SDHCI_CTRL_UHS_MASK;
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl |= SDHCI_CTRL_VDD_180;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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}
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if (host->mmc->ddr_mode)
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sdhci_set_uhs_timing(host);
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ctrl |= UHS_DDR50_BUS_SPEED;
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return 0;
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}
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static void sdhci_start_tuning(struct sdhci_host *host)
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{
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u32 ctrl;
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl |= SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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return 0;
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
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}
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static void sdhci_end_tuning(struct sdhci_host *host)
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{
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/* Enable only interrupts served by the SD controller */
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sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
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SDHCI_INT_ENABLE);
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/* Mask all sdhci interrupt sources */
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sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
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}
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static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode)
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{
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struct mmc_cmd cmd;
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u32 ctrl;
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u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
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struct sdhci_host *host = dev_get_priv(mmc->dev);
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char tuning_loop_counter = MAX_TUNING_LOOP;
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int ret = 0;
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sdhci_start_tuning(host);
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cmd.cmdidx = opcode;
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cmd.resp_type = MMC_RSP_R1;
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cmd.cmdarg = 0;
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if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
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blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
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sdhci_writew(host, blocksize, SDHCI_BLOCK_SIZE);
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sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
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sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
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do {
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mmc_send_cmd(mmc, &cmd, NULL);
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if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
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/*
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* For tuning command, do not do busy loop. As tuning
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* is happening (CLK-DATA latching for setup/hold time
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* requirements), give time to complete
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*/
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udelay(1);
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (tuning_loop_counter-- == 0)
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break;
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} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
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if (tuning_loop_counter < 0 || (!(ctrl & SDHCI_CTRL_TUNED_CLK))) {
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ctrl &= ~(SDHCI_CTRL_TUNED_CLK | SDHCI_CTRL_EXEC_TUNING);
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sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
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printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode);
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ret = -EIO;
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}
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sdhci_end_tuning(host);
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return ret;
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}
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}
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static struct sdhci_ops sdhci_platform_ops = {
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static struct sdhci_ops sdhci_platform_ops = {
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@ -163,6 +238,7 @@ static struct sdhci_ops sdhci_platform_ops = {
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.write_b = sdhci_iproc_writeb,
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.write_b = sdhci_iproc_writeb,
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#endif
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#endif
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.set_ios_post = sdhci_iproc_set_ios_post,
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.set_ios_post = sdhci_iproc_set_ios_post,
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.platform_execute_tuning = sdhci_iproc_execute_tuning,
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};
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};
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struct iproc_sdhci_plat {
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struct iproc_sdhci_plat {
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@ -190,9 +266,7 @@ static int iproc_sdhci_probe(struct udevice *dev)
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host->name = dev->name;
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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host->ioaddr = dev_read_addr_ptr(dev);
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host->voltages = MMC_VDD_165_195 |
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host->quirks = SDHCI_QUIRK_BROKEN_R1B;
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MMC_VDD_32_33 | MMC_VDD_33_34;
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host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B;
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host->host_caps = MMC_MODE_DDR_52MHz;
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host->host_caps = MMC_MODE_DDR_52MHz;
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host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
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host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
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host->ops = &sdhci_platform_ops;
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host->ops = &sdhci_platform_ops;
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