mips: mtmips: add two reference boards for mt7620
The mt7620_rfb board supports integrated 10/100M PHYs plus two external giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB. The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a 16MB SPI-NOR flash. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Daniel Schwierzeck
parent
dd4fdc0b14
commit
76880b08c4
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@ -14,6 +14,8 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
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dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
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dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
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dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
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dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
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dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
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dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
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dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
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dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
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@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "mt7620.dtsi"
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/ {
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compatible = "mediatek,mt7620-mt7530-rfb", "mediatek,mt7620-soc";
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model = "MediaTek MT7620-MT7530 RFB (MTKC712)";
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aliases {
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serial0 = &uartlite;
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spi0 = &spi0;
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};
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chosen {
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stdout-path = &uartlite;
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};
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};
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&uartlite {
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status = "okay";
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};
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&pinctrl {
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state_default: pin_state {
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pleds {
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groups = "ephy led", "wled";
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function = "led";
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};
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gpios {
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groups = "pa", "uartf";
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function = "gpio";
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};
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};
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gsw_pins: gsw_pins {
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mdio {
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groups = "mdio";
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function = "mdio";
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};
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rgmii1 {
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groups = "rgmii1";
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function = "rgmii1";
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};
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};
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};
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&spi0 {
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status = "okay";
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num-cs = <2>;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <25000000>;
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reg = <0>;
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};
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};
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&gpio0 {
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pa0_pull_low {
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gpio-hog;
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output-low;
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gpios = <20 GPIO_ACTIVE_HIGH>;
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};
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pa1_pull_low {
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gpio-hog;
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output-low;
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gpios = <21 GPIO_ACTIVE_HIGH>;
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};
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};
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ð {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&gsw_pins>;
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port5 {
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phy-mode = "rgmii";
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phy-addr = <5>;
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fixed-link {
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full-duplex;
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speed = <1000>;
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mediatek,mt7530;
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mediatek,mt7530-reset = <&gpio0 10 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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@ -0,0 +1,97 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "mt7620.dtsi"
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/ {
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compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc";
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model = "MediaTek MT7620 RFB (WS2120)";
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aliases {
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serial0 = &uartlite;
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spi0 = &spi0;
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};
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chosen {
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stdout-path = &uartlite;
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};
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};
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&uartlite {
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status = "okay";
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};
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&pinctrl {
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state_default: pin_state {
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pleds {
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groups = "ephy led", "wled";
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function = "led";
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};
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gpios {
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groups = "uartf";
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function = "gpio";
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};
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};
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gsw_pins: gsw_pins {
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mdio {
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groups = "mdio";
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function = "mdio";
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};
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rgmii1 {
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groups = "rgmii1";
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function = "rgmii1";
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};
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rgmii2 {
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groups = "rgmii2";
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function = "rgmii2";
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};
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};
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};
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&spi0 {
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status = "okay";
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num-cs = <2>;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <25000000>;
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reg = <0>;
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};
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};
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ð {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&gsw_pins>;
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port4 {
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phy-mode = "rgmii";
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phy-addr = <4>;
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};
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port5 {
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phy-mode = "rgmii";
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phy-addr = <5>;
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};
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};
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&mmc {
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bus-width = <4>;
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cap-sd-highspeed;
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status = "okay";
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};
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@ -7,6 +7,21 @@ config DEBUG_UART_BOARD_INIT
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choice
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prompt "Board select"
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config BOARD_MT7620_RFB
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bool "MediaTek MT7620 RFB"
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help
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The reference design of MT7620A (WS2120). The board has 64 MiB DDR2,
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8 MiB SPI-NOR flash, 1 built-in 6 port switch (two GE PHYs and five
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FE PHYs,one port can be configured to use either FE PHY or GE PHY),
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1 UART, 1 USB host, 1 SDXC, 1 PCIe socket and JTAG pins.
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config BOARD_MT7620_MT7530_RFB
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bool "MediaTek MT7620-MT7530 RFB"
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help
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The reference design of MT7620DA (MTKC712). The board has 64 MiB
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intergrated DDR2 KGD, 16 MiB SPI-NOR flash, an external 5-port giga
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switch MT7530 and 1 UART.
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endchoice
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choice
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@ -51,4 +66,6 @@ config CPU_FREQ_MULTI
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default 6 if CPU_FREQ_600MHZ
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default 7 if CPU_FREQ_620MHZ
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source "board/mediatek/mt7620/Kconfig"
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endif
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@ -0,0 +1,12 @@
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if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
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config SYS_BOARD
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default "mt7620"
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config SYS_VENDOR
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default "mediatek"
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config SYS_CONFIG_NAME
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default "mt7620"
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endif
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@ -0,0 +1,9 @@
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MT7620_RFB BOARD
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M: Weijie Gao <weijie.gao@mediatek.com>
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S: Maintained
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F: board/mediatek/mt7620
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F: include/configs/mt7620.h
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F: configs/mt7620_rfb_defconfig
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F: configs/mt7620_mt7530_rfb_defconfig
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F: arch/mips/dts/mediatek,mt7620-rfb.dts
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F: arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += board.o
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@ -0,0 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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@ -0,0 +1,58 @@
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CONFIG_MIPS=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x30000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BASE=0xb0000c00
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CONFIG_DEBUG_UART_CLOCK=40000000
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CONFIG_ARCH_MTMIPS=y
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CONFIG_BOARD_MT7620_MT7530_RFB=y
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CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb"
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CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
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CONFIG_MIPS_BOOT_FDT=y
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_NOR_SUPPORT=y
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_CRC32 is not set
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# CONFIG_CMD_DM is not set
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_SPI=y
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_MII=y
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# CONFIG_CMD_MDIO is not set
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# CONFIG_PARTITIONS is not set
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts resets reset-names"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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# CONFIG_SIMPLE_BUS is not set
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# CONFIG_SPL_SIMPLE_BUS is not set
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CONFIG_GPIO_HOG=y
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# CONFIG_INPUT is not set
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CONFIG_SPI_FLASH_SFDP_SUPPORT=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_XMC=y
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CONFIG_MT7620_ETH=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SPI=y
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CONFIG_MT7620_SPI=y
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CONFIG_LZMA=y
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CONFIG_SPL_LZMA=y
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@ -0,0 +1,76 @@
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CONFIG_MIPS=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x30000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BASE=0xb0000c00
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CONFIG_DEBUG_UART_CLOCK=40000000
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CONFIG_ARCH_MTMIPS=y
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CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb"
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CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
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CONFIG_MIPS_BOOT_FDT=y
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_NOR_SUPPORT=y
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_CRC32 is not set
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# CONFIG_CMD_DM is not set
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_MII=y
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# CONFIG_CMD_MDIO is not set
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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# CONFIG_SPL_DOS_PARTITION is not set
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# CONFIG_ISO_PARTITION is not set
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CONFIG_EFI_PARTITION=y
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# CONFIG_SPL_EFI_PARTITION is not set
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts resets reset-names"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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# CONFIG_SIMPLE_BUS is not set
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# CONFIG_SPL_SIMPLE_BUS is not set
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# CONFIG_SPL_BLK is not set
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CONFIG_GPIO_HOG=y
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# CONFIG_INPUT is not set
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CONFIG_MMC=y
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CONFIG_DM_MMC=y
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# CONFIG_MMC_QUIRKS is not set
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# CONFIG_MMC_HW_PARTITIONING is not set
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CONFIG_MMC_MTK=y
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CONFIG_SPI_FLASH_SFDP_SUPPORT=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_XMC=y
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CONFIG_MT7620_ETH=y
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CONFIG_PHY=y
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CONFIG_MT7620_USB_PHY=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SPI=y
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CONFIG_MT7620_SPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_LZMA=y
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CONFIG_SPL_LZMA=y
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