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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
imx6: SPL support for iMX6 SabreSD
This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port (Switch 1 or 2 of SW6) Signed-off-by: John Tobias <john.tobias.ph@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
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@ -27,8 +27,12 @@
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#include <i2c.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include <power/pfuze100_pmic.h>
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#include <asm/arch/mx6-ddr.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#define BOOT_CFG 0x020D8004
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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@ -55,8 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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int dram_init(void)
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{
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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gd->ram_size = imx_ddr_size();
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return 0;
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return 0;
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}
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}
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@ -253,6 +256,7 @@ int board_mmc_getcd(struct mmc *mmc)
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int board_mmc_init(bd_t *bis)
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int board_mmc_init(bd_t *bis)
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{
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{
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#ifndef CONFIG_SPL_BUILD
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s32 status = 0;
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s32 status = 0;
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int i;
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int i;
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@ -293,6 +297,43 @@ int board_mmc_init(bd_t *bis)
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}
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}
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return status;
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return status;
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#else
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unsigned reg = readl(BOOT_CFG) >> 11;
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/*
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* Upon reading BOOT_CFG register the following map is done:
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* Bit 11 and 12 of BOOT_CFG register can determine the current
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* mmc port
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* 0x1 SD1
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* 0x2 SD2
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* 0x3 SD4
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*/
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switch (reg & 0x3) {
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case 0x1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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case 0x2:
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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case 0x3:
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imx_iomux_v3_setup_multiple_pads(
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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}
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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#endif
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}
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}
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#endif
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#endif
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@ -607,3 +648,144 @@ int checkboard(void)
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puts("Board: MX6-SabreSD\n");
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puts("Board: MX6-SabreSD\n");
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return 0;
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return 0;
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}
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}
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#include <libfdt.h>
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const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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.dram_dqm0 = 0x00020030,
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.dram_dqm1 = 0x00020030,
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.dram_dqm2 = 0x00020030,
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.dram_dqm3 = 0x00020030,
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.dram_dqm4 = 0x00020030,
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.dram_dqm5 = 0x00020030,
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.dram_dqm6 = 0x00020030,
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.dram_dqm7 = 0x00020030,
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};
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const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000C0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x001F001F,
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.p0_mpwldectrl1 = 0x001F001F,
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.p1_mpwldectrl0 = 0x00440044,
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.p1_mpwldectrl1 = 0x00440044,
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.p0_mpdgctrl0 = 0x434B0350,
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.p0_mpdgctrl1 = 0x034C0359,
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.p1_mpdgctrl0 = 0x434B0350,
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.p1_mpdgctrl1 = 0x03650348,
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.p0_mprddlctl = 0x4436383B,
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.p1_mprddlctl = 0x39393341,
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.p0_mpwrdlctl = 0x35373933,
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.p1_mpwrdlctl = 0x48254A36,
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 1600,
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.density = 4,
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.width = 64,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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/*
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* This section require the differentiation
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* between iMX6 Sabre Families.
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* But for now, it will configure only for
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* SabreSD.
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*/
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = mem_ddr.width/32,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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#ifdef RTT_NOM_120OHM
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.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
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#else
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.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
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#endif
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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};
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mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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/* iomux and setup of i2c */
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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void reset_cpu(ulong addr)
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{
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}
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#endif
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