mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-i2c
This commit is contained in:
Tom Rini
commit
755b06d1c0
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@ -17,6 +17,7 @@
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#include <i2c.h>
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#include <fdtdec.h>
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#include <mapmem.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -67,6 +68,9 @@ struct cdns_i2c_regs {
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#define CDNS_I2C_FIFO_DEPTH 16
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#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
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#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
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#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
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#ifdef DEBUG
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static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
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@ -114,6 +118,13 @@ struct i2c_cdns_bus {
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int id;
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unsigned int input_freq;
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struct cdns_i2c_regs __iomem *regs; /* register base */
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int hold_flag;
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u32 quirks;
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};
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struct cdns_i2c_platform_data {
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u32 quirks;
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};
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/* Wait for an interrupt */
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@ -122,10 +133,10 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
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int timeout, int_status;
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for (timeout = 0; timeout < 100; timeout++) {
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udelay(100);
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int_status = readl(&cdns_i2c->interrupt_status);
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if (int_status & mask)
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break;
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udelay(100);
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}
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/* Clear interrupt status flags */
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@ -215,43 +226,25 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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return 0;
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}
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/* Probe to see if a chip is present. */
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static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
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uint chip_flags)
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{
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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/* Attempt to read a byte */
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
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CDNS_I2C_CONTROL_RW);
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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writel(0xFF, ®s->interrupt_status);
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writel(chip_addr, ®s->address);
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writel(1, ®s->transfer_size);
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return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_NACK) &
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CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
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}
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static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 len, bool next_is_read)
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u32 len)
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{
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u8 *cur_data = data;
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
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CDNS_I2C_CONTROL_HOLD);
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/* if next is a read, we need to clear HOLD, doesn't work */
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if (next_is_read)
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Set the controller in Master transmit mode and clear FIFO */
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
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/* Check message size against FIFO depth, and set hold bus bit
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* if it is greater than FIFO depth
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*/
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if (len > CDNS_I2C_FIFO_DEPTH)
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setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Clear the interrupts in status register */
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writel(0xFF, ®s->interrupt_status);
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writel(addr, ®s->address);
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while (len--) {
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@ -267,54 +260,107 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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}
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/* All done... release the bus */
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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if (!i2c_bus->hold_flag)
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Wait for the address and data to be sent */
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if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
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return -ETIMEDOUT;
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return 0;
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}
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static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 len)
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static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
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{
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u32 status;
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u32 i = 0;
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u8 *cur_data = data;
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return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
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}
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/* TODO: Fix this */
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static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 recv_count)
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{
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u8 *cur_data = data;
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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int curr_recv_count;
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int updatetx, hold_quirk;
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/* Check the hardware can handle the requested bytes */
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if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
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if ((recv_count < 0))
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return -EINVAL;
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curr_recv_count = recv_count;
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/* Check for the message size against the FIFO depth */
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if (recv_count > CDNS_I2C_FIFO_DEPTH)
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setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
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CDNS_I2C_CONTROL_RW);
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if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
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curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
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writel(curr_recv_count, ®s->transfer_size);
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} else {
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writel(recv_count, ®s->transfer_size);
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}
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/* Start reading data */
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writel(addr, ®s->address);
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writel(len, ®s->transfer_size);
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/* Wait for data */
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do {
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status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_DATA);
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if (!status) {
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/* Release the bus */
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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return -ETIMEDOUT;
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updatetx = recv_count > curr_recv_count;
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hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
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while (recv_count) {
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while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
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if (recv_count < CDNS_I2C_FIFO_DEPTH &&
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!i2c_bus->hold_flag) {
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clrbits_le32(®s->control,
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CDNS_I2C_CONTROL_HOLD);
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}
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*(cur_data)++ = readl(®s->data);
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recv_count--;
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curr_recv_count--;
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if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
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break;
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}
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debug("Read %d bytes\n",
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len - readl(®s->transfer_size));
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for (; i < len - readl(®s->transfer_size); i++)
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*(cur_data++) = readl(®s->data);
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} while (readl(®s->transfer_size) != 0);
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/* All done... release the bus */
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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#ifdef DEBUG
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cdns_i2c_debug_status(regs);
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#endif
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if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
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/* wait while fifo is full */
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while (readl(®s->transfer_size) !=
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(curr_recv_count - CDNS_I2C_FIFO_DEPTH))
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;
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/*
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* Check number of bytes to be received against maximum
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* transfer size and update register accordingly.
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*/
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if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
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CDNS_I2C_TRANSFER_SIZE) {
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writel(CDNS_I2C_TRANSFER_SIZE,
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®s->transfer_size);
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curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
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CDNS_I2C_FIFO_DEPTH;
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} else {
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writel(recv_count - CDNS_I2C_FIFO_DEPTH,
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®s->transfer_size);
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curr_recv_count = recv_count;
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}
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} else if (recv_count && !hold_quirk && !curr_recv_count) {
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writel(addr, ®s->address);
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if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
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writel(CDNS_I2C_TRANSFER_SIZE,
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®s->transfer_size);
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curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
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} else {
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writel(recv_count, ®s->transfer_size);
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curr_recv_count = recv_count;
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}
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}
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}
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/* Wait for the address and data to be sent */
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if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
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return -ETIMEDOUT;
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return 0;
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}
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@ -322,19 +368,41 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
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int ret;
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int ret, count;
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bool hold_quirk;
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hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
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if (nmsgs > 1) {
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/*
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* This controller does not give completion interrupt after a
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* master receive message if HOLD bit is set (repeated start),
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* resulting in SW timeout. Hence, if a receive message is
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* followed by any other message, an error is returned
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* indicating that this sequence is not supported.
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*/
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for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
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if (msg[count].flags & I2C_M_RD) {
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printf("Can't do repeated start after a receive message\n");
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return -EOPNOTSUPP;
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}
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}
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i2c_bus->hold_flag = 1;
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setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
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} else {
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i2c_bus->hold_flag = 0;
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}
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD) {
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ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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} else {
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ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
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msg->len, next_is_read);
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msg->len);
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}
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if (ret) {
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debug("i2c_write: error sending\n");
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@ -348,11 +416,16 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
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{
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
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struct cdns_i2c_platform_data *pdata =
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(struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
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i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
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if (!i2c_bus->regs)
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return -ENOMEM;
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if (pdata)
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i2c_bus->quirks = pdata->quirks;
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i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
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return 0;
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@ -360,12 +433,15 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
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static const struct dm_i2c_ops cdns_i2c_ops = {
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.xfer = cdns_i2c_xfer,
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.probe_chip = cdns_i2c_probe_chip,
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.set_bus_speed = cdns_i2c_set_bus_speed,
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};
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static const struct cdns_i2c_platform_data r1p10_i2c_def = {
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.quirks = CDNS_I2C_BROKEN_HOLD_BIT,
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};
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static const struct udevice_id cdns_i2c_of_match[] = {
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{ .compatible = "cdns,i2c-r1p10" },
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{ .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
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{ .compatible = "cdns,i2c-r1p14" },
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{ /* end of table */ }
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};
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@ -86,6 +86,16 @@ static int i2c_mux_post_probe(struct udevice *mux)
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debug("%s: %s\n", __func__, mux->name);
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priv->selected = -1;
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/* if parent is of i2c uclass already, we'll take that, otherwise
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* look if we find an i2c-parent phandle
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*/
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if (UCLASS_I2C == device_get_uclass_id(mux->parent)) {
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priv->i2c_bus = dev_get_parent(mux);
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debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus,
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priv->i2c_bus->name);
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return 0;
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}
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ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
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&priv->i2c_bus);
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if (ret)
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