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Last-minute fixes for 2019.1:

Browse Source 
- clamp DRAM size to below 32bit for 32bit targets to support 4GB
 - fix copyright notice on some Rockchip-contributed files
 - adjust vdd_log for the RK3399-Q7 to improve stability in some workloads
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Merge tag 'for-master-20190103' of git://git.denx.de/u-boot-rockchip

Last-minute fixes for 2019.1:
- clamp DRAM size to below 32bit for 32bit targets to support 4GB
- fix copyright notice on some Rockchip-contributed files
- adjust vdd_log for the RK3399-Q7 to improve stability in some workloads
This commit is contained in:
Tom Rini 2019-01-03 08:39:44 -05:00
commit 7436f5e54d
16 changed files with 317 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/dts/rk3399-puma.dtsi
View File

@ -172,10 +172,7 @@
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
/* for rockchip boot on */
rockchip,pwm_id= <2>;
rockchip,pwm_voltage = <1000000>;
regulator-init-microvolt = <950000>;
};
};

4
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2015 Google, Inc
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <asm/io.h>

18
arch/arm/mach-rockchip/sdram_common.c
View File

@ -48,6 +48,24 @@ size_t rockchip_sdram_size(phys_addr_t reg)
rank, col, bk, cs0_row, bw, row_3_4);
}
/*
* This is workaround for issue we can't get correct size for 4GB ram
* in 32bit system and available before we really need ram space
* out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
* The size of 4GB is '0x1 00000000', and this value will be truncated
* to 0 in 32bit system, and system can not get correct ram size.
* Rockchip SoCs reserve a blob of space for peripheral near 4GB,
* and we are now setting SDRAM_MAX_SIZE as max available space for
* ram in 4GB, so we can use this directly to workaround the issue.
* TODO:
* 1. update correct value for SDRAM_MAX_SIZE as what dram
* controller sees.
* 2. update board_get_usable_ram_top() and dram_init_banksize()
* to reserve memory for peripheral space after previous update.
*/
if (size_mb > (SDRAM_MAX_SIZE >> 20))
size_mb = (SDRAM_MAX_SIZE >> 20);
return (size_t)size_mb << 20;
}

2
configs/puma-rk3399_defconfig
View File

@ -75,10 +75,12 @@ CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3399=y
CONFIG_PINCTRL_ROCKCHIP_RK3399_FULL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y

10
drivers/pinctrl/Kconfig
View File

@ -238,6 +238,16 @@ config PINCTRL_ROCKCHIP_RK3399
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_ROCKCHIP_RK3399_FULL
bool "Rockchip rk3399 pin control driver (full)"
depends on PINCTRL_FULL && PINCTRL_ROCKCHIP_RK3399
help
Support full pin multiplexing control on Rockchip rk3399 SoCs.
This enables the full pinctrl driver for the RK3399.
Contrary to the non-full pinctrl driver, this will evaluate
the board DTB to get the pinctrl settings.
config PINCTRL_ROCKCHIP_RV1108
bool "Rockchip rv1108 pin control driver"
depends on DM

22
drivers/pinctrl/pinctrl-uclass.c
View File

@ -27,6 +27,28 @@ int pinctrl_decode_pin_config(const void *blob, int node)
return flags;
}
/*
* TODO: this function is temporary for v2019.01.
* It should be renamed to pinctrl_decode_pin_config(),
* the original pinctrl_decode_pin_config() function should
* be removed and all callers of the original function should
* be migrated to use the new one.
*/
int pinctrl_decode_pin_config_dm(struct udevice *dev)
{
int pinconfig = 0;
if (dev->uclass->uc_drv->id != UCLASS_PINCONFIG)
return -EINVAL;
if (dev_read_bool(dev, "bias-pull-up"))
pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_UP;
else if (dev_read_bool(dev, "bias-pull-down"))
pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_DOWN;
return pinconfig;
}
#if CONFIG_IS_ENABLED(PINCTRL_FULL)
/**
* pinctrl_config_one() - apply pinctrl settings for a single node

236
drivers/pinctrl/rockchip/pinctrl_rk3399.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* (C) 2018 Theobroma Systems Design und Consulting GmbH
*/
#include <common.h>
@ -14,11 +15,240 @@
#include <asm/arch/clock.h>
#include <dm/pinctrl.h>
#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
static const u32 RK_GRF_P_PULLUP = 1;
static const u32 RK_GRF_P_PULLDOWN = 2;
#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
struct rk3399_pinctrl_priv {
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs *pmugrf;
struct rockchip_pin_bank *banks;
};
#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
/* Location of pinctrl/pinconf registers. */
enum rk_grf_location {
RK_GRF,
RK_PMUGRF,
};
/**
* @nr_pins: number of pins in this bank
* @grf_location: location of pinctrl/pinconf registers
* @bank_num: number of the bank, to account for holes
* @iomux: array describing the 4 iomux sources of the bank
*/
struct rockchip_pin_bank {
u8 nr_pins;
enum rk_grf_location grf_location;
size_t iomux_offset;
size_t pupd_offset;
};
#define PIN_BANK(pins, grf, iomux, pupd) \
{ \
.nr_pins = pins, \
.grf_location = grf, \
.iomux_offset = iomux, \
.pupd_offset = pupd, \
}
static struct rockchip_pin_bank rk3399_pin_banks[] = {
PIN_BANK(16, RK_PMUGRF,
offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
PIN_BANK(32, RK_PMUGRF,
offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
PIN_BANK(32, RK_GRF,
offsetof(struct rk3399_grf_regs, gpio2a_iomux),
offsetof(struct rk3399_grf_regs, gpio2_p)),
PIN_BANK(32, RK_GRF,
offsetof(struct rk3399_grf_regs, gpio3a_iomux),
offsetof(struct rk3399_grf_regs, gpio3_p)),
PIN_BANK(32, RK_GRF,
offsetof(struct rk3399_grf_regs, gpio4a_iomux),
offsetof(struct rk3399_grf_regs, gpio4_p)),
};
static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
u32 *shift, u32 *mask)
{
/*
* In general we four subsequent 32-bit configuration registers
* per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
* The configuration for each pin has two bits.
*
* @base...contains the address to the first register.
* @index...defines the pin within the bank (0..31).
* @addr...will be the address of the actual register to use
* @shift...will be the bit position in the configuration register
* @mask...will be the (unshifted) mask
*/
const u32 pins_per_register = 8;
const u32 config_bits_per_pin = 2;
/* Get the address of the configuration register. */
*addr = base + (index / pins_per_register) * sizeof(u32);
/* Get the bit offset within the configuration register. */
*shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
/* Get the (unshifted) mask for the configuration pins. */
*mask = ((1 << config_bits_per_pin) - 1);
pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
__func__, *addr, *mask, *shift);
}
static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
struct rockchip_pin_bank *bank,
u32 index, u32 muxval)
{
uintptr_t iomux_base, addr;
u32 shift, mask;
iomux_base = grf_addr + bank->iomux_offset;
rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask);
/* Set pinmux register */
rk_clrsetreg(addr, mask << shift, muxval << shift);
}
static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr,
struct rockchip_pin_bank *bank,
u32 index, int pinconfig)
{
uintptr_t pupd_base, addr;
u32 shift, mask, pupdval;
/* Fast path in case there's nothing to do. */
if (!pinconfig)
return;
if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP))
pupdval = RK_GRF_P_PULLUP;
else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
pupdval = RK_GRF_P_PULLDOWN;
else
/* Flag not supported. */
pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__,
pinconfig);
return;
pupd_base = grf_addr + (uintptr_t)bank->pupd_offset;
rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask);
/* Set pull-up/pull-down regisrer */
rk_clrsetreg(addr, mask << shift, pupdval << shift);
}
static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index,
u32 muxval, int pinconfig)
{
struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
struct rockchip_pin_bank *bank = &priv->banks[banknum];
uintptr_t grf_addr;
pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval,
pinconfig);
if (bank->grf_location == RK_GRF)
grf_addr = (uintptr_t)priv->grf;
else if (bank->grf_location == RK_PMUGRF)
grf_addr = (uintptr_t)priv->pmugrf;
else
return -EINVAL;
rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval);
rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig);
return 0;
}
static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
/*
* The order of the fields in this struct must match the order of
* the fields in the "rockchip,pins" property.
*/
struct rk_pin {
u32 banknum;
u32 index;
u32 muxval;
u32 phandle;
} __packed;
u32 *fields = NULL;
const int fields_per_pin = 4;
int num_fields, num_pins;
int ret;
int size;
int i;
struct rk_pin *pin;
pr_debug("%s: %s\n", __func__, config->name);
size = dev_read_size(config, "rockchip,pins");
if (size < 0)
return -EINVAL;
num_fields = size / sizeof(u32);
num_pins = num_fields / fields_per_pin;
if (num_fields * sizeof(u32) != size ||
num_pins * fields_per_pin != num_fields) {
pr_warn("Invalid number of rockchip,pins fields.\n");
return -EINVAL;
}
fields = calloc(num_fields, sizeof(u32));
if (!fields)
return -ENOMEM;
ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields);
if (ret) {
pr_warn("%s: Failed to read rockchip,pins fields.\n",
config->name);
goto end;
}
pin = (struct rk_pin *)fields;
for (i = 0; i < num_pins; i++, pin++) {
struct udevice *dev_pinconfig;
int pinconfig;
ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG,
pin->phandle,
&dev_pinconfig);
if (ret) {
pr_debug("Could not get pinconfig device\n");
goto end;
}
pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig);
if (pinconfig < 0) {
pr_warn("Could not parse pinconfig\n");
goto end;
}
ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index,
pin->muxval, pinconfig);
if (ret) {
pr_warn("Could not set pinctrl settings\n");
goto end;
}
}
end:
free(fields);
return ret;
}
#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
{
@ -468,6 +698,9 @@ static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
}
static struct pinctrl_ops rk3399_pinctrl_ops = {
#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
.set_state = rk3399_pinctrl_set_state,
#endif
.set_state_simple = rk3399_pinctrl_set_state_simple,
.request = rk3399_pinctrl_request,
.get_periph_id = rk3399_pinctrl_get_periph_id,
@ -481,6 +714,9 @@ static int rk3399_pinctrl_probe(struct udevice *dev)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
priv->banks = rk3399_pin_banks;
#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
return ret;
}

7
drivers/power/regulator/Kconfig
View File

@ -61,6 +61,13 @@ config REGULATOR_PWM
This driver is controlled by a device tree node
which includes voltage limits.
config SPL_REGULATOR_PWM
bool "Enable Driver for PWM regulators in SPL"
depends on REGULATOR_PWM
help
This config enables implementation of driver-model regulator uclass
features for PWM regulators in SPL.
config DM_REGULATOR_MAX77686
bool "Enable Driver Model for REGULATOR MAX77686"
depends on DM_REGULATOR && DM_PMIC_MAX77686

2
drivers/power/regulator/Makefile
View File

@ -9,7 +9,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o

2
drivers/ram/rockchip/sdram_rk3128.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/

2
drivers/ram/rockchip/sdram_rk3188.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2015 Google, Inc
* Copyright 2014 Rockchip Inc.

2
drivers/ram/rockchip/sdram_rk322x.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/

2
drivers/ram/rockchip/sdram_rk3288.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2015 Google, Inc
* Copyright 2014 Rockchip Inc.

2
drivers/ram/rockchip/sdram_rk3328.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/

2
drivers/ram/rockchip/sdram_rk3399.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2016-2017 Rockchip Inc.
*

12
include/dm/pinctrl.h
View File

@ -354,6 +354,18 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
*/
int pinctrl_decode_pin_config(const void *blob, int node);
/**
* pinctrl_decode_pin_config_dm() - decode pin configuration flags
*
* This decodes some of the PIN_CONFIG values into flags, with each value
* being (1 << pin_cfg). This does not support things with values like the
* slew rate.
*
* @pinconfig: Pinconfig udevice
* @return decoded flag value, or -ve on error
*/
int pinctrl_decode_pin_config_dm(struct udevice *dev);
/**
* pinctrl_get_gpio_mux() - get the mux value for a particular GPIO
*