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ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1

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The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits

and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.

So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2019-07-16 17:27:20 +05:30 committed by Kever Yang
parent 66912baa0f
commit 740409804e
1 changed files with 12 additions and 2 deletions
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14
drivers/ram/rockchip/sdram_rk3399.c
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@ -1225,8 +1225,18 @@ static void dram_all_config(struct dram_info *dram,
writel(noc_timing->ddrmode.d32,
&ddr_msch_regs->ddrmode);
/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
if (params->ch[channel].cap_info.rank == 1)
/**
* rank 1 memory clock disable (dfi_dram_clk_disable = 1)
*
* The hardware for LPDDR4 with
* - CLK0P/N connect to lower 16-bits
* - CLK1P/N connect to higher 16-bits
*
* dfi dram clk is configured via CLK1P/N, so disabling
* dfi dram clk will disable the CLK1P/N as well for lpddr4.
*/
if (params->ch[channel].cap_info.rank == 1 &&
params->base.dramtype != LPDDR4)
setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1 << 17);
}