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Prepare v2021.07-rc5 

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Merge tag 'v2021.07-rc5' into 2021.07+fslc

Prepare v2021.07-rc5

Conflicts (manual resolve):
- configs/imx8mm_evk_defconfig:
- configs/imx8mn_ddr4_evk_defconfig:
- configs/imx8mn_evk_defconfig:
- configs/imx8mp_evk_defconfig:
Drop our local change, which are incuded in the commit 2bba78076b
("configs: Resync with savedefconfig") from upstream.

- configs/mx6sabresd_defconfig:
Merge changes from commit 2f7d3890b6 ("mx6sabre_common: Dynamically
change the video output") with upstream commit 2bba78076b ("configs:
Resync with savedefconfig").

Link: https://lore.kernel.org/u-boot/20210628194137.GU9516@bill-the-cat/
Signed-off-by: Andrey Zhizhikin <andrey.z@gmail.com>
This commit is contained in:
Andrey Zhizhikin 2021-06-29 14:03:31 +00:00
parent c10bedd96f 3ef4572110
commit 73fb2c32f7
1244 changed files with 10250 additions and 2793 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.azure-pipelines.yml
View File

@ -16,7 +16,7 @@ jobs:
vmImage: $(windows_vm)
steps:
- powershell: |
(New-Object Net.WebClient).DownloadFile("https://github.com/msys2/msys2-installer/releases/download/2020-07-20/msys2-base-x86_64-20200720.sfx.exe", "sfx.exe")
(New-Object Net.WebClient).DownloadFile("https://github.com/msys2/msys2-installer/releases/download/2021-06-04/msys2-base-x86_64-20210604.sfx.exe", "sfx.exe")
displayName: 'Install MSYS2'
- script: |
sfx.exe -y -o%CD:~0,2%\

21
MAINTAINERS
View File

@ -882,6 +882,7 @@ F: arch/mips/dts/mrvl,cn73xx.dtsi
MMC
M: Peng Fan <peng.fan@nxp.com>
M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
F: drivers/mmc/
@ -913,12 +914,32 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-nios.git
F: arch/nios2/
NVMe
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
F: drivers/nvme/
F: cmd/nvme.c
F: include/nvme.h
F: doc/develop/driver-model/nvme.rst
ONENAND
#M: Lukasz Majewski <l.majewski@majess.pl>
S: Orphaned (Since 2017-01)
T: git https://source.denx.de/u-boot/custodians/u-boot-onenand.git
F: drivers/mtd/onenand/
OUT4-IMX6ULL-NANO BOARD
M: Oleh Kravchenko <oleg@kaa.org.ua>
S: Maintained
T: git https://github.com/Oleh-Kravchenko/u-boot-out4.git
F: arch/arm/dts/ev-imx280-nano-x-mb.dts
F: arch/arm/dts/o4-imx-nano.dts
F: arch/arm/dts/o4-imx6ull-nano.dtsi
F: board/out4
F: configs/ev-imx280-nano-x-mb_defconfig
F: configs/o4-imx6ull-nano_defconfig
F: include/configs/o4-imx6ull-nano.h
PATMAN
M: Simon Glass <sjg@chromium.org>
S: Maintained

4
Makefile
View File

@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION = -rc4
EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*
@ -2279,7 +2279,7 @@ endif
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
quiet_cmd_genenv = GENENV $@
quiet_cmd_genenv = GENENV $@
cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \
sed --in-place -e 's/\x00/\x0A/g' $@

2
arch/arc/include/asm/global_data.h
View File

@ -6,8 +6,6 @@
#ifndef __ASM_ARC_GLOBAL_DATA_H
#define __ASM_ARC_GLOBAL_DATA_H
#include <config.h>
#ifndef __ASSEMBLY__
/* Architecture-specific global data */
struct arch_global_data {

19
arch/arm/Kconfig
View File

@ -1491,6 +1491,24 @@ config TARGET_PG_WCOM_SELI8
SELI8 is a QorIQ LS1021a based service unit card used
in XMC20 and FOX615 product families.
config TARGET_PG_WCOM_EXPU1
bool "Support Hitachi-Powergrids EXPU1 service unit card"
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
select VENDOR_KM
imply SCSI
help
Support for Hitachi-Powergrids EXPU1 service unit card.
EXPU1 is a QorIQ LS1021a based service unit card used
in XMC20 and FOX615 product families.
config TARGET_LS1021ATSN
bool "Support ls1021atsn"
select ARCH_LS1021A
@ -2008,6 +2026,7 @@ source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"

12
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -223,7 +223,9 @@ config ARCH_LX2162A
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106
select SYS_FSL_ERRATUM_A050204
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508
@ -253,7 +255,9 @@ config ARCH_LX2160A
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106
select SYS_FSL_ERRATUM_A050204
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508
@ -371,8 +375,8 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A050106
bool "Workaround for USB PHY erratum A050106"
config SYS_FSL_ERRATUM_A050204
bool "Workaround for USB PHY erratum A050204"
help
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar

2
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1063,7 +1063,7 @@ int cpu_eth_init(struct bd_info *bis)
return error;
}
static inline int check_psci(void)
int check_psci(void)
{
unsigned int psci_ver;

1
arch/arm/cpu/armv8/fsl-layerscape/cpu.h
View File

@ -6,3 +6,4 @@
int fsl_qoriq_core_to_cluster(unsigned int core);
u32 initiator_type(u32 cluster, int init_id);
u32 cpu_mask(void);
int check_psci(void);

150
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
#include <common.h>
@ -478,6 +478,151 @@ static bool crypto_is_disabled(unsigned int svr)
return false;
}
#ifdef CONFIG_FSL_PFE
void pfe_set_firmware_in_fdt(void *blob, int pfenode, void *pfw, char *pename,
unsigned int len)
{
int rc, fwnode;
unsigned int phandle;
char subnode_str[32], prop_str[32], phandle_str[32], s[64];
sprintf(subnode_str, "pfe-%s-firmware", pename);
sprintf(prop_str, "fsl,pfe-%s-firmware", pename);
sprintf(phandle_str, "fsl,%s-firmware", pename);
/*Add PE FW to fdt.*/
/* Increase the size of the fdt to make room for the node. */
rc = fdt_increase_size(blob, len);
if (rc < 0) {
printf("Unable to make room for %s firmware: %s\n", pename,
fdt_strerror(rc));
return;
}
/* Create the firmware node. */
fwnode = fdt_add_subnode(blob, pfenode, subnode_str);
if (fwnode < 0) {
fdt_get_path(blob, pfenode, s, sizeof(s));
printf("Could not add firmware node to %s: %s\n", s,
fdt_strerror(fwnode));
return;
}
rc = fdt_setprop_string(blob, fwnode, "compatible", prop_str);
if (rc < 0) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add compatible property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
rc = fdt_setprop_u32(blob, fwnode, "length", len);
if (rc < 0) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add compatible property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
/*create phandle and set the property*/
phandle = fdt_create_phandle(blob, fwnode);
if (!phandle) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add phandle property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
rc = fdt_setprop(blob, fwnode, phandle_str, pfw, len);
if (rc < 0) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add firmware property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
}
void fdt_fixup_pfe_firmware(void *blob)
{
int pfenode;
unsigned int len_class = 0, len_tmu = 0, len_util = 0;
const char *p;
void *pclassfw, *ptmufw, *putilfw;
/* The first PFE we find, will contain the actual firmware. */
pfenode = fdt_node_offset_by_compatible(blob, -1, "fsl,pfe");
if (pfenode < 0)
/* Exit silently if there are no PFE devices */
return;
/* If we already have a firmware node, then also exit silently. */
if (fdt_node_offset_by_compatible(blob, -1,
"fsl,pfe-class-firmware") > 0)
return;
/* If the environment variable is not set, then exit silently */
p = env_get("class_elf_firmware");
if (!p)
return;
pclassfw = (void *)simple_strtoul(p, NULL, 16);
if (!pclassfw)
return;
p = env_get("class_elf_size");
if (!p)
return;
len_class = simple_strtoul(p, NULL, 16);
/* If the environment variable is not set, then exit silently */
p = env_get("tmu_elf_firmware");
if (!p)
return;
ptmufw = (void *)simple_strtoul(p, NULL, 16);
if (!ptmufw)
return;
p = env_get("tmu_elf_size");
if (!p)
return;
len_tmu = simple_strtoul(p, NULL, 16);
if (len_class == 0 || len_tmu == 0) {
printf("PFE FW corrupted. CLASS FW size %d, TMU FW size %d\n",
len_class, len_tmu);
return;
}
/*Add CLASS FW to fdt.*/
pfe_set_firmware_in_fdt(blob, pfenode, pclassfw, "class", len_class);
/*Add TMU FW to fdt.*/
pfe_set_firmware_in_fdt(blob, pfenode, ptmufw, "tmu", len_tmu);
/* Util PE firmware is handled separately as it is not a usual case*/
p = env_get("util_elf_firmware");
if (!p)
return;
putilfw = (void *)simple_strtoul(p, NULL, 16);
if (!putilfw)
return;
p = env_get("util_elf_size");
if (!p)
return;
len_util = simple_strtoul(p, NULL, 16);
if (len_util) {
printf("PFE Util PE firmware is not added to FDT.\n");
return;
}
pfe_set_firmware_in_fdt(blob, pfenode, putilfw, "util", len_util);
}
#endif
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@ -534,6 +679,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
#ifdef CONFIG_FSL_PFE
fdt_fixup_pfe_firmware(blob);
#endif
#ifndef CONFIG_ARCH_LS1012A
fsl_fdt_disable_usb(blob);
#endif

51
arch/arm/cpu/armv8/fsl-layerscape/mp.c
View File

@ -10,10 +10,12 @@
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/arch/mp.h>
#include <asm/arch/soc.h>
#include <linux/delay.h>
#include <linux/psci.h>
#include "cpu.h"
#include <asm/arch-fsl-layerscape/soc.h>
#include <efi_loader.h>
@ -301,24 +303,41 @@ int cpu_release(u32 nr, int argc, char *const argv[])
u64 *table = get_spin_tbl_addr();
int pos;
pos = core_to_pos(nr);
if (pos <= 0)
return -1;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
boot_addr = simple_strtoull(argv[0], NULL, 16);
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
/*
* The secondary CPUs polling the spin-table above for a non-zero
* value. To save power "wfe" is called. Thus call "sev" here to
* wake the CPUs and let them check the spin-table again (see
* slave_cpu loop in lowlevel.S)
*/
asm volatile("sev");
if (check_psci()) {
/* SPIN Table is used */
pos = core_to_pos(nr);
if (pos <= 0)
return -1;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
/*
* The secondary CPUs polling the spin-table above for a non-zero
* value. To save power "wfe" is called. Thus call "sev" here to
* wake the CPUs and let them check the spin-table again (see
* slave_cpu loop in lowlevel.S)
*/
asm volatile("sev");
} else {
/* Use PSCI to kick the core */
struct pt_regs regs;
printf("begin to kick cpu core #%d to address %llx\n",
nr, boot_addr);
regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
regs.regs[1] = nr;
regs.regs[2] = boot_addr;
regs.regs[3] = 0;
smc_call(&regs);
if (regs.regs[0])
return -1;
}
return 0;
}

6
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#include <common.h>
@ -218,7 +218,7 @@ static void erratum_a009007(void)
}
#if defined(CONFIG_FSL_LSCH3)
static void erratum_a050106(void)
static void erratum_a050204(void)
{
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009798();
erratum_a008997();
erratum_a009007();
erratum_a050106();
erratum_a050204();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.

13
arch/arm/dts/Makefile
View File

@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-qds-42-x.dtb \
@ -810,6 +811,7 @@ dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-seeed-npi-imx6ull-dev-board.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ull-somlabs-visionsom.dtb \
@ -819,6 +821,12 @@ dtb-$(CONFIG_ARCH_MX6) += \
imx6-apalis.dtb \
imx6-colibri.dtb
dtb-$(CONFIG_O4_IMX_NANO) += \
o4-imx-nano.dtb
dtb-$(CONFIG_EV_IMX280_NANO_X_MB) += \
ev-imx280-nano-x-mb.dtb
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
imx7-cm.dtb \
@ -827,8 +835,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7s-warp.dtb \
imx7d-meerkat96.dtb \
imx7d-pico-pi.dtb \
imx7d-pico-hobbit.dtb
imx7d-pico-hobbit.dtb \
imx7d-smegw01.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
imx7ulp-evk.dtb
@ -836,6 +844,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
imx8qm-cgtqmx8.dtb \
imx8qm-rom7720-a1.dtb \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \

55
arch/arm/dts/armada-3720-turris-mox.dts
View File

@ -11,6 +11,8 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "armada-372x.dtsi"
/ {
@ -34,6 +36,28 @@
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
led {
gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_ACTIVITY;
};
};
gpio-keys {
compatible = "gpio-keys";
reset {
compatible = "gpio-keys";
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
reg_usb3_vbus: usb3_vbus@0 {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
@ -140,6 +164,37 @@
reg = <0>;
spi-max-frequency = <20000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "secure-firmware";
reg = <0x0 0x20000>;
};
partition@20000 {
label = "a53-firmware";
reg = <0x20000 0x160000>;
};
partition@180000 {
label = "u-boot-env";
reg = <0x180000 0x10000>;
};
partition@190000 {
label = "Rescue system";
reg = <0x190000 0x660000>;
};
partition@7f0000 {
label = "dtb";
reg = <0x7f0000 0x10000>;
};
};
};
moxtet@1 {

109
arch/arm/dts/ev-imx280-nano-x-mb.dts Normal file
View File

@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
/dts-v1/;
#include "o4-imx6ull-nano.dtsi"
/ {
model = "EV-iMX280-NANO-X-MB";
compatible = "evodbg,ev-imx280-nano-x-mb",
"out4,o4-imx6ull-nano",
"fsl,imx6ull";
aliases {
mmc1 = &usdhc1;
};
chosen {
stdout-path = &uart1;
};
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
>;
};
pinctrl_mdio: mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
};
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&usdhc1 {
bus-width = <4>;
no-1-8-v;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-names = "default";
status = "okay";
wakeup-source;
};
&fec1 {
phy-handle = <&phy0>;
phy-mode = "rmii";
phy-reset-duration = <250>;
phy-reset-post-delay = <100>;
phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_fec1 &pinctrl_mdio>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_phy0_irq>;
pinctrl-names = "default";
reg = <0>;
};
};
};
&usbotg1 {
dr_mode = "otg";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
pinctrl-names = "default";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};

3
arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
View File

@ -41,8 +41,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddh>;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";

3
arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
View File

@ -32,8 +32,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddh>;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";

12
arch/arm/dts/fsl-ls1028a-rdb.dts
View File

@ -15,12 +15,12 @@
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
spi0 = &fspi;
eth0 = &enetc0;
eth1 = &enetc2;
eth2 = &mscc_felix_port0;
eth3 = &mscc_felix_port1;
eth4 = &mscc_felix_port2;
eth5 = &mscc_felix_port3;
ethernet0 = &enetc0;
ethernet1 = &enetc2;
ethernet2 = &mscc_felix_port0;
ethernet3 = &mscc_felix_port1;
ethernet4 = &mscc_felix_port2;
ethernet5 = &mscc_felix_port3;
};
};

8
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
View File

@ -5,7 +5,7 @@
* Some assumptions are made:
* * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -56,3 +56,9 @@
reg = <0x3>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

8
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
View File

@ -6,7 +6,7 @@
* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
* * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -59,3 +59,9 @@
reg = <0x1>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

8
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
View File

@ -6,7 +6,7 @@
* * Mezzanine card M8 is connected to IO SLOT1
* (xlaui4 for DPMAC 1)
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -24,3 +24,9 @@
reg = <0x0>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

8
arch/arm/dts/fsl-lx2162a-qds.dts
View File

@ -2,7 +2,7 @@
/*
* NXP LX2162AQDS device tree source
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -135,3 +135,9 @@
reg = <2>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

2
arch/arm/dts/imx6qdl-gw51xx.dtsi
View File

@ -129,6 +129,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

2
arch/arm/dts/imx6qdl-gw52xx.dtsi
View File

@ -195,6 +195,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw53xx.dtsi
View File

@ -188,6 +188,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};
@ -597,6 +599,7 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};

3
arch/arm/dts/imx6qdl-gw54xx.dtsi
View File

@ -225,6 +225,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};
@ -675,6 +677,7 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};

2
arch/arm/dts/imx6qdl-gw560x.dtsi
View File

@ -279,6 +279,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw5903.dtsi
View File

@ -223,6 +223,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw5904.dtsi
View File

@ -200,6 +200,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
fixed-link {

2
arch/arm/dts/imx6qdl-gw5907.dtsi
View File

@ -131,6 +131,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw5910.dtsi
View File

@ -146,6 +146,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

4
arch/arm/dts/imx6qdl-gw5912.dtsi
View File

@ -141,6 +141,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};
@ -426,6 +429,7 @@
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};

3
arch/arm/dts/imx6qdl-gw5913.dtsi
View File

@ -121,6 +121,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

19
arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Linumiz
* Author: Navin Sankar Velliangiri <navin@linumiz.com>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-seeed-npi-imx6ull.dtsi"
#include "imx6ull-seeed-npi-imx6ull-u-boot.dtsi"
/ {
model = "Seeed NPi iMX6ULL Dev Board with NAND";
compatible = "seeed,imx6ull-seeed-npi-imx6ull", "fsl,imx6ull";
};
&gpmi {
status = "okay";
};

24
arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Linumiz
* Author: Navin Sankar Velliangiri <navin@linumiz.com>
*/
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};
&gpmi {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&usdhc1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&usdhc2 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};

271
arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi Normal file
View File

@ -0,0 +1,271 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Linumiz
* Author: Navin Sankar Velliangiri <navin@linumiz.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Seeed NPi-iMX6ULL Dev Board";
compatible = "fsl,imx6ull";
chosen {
stdout-path = &uart1;
};
leds {
compatible = "gpio-leds";
user-led {
label = "User";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
};
&uart1 {
pinctrl-name = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
non-removable;
keep-power-in-suspend;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl_uart1: uart1grp {
fsl,pin = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pin = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright (C) 2020 PHYTEC Messtechnik GmbH
// Author: Jens Lang <J.Lang@phytec.de>
// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
/dts-v1/;
#include "imx7d.dtsi"
/ {
model = "Storopack SMEGW01 board";
compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc3;
};
chosen {
stdout-path = &uart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
enable-sdio-wakeup;
keep-power-in-suspend;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
max-frequency = <200000000>;
bus-width = <8>;
fsl,tuning-step = <1>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
sd-uhs-ddr50;
sd-uhs-sdr104;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
>;
};
pinctrl_usdhc1: usdhc1 {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
pinctrl_usdhc3: usdhc3 {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
>;
};
pinctrl_usdhc3_100mhz: usdhc3_100mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
>;
};
pinctrl_usdhc3_200mhz: usdhc3_200mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
>;
};
};
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017 congatec AG
* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/memreserve/ 0x80000000 0x00020000;
#include "fsl-imx8qm.dtsi"
/ {
model = "Congatec QMX8 Qseven series";
compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
stdout-path = &lpuart0;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "sw-3p3-sd1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <3000>;
};
reg_usdhc3_vmmc: usdhc3_vmmc {
compatible = "regulator-fixed";
regulator-name = "sw-3p3-sd2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <3000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
fsl,rgmii_txc_dly;
fsl,rgmii_rxc_dly;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <6>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&gpio2 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c0>;
clock-frequency = <100000>;
status = "okay";
rtc_ext: m41t62@68 {
compatible = "st,m41t62";
reg = <0x68>;
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
clock-names = "mclk";
wlf,shared-lrclk;
/* power-domains = <&pd_mclk_out0>; */
assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <24576000>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx8qm-qmx8 {
pinctrl_hog: hoggrp{
fsl,pins = <
SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021
SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021
SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021
SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021
SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_lpi2c0: lpi2c0grp {
fsl,pins = <
SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c
SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_DMA_UART0_RX 0x06000020
SC_P_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
SC_P_UART1_RX_DMA_UART1_RX 0x06000020
SC_P_UART1_TX_DMA_UART1_TX 0x06000020
SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020
SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020
>;
};
pinctrl_mlb: mlbgrp {
fsl,pins = <
SC_P_MLB_SIG_CONN_MLB_SIG 0x21
SC_P_MLB_CLK_CONN_MLB_CLK 0x21
SC_P_MLB_DATA_CONN_MLB_DATA 0x21
>;
};
pinctrl_isl29023: isl29023grp {
fsl,pins = <
SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_usdhc3_gpio: usdhc3grpgpio {
fsl,pins = <
SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
>;
};
};
};
&lpuart0 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lpuart1 { /* Q7 connector */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&pd_dma_lpuart0 {
debug_console;
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
bus-width = <4>;
cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc3_vmmc>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "okay";
};

38
arch/arm/dts/imxrt1020-evk-u-boot.dtsi
View File

@ -8,6 +8,42 @@
chosen {
u-boot,dm-spl;
};
clocks {
u-boot,dm-spl;
};
soc {
u-boot,dm-spl;
};
};
&osc {
u-boot,dm-spl;
};
&clks {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpt1 {
u-boot,dm-spl;
};
&lpuart1 { /* console */
@ -15,6 +51,8 @@
};
&semc {
u-boot,dm-spl;
bank1: bank@0 {
u-boot,dm-spl;
};

6
arch/arm/dts/imxrt1020-evk.dts
View File

@ -16,9 +16,11 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
tick-timer = &gpt1;
};
memory {
device_type = "memory";
reg = <0x80000000 0x2000000>;
};
};
@ -186,6 +188,10 @@
};
};
&gpt1 {
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;

31
arch/arm/dts/imxrt1020.dtsi
View File

@ -23,7 +23,6 @@
};
clocks {
u-boot,dm-spl;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
@ -36,8 +35,7 @@
clock-frequency = <0>;
};
osc {
u-boot,dm-spl;
osc: osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
@ -45,10 +43,7 @@
};
soc {
u-boot,dm-spl;
semc: semc@402f0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1020_CLK_SEMC>;
@ -73,7 +68,6 @@
};
clks: ccm@400fc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
@ -82,7 +76,6 @@
};
usdhc1: usdhc@402c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c0000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
@ -95,7 +88,6 @@
};
gpio1: gpio@401b8000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
@ -107,7 +99,6 @@
};
gpio2: gpio@401bc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
@ -119,7 +110,6 @@
};
gpio3: gpio@401c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@ -129,5 +119,24 @@
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@400c0000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpt1: gpt1@401ec000 {
compatible = "fsl,imxrt-gpt";
reg = <0x401ec000 0x4000>;
interrupts = <100>;
clocks = <&osc>;
status = "disabled";
};
};
};

42
arch/arm/dts/imxrt1050-evk-u-boot.dtsi
View File

@ -8,6 +8,46 @@
chosen {
u-boot,dm-spl;
};
clocks {
u-boot,dm-spl;
};
soc {
u-boot,dm-spl;
};
};
&osc {
u-boot,dm-spl;
};
&clks {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpt1 {
u-boot,dm-spl;
};
&lpuart1 { /* console */
@ -15,6 +55,8 @@
};
&semc {
u-boot,dm-spl;
bank1: bank@0 {
u-boot,dm-spl;
};

15
arch/arm/dts/imxrt1050-evk.dts
View File

@ -16,9 +16,11 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
tick-timer = &gpt1;
};
memory {
device_type = "memory";
reg = <0x80000000 0x2000000>;
};
};
@ -187,7 +189,6 @@
};
pinctrl_lcdif: lcdifgrp {
u-boot,dm-spl;
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
@ -215,6 +216,10 @@
};
};
&gpt1 {
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
@ -232,9 +237,6 @@
display = <&display0>;
status = "okay";
assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
@ -258,3 +260,8 @@
};
};
};
&usbotg1 {
dr_mode = "host";
status = "okay";
};

57
arch/arm/dts/imxrt1050.dtsi
View File

@ -23,13 +23,11 @@
gpio4 = &gpio5;
mmc0 = &usdhc1;
serial0 = &lpuart1;
usbphy0 = &usbphy1;
};
clocks {
u-boot,dm-spl;
osc {
u-boot,dm-spl;
osc: osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
@ -37,10 +35,7 @@
};
soc {
u-boot,dm-spl;
semc: semc@402f0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1050_CLK_SEMC>;
@ -65,7 +60,6 @@
};
clks: ccm@400fc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
@ -74,7 +68,6 @@
};
usdhc1: usdhc@402c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c0000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
@ -87,7 +80,6 @@
};
gpio1: gpio@401b8000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
@ -99,7 +91,6 @@
};
gpio2: gpio@401bc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
@ -111,7 +102,6 @@
};
gpio3: gpio@401c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@ -123,7 +113,6 @@
};
gpio4: gpio@401c4000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
@ -135,7 +124,6 @@
};
gpio5: gpio@400c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
@ -150,8 +138,45 @@
compatible = "fsl,imxrt-lcdif";
reg = <0x402b8000 0x4000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_LCDIF>;
clock-names = "per";
clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
<&clks IMXRT1050_CLK_LCDIF_APB>;
clock-names = "pix", "axi";
assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
status = "disabled";
};
gpt1: gpt1@401ec000 {
compatible = "fsl,imxrt-gpt";
reg = <0x401ec000 0x4000>;
interrupts = <100>;
clocks = <&osc>;
status = "disabled";
};
usbphy1: usbphy@400d9000 {
compatible = "fsl,imxrt-usbphy";
reg = <0x400d9000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
};
usbmisc: usbmisc@402e0800 {
#index-cells = <1>;
compatible = "fsl,imxrt-usbmisc";
reg = <0x402e0800 0x200>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
};
usbotg1: usb@402e0000 {
compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
reg = <0x402e0000 0x200>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
status = "disabled";
};
};

130
arch/arm/dts/ls1021a-pg-wcom-expu1.dts Normal file
View File

@ -0,0 +1,130 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Hitachi ABB Power Grids EXPU1 board device tree source
*
* Copyright 2020 Hitachi ABB Power Grids
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include "ls1021a.dtsi"
/ {
model = "EXPU1 Service Unit for XMC and FOX";
aliases {
enet2-rgmii-debug-phy = &debug_phy;
};
chosen {
stdout-path = &uart0;
};
};
&enet0 {
status = "okay";
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet1 {
status = "okay";
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet2 {
phy-handle = <&debug_phy>;
phy-connection-type = "rgmii-id";
max-speed = <100>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&dspi1 {
bus-num = <0>;
status = "okay";
zl30343@0 {
compatible = "gen,spidev", "zarlink,zl30343";
reg = <0>;
spi-max-frequency = <8000000>;
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR Flash on board */
ranges = <0x0 0x0 0x60000000 0x04000000>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
label = "rcw";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "qe";
reg = <0x20000 0x20000>;
};
/* ZL30343 init data to be added here */
partition@40000 {
label = "envred";
reg = <0x40000 0x20000>;
};
partition@60000 {
label = "env";
reg = <0x60000 0x20000>;
};
partition@100000 {
label = "u-boot";
reg = <0x100000 0x100000>;
};
partition@200000 {
label = "ubi0";
reg = <0x200000 0x3E00000>;
};
};
};
&mdio0 {
debug_phy: ethernet-phy@11 {
reg = <0x11>;
};
tbi0: tbi-phy@0xb {
reg = <0xb>;
device_type = "tbi-phy";
};
};
&mdio1 {
tbi1: tbi-phy@0xd {
reg = <0xd>;
device_type = "tbi-phy";
};
};
&uart0 {
status = "okay";
};

8
arch/arm/dts/ls1021a.dtsi
View File

@ -100,7 +100,7 @@
gpio0: gpio@2300000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
reg = <0x2300000 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -110,7 +110,7 @@
gpio1: gpio@2310000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
reg = <0x2310000 0x10000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -120,7 +120,7 @@
gpio2: gpio@2320000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
reg = <0x2320000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -130,7 +130,7 @@
gpio3: gpio@2330000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
reg = <0x2330000 0x10000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;

235
arch/arm/dts/o4-imx-nano.dts Normal file
View File

@ -0,0 +1,235 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "o4-imx6ull-nano.dtsi"
/ {
model = "O4-iMX-NANO";
compatible = "out4,o4-imx-nano",
"out4,o4-imx6ull-nano",
"fsl,imx6ull";
aliases {
mmc1 = &usdhc1;
};
chosen {
stdout-path = &uart1;
};
leds {
compatible = "gpio-leds";
led0 {
color = <LED_COLOR_ID_RED>;
gpios = <&pcf8574a 0 GPIO_ACTIVE_LOW>;
};
led1{
color = <LED_COLOR_ID_GREEN>;
gpios = <&pcf8574a 1 GPIO_ACTIVE_LOW>;
};
led2 {
gpios = <&pcf8574a 2 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_BLUE>;
};
led3 {
color = <LED_COLOR_ID_RED>;
gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>;
};
led4{
color = <LED_COLOR_ID_GREEN>;
gpios = <&pcf8574a 4 GPIO_ACTIVE_LOW>;
};
led5 {
color = <LED_COLOR_ID_BLUE>;
gpios = <&pcf8574a 5 GPIO_ACTIVE_LOW>;
};
};
usbotg1_vbus: reg_usbotg1_vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&pcf8574a 6 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb0";
};
usbotg2_vbus: reg_usbotg2_vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&pcf8574a 7 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1";
};
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
>;
};
pinctrl_mdio: mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b8b0
MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b8b0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
>;
};
};
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&usdhc1 {
bus-width = <4>;
no-1-8-v;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-names = "default";
status = "okay";
wakeup-source;
};
&fec1 {
phy-handle = <&phy0>;
phy-mode = "rmii";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-names = "default";
status = "okay";
};
&fec2 {
phy-handle = <&phy1>;
phy-mode = "rmii";
phy-reset-duration = <250>;
phy-reset-post-delay = <100>;
phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_fec2 &pinctrl_mdio>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_phy0_irq>;
pinctrl-names = "default";
reg = <0>;
};
phy1: ethernet-phy@1 {
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
interrupt-parent = <&gpio5>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_phy1_irq>;
pinctrl-names = "default";
reg = <1>;
};
};
};
&usbotg1 {
dr_mode = "host";
status = "okay";
vbus-supply = <&usbotg1_vbus>;
};
&usbotg2 {
dr_mode = "host";
status = "okay";
vbus-supply = <&usbotg2_vbus>;
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio4 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pcf8574a: gpio@38 {
compatible = "nxp,pcf8574a";
#gpio-cells = <2>;
gpio-controller;
reg = <0x38>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&uart2 {
linux,rs485-enabled-at-boot-time;
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
status = "okay";
uart-has-rtscts;
};

87
arch/arm/dts/o4-imx6ull-nano.dtsi Normal file
View File

@ -0,0 +1,87 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
/dts-v1/;
#include "imx6ull.dtsi"
/ {
model = "O4-iMX6ULL-NANO";
compatible = "out4,o4-imx6ull-nano", "fsl,imx6ull";
aliases {
mmc0 = &usdhc2;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
};
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
>;
};
pinctrl_phy0_irq: phy0grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79
>;
};
pinctrl_phy1_irq: phy1grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
>;
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
bus-width = <8>;
status = "okay";
};

3
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -50,6 +50,8 @@
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
#define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */
#define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
@ -57,6 +59,7 @@
#define MXC_SOC_MX7 0x70
#define MXC_SOC_IMX8M 0x80
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_IMXRT 0xB0 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
#define CHIP_REV_1_0 0x10

4
arch/arm/include/asm/arch-imxrt/imx-regs.h
View File

@ -23,4 +23,8 @@
#include <asm/mach-imx/regs-lcdif.h>
#endif
#define USB_BASE_ADDR 0x402E0000
#define USB_PHY0_BASE_ADDR 0x400D9000
#define USB_PHY1_BASE_ADDR 0x400DA000
#endif /* __ASM_ARCH_IMX_REGS_H__ */

2
arch/arm/include/asm/global_data.h
View File

@ -9,6 +9,8 @@
#ifndef __ASSEMBLY__
#include <config.h>
#include <asm/types.h>
#include <linux/types.h>

4
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -31,6 +31,7 @@ struct bd_info;
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
@ -78,6 +79,9 @@ struct bd_info;
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
#ifdef CONFIG_MX6
#define IMX6_SRC_GPR10_BMODE BIT(28)
#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)

5
arch/arm/lib/crt0_64.S
View File

@ -112,6 +112,11 @@ ENTRY(_main)
ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */
sub x9, x9, x0 /* x9 <- Run-vs-link offset */
add lr, lr, x9
#if defined(CONFIG_SYS_RELOC_GD_ENV_ADDR)
ldr x0, [x18, #GD_ENV_ADDR] /* x0 <- gd->env_addr */
add x0, x0, x9
str x0, [x18, #GD_ENV_ADDR]
#endif
#endif
/* Add in link-vs-relocation offset */
ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */

7
arch/arm/mach-imx/imx8/Kconfig
View File

@ -86,6 +86,12 @@ config TARGET_IMX8QM_MEK
select BOARD_LATE_INIT
select IMX8QM
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
select BOARD_LATE_INIT
select SUPPORT_SPL
select IMX8QM
config TARGET_IMX8QM_ROM7720_A1
bool "Support i.MX8QM ROM-7720-A1"
select BOARD_LATE_INIT
@ -101,6 +107,7 @@ endchoice
source "board/freescale/imx8qm_mek/Kconfig"
source "board/freescale/imx8qxp_mek/Kconfig"
source "board/congatec/cgtqmx8/Kconfig"
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
source "board/toradex/apalis-imx8/Kconfig"
source "board/toradex/colibri-imx8x/Kconfig"

2
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View File

@ -646,7 +646,7 @@ static u32 decode_fracpll(enum clk_root_src frac_pll)
pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
break;
default:
printf("Not supported\n");
printf("Unsupported clk_root_src %d\n", frac_pll);
return 0;
}

18
arch/arm/mach-imx/imxrt/soc.c
View File

@ -8,13 +8,14 @@
#include <init.h>
#include <asm/io.h>
#include <asm/armv7_mpu.h>
#include <asm/mach-imx/sys_proto.h>
#include <linux/bitops.h>
int arch_cpu_init(void)
{
int i;
struct mpu_region_config imxrt1050_region_config[] = {
struct mpu_region_config imxrt_region_config[] = {
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_4GB },
{ PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
@ -29,9 +30,20 @@ int arch_cpu_init(void)
* the whole 4GB address space.
*/
disable_mpu();
for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
mpu_config(&imxrt1050_region_config[i]);
for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++)
mpu_config(&imxrt_region_config[i]);
enable_mpu();
return 0;
}
u32 get_cpu_rev(void)
{
#if defined(CONFIG_IMXRT1020)
return MXC_CPU_IMXRT1020 << 12;
#elif defined(CONFIG_IMXRT1050)
return MXC_CPU_IMXRT1050 << 12;
#else
#error This IMXRT SoC is not supported
#endif
}

24
arch/arm/mach-imx/mx6/Kconfig
View File

@ -453,6 +453,17 @@ config TARGET_NITROGEN6X
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
config TARGET_NPI_IMX6ULL
bool "Seeed NPI-IMX6ULL"
depends on MX6ULL
select DM
select DM_ETH
select DM_MMC
select DM_GPIO
select DM_SERIAL
select DM_THERMAL
select SUPPORT_SPL
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"
depends on MX6UL
@ -619,6 +630,18 @@ config TARGET_BRPPT2
Support
B&R BRPPT2 platform
based on Freescale's iMX6 SoC
config TARGET_O4_IMX6ULL_NANO
bool "O4-iMX6ULL-NANO"
depends on MX6ULL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
imply CMD_DM
help
Support for www.out4.ru O4-iMX6UL-NANO platform
based on Freescale's i.MX6UL/i.MX6ULL SoC.
endchoice
config SYS_SOC
@ -668,5 +691,6 @@ source "board/udoo/neo/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/BuR/brppt2/Kconfig"
source "board/out4/o4-imx6ull-nano/Kconfig"
endif

9
arch/arm/mach-imx/mx7/Kconfig
View File

@ -70,6 +70,14 @@ config TARGET_PICO_IMX7D
select SUPPORT_SPL
imply CMD_DM
config TARGET_SMEGW01
bool "smegw01"
select BOARD_LATE_INIT
select DM
select DM_THERMAL
select MX7D
imply CMD_DM
config TARGET_WARP7
bool "warp7"
select BOARD_LATE_INIT
@ -94,6 +102,7 @@ source "board/compulab/cl-som-imx7/Kconfig"
source "board/ronetix/imx7-cm/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/novtech/meerkat96/Kconfig"
source "board/storopack/smegw01/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"

3
arch/arm/mach-rmobile/Kconfig.64
View File

@ -69,16 +69,19 @@ choice
config TARGET_BEACON_RZG2H
bool "Beacon EmbeddedWorks RZ/G2H Dev Kit"
select R8A774E1
select RZ_G2
select PINCTRL_PFC_R8A774E1
config TARGET_BEACON_RZG2M
bool "Beacon EmbeddedWorks RZ/G2M Dev Kit"
select R8A774A1
select RZ_G2
select PINCTRL_PFC_R8A774A1
config TARGET_BEACON_RZG2N
bool "Beacon EmbeddedWorks RZ/G2N Dev Kit"
select R8A774B1
select RZ_G2
select PINCTRL_PFC_R8A774B1
config TARGET_CONDOR

5
arch/arm/mach-zynqmp/include/mach/hardware.h
View File

@ -19,6 +19,11 @@
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
#define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800
#define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \
+ 0x00000114)
#define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210
#define PS_MODE0 BIT(0)
#define PS_MODE1 BIT(1)
#define PS_MODE2 BIT(2)

2
arch/m68k/include/asm/global_data.h
View File

@ -7,6 +7,8 @@
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
#include <config.h>
/* Architecture-specific global data */
struct arch_global_data {
#ifdef CONFIG_SYS_I2C_FSL

2
arch/nds32/include/asm/global_data.h
View File

@ -17,6 +17,8 @@
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
#include <config.h>
/* Architecture-specific global data */
struct arch_global_data {
};

7
arch/powerpc/dts/t2080rdb.dts
View File

@ -77,10 +77,17 @@
reg = <0x0>;
};
#ifdef CONFIG_T2080RDB_REV_D
xg_aq1202_phy4: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x8>;
};
#else
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
#endif
};
};
};

2
arch/powerpc/include/asm/global_data.h
View File

@ -8,7 +8,7 @@
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
#include "config.h"
#include <config.h>
#include "asm/types.h"
/* Architecture-specific global data */

1
arch/powerpc/lib/traps.c
View File

@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>

52
arch/riscv/dts/ae350-u-boot.dtsi Normal file
View File

@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/ {
cpus {
u-boot,dm-spl;
CPU0: cpu@0 {
u-boot,dm-spl;
CPU0_intc: interrupt-controller {
u-boot,dm-spl;
};
};
CPU1: cpu@1 {
u-boot,dm-spl;
CPU1_intc: interrupt-controller {
u-boot,dm-spl;
};
};
CPU2: cpu@2 {
u-boot,dm-spl;
CPU2_intc: interrupt-controller {
u-boot,dm-spl;
};
};
CPU3: cpu@3 {
u-boot,dm-spl;
CPU3_intc: interrupt-controller {
u-boot,dm-spl;
};
};
};
memory@0 {
u-boot,dm-spl;
};
soc {
u-boot,dm-spl;
plic1: interrupt-controller@e6400000 {
u-boot,dm-spl;
};
plmt0@e6000000 {
u-boot,dm-spl;
};
};
serial0: serial@f0300000 {
u-boot,dm-spl;
};
};

9
arch/riscv/dts/ae350_32.dts
View File

@ -1,6 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
#address-cells = <1>;
@ -14,7 +17,7 @@
};
chosen {
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
stdout-path = "uart0:38400n8";
};
@ -133,8 +136,7 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
#address-cells = <1>;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xe4000000 0x2000000>;
riscv,ndev=<71>;
@ -146,7 +148,6 @@
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
#address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe6400000 0x400000>;

7
arch/riscv/dts/ae350_64.dts
View File

@ -1,6 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
#address-cells = <2>;
@ -14,7 +17,7 @@
};
chosen {
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
bootargs = "console=ttyS0,38400n8 debug loglevel=7";
stdout-path = "uart0:38400n8";
};
@ -133,7 +136,6 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe4000000 0x0 0x2000000>;
@ -146,7 +148,6 @@
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;

4
arch/riscv/lib/andes_plic.c
View File

@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending)
{
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
*pending = !!(*pending & SEND_IPI_TO_HART(hart));
*pending = !!(*pending & ipi);
return 0;
}

10
arch/sandbox/dts/test.dts
View File

@ -14,11 +14,11 @@
aliases {
console = &uart0;
eth0 = "/eth@10002000";
eth2 = &swp_0;
eth3 = &eth_3;
eth4 = &dsa_eth0;
eth5 = &eth_5;
ethernet0 = "/eth@10002000";
ethernet2 = &swp_0;
ethernet3 = &eth_3;
ethernet4 = &dsa_eth0;
ethernet5 = &eth_5;
gpio1 = &gpio_a;
gpio2 = &gpio_b;
gpio3 = &gpio_c;

1
arch/x86/cpu/u-boot-64.lds
View File

@ -107,4 +107,5 @@ SECTIONS
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.note.gnu.property) }
}

1
arch/x86/cpu/u-boot-spl.lds
View File

@ -82,6 +82,7 @@ SECTIONS
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.note.gnu.property) }
#if defined(CONFIG_SPL_X86_16BIT_INIT) || defined(CONFIG_TPL_X86_16BIT_INIT)
/*

1
arch/x86/cpu/u-boot.lds
View File

@ -105,6 +105,7 @@ SECTIONS
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.note.gnu.property) }
#ifdef CONFIG_X86_16BIT_INIT
/*

114
board/CZ.NIC/turris_mox/turris_mox.c
View File

@ -10,11 +10,13 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <button.h>
#include <clk.h>
#include <dm.h>
#include <env.h>
#include <fdt_support.h>
#include <init.h>
#include <led.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <linux/string.h>
@ -44,6 +46,8 @@
#define SFP_GPIO_PATH "/soc/internal-regs@d0000000/spi@10600/moxtet@1/gpio@0"
#define PCIE_PATH "/soc/pcie@d0070000"
#define SFP_PATH "/sfp"
#define LED_PATH "/leds/led"
#define BUTTON_PATH "/gpio-keys/reset"
DECLARE_GLOBAL_DATA_PTR;
@ -373,6 +377,114 @@ int misc_init_r(void)
return 0;
}
static void mox_phy_modify(struct phy_device *phydev, int page, int reg,
u16 mask, u16 set)
{
int val;
val = phydev->drv->readext(phydev, MDIO_DEVAD_NONE, page, reg);
val &= ~mask;
val |= set;
phydev->drv->writeext(phydev, MDIO_DEVAD_NONE, page, reg, val);
}
static void mox_phy_leds_start_blinking(void)
{
struct phy_device *phydev;
struct mii_dev *bus;
bus = miiphy_get_dev_by_name("neta@30000");
if (!bus) {
printf("Cannot get MDIO bus device!\n");
return;
}
phydev = phy_find_by_mask(bus, BIT(1), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
printf("Cannot get ethernet PHY!\n");
return;
}
mox_phy_modify(phydev, 3, 0x12, 0x700, 0x400);
mox_phy_modify(phydev, 3, 0x10, 0xff, 0xbb);
}
static bool read_reset_button(void)
{
struct udevice *button, *led;
int i;
if (device_get_global_by_ofnode(ofnode_path(BUTTON_PATH), &button)) {
printf("Cannot find reset button!\n");
return false;
}
if (device_get_global_by_ofnode(ofnode_path(LED_PATH), &led)) {
printf("Cannot find status LED!\n");
return false;
}
led_set_state(led, LEDST_ON);
for (i = 0; i < 21; ++i) {
if (button_get_state(button) != BUTTON_ON)
return false;
if (i < 20)
mdelay(50);
}
led_set_state(led, LEDST_OFF);
return true;
}
static void handle_reset_button(void)
{
const char * const vars[1] = { "bootcmd_rescue", };
/*
* Ensure that bootcmd_rescue has always stock value, so that running
* run bootcmd_rescue
* always works correctly.
*/
env_set_default_vars(1, (char * const *)vars, 0);
if (read_reset_button()) {
const char * const vars[2] = {
"bootcmd",
"distro_bootcmd",
};
/*
* Set the above envs to their default values, in case the user
* managed to break them.
*/
env_set_default_vars(2, (char * const *)vars, 0);
/* Ensure bootcmd_rescue is used by distroboot */
env_set("boot_targets", "rescue");
/* start blinking PHY LEDs */
mox_phy_leds_start_blinking();
printf("RESET button was pressed, overwriting boot_targets!\n");
} else {
/*
* In case the user somehow managed to save environment with
* boot_targets=rescue, reset boot_targets to default value.
* This could happen in subsequent commands if bootcmd_rescue
* failed.
*/
if (!strcmp(env_get("boot_targets"), "rescue")) {
const char * const vars[1] = {
"boot_targets",
};
env_set_default_vars(1, (char * const *)vars, 0);
}
}
}
static void mox_print_info(void)
{
int ret, board_version, ram_size;
@ -543,6 +655,8 @@ int last_stage_init(void)
printf("\n");
handle_reset_button();
return 0;
}

13
board/CZ.NIC/turris_omnia/turris_omnia.c
View File

@ -339,9 +339,17 @@ static int set_regdomain(void)
static void handle_reset_button(void)
{
const char * const vars[1] = { "bootcmd_rescue", };
int ret;
u8 reset_status;
/*
* Ensure that bootcmd_rescue has always stock value, so that running
* run bootcmd_rescue
* always works correctly.
*/
env_set_default_vars(1, (char * const *)vars, 0);
ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
if (ret) {
printf("omnia_mcu_read failed: %i, reset status unknown!\n",
@ -352,9 +360,8 @@ static void handle_reset_button(void)
env_set_ulong("omnia_reset", reset_status);
if (reset_status) {
const char * const vars[3] = {
const char * const vars[2] = {
"bootcmd",
"bootcmd_rescue",
"distro_bootcmd",
};
@ -362,7 +369,7 @@ static void handle_reset_button(void)
* Set the above envs to their default values, in case the user
* managed to break them.
*/
env_set_default_vars(3, (char * const *)vars, 0);
env_set_default_vars(2, (char * const *)vars, 0);
/* Ensure bootcmd_rescue is used by distroboot */
env_set("boot_targets", "rescue");

14
board/congatec/cgtqmx8/Kconfig Normal file
View File

@ -0,0 +1,14 @@
if TARGET_CONGA_QMX8
config SYS_BOARD
default "cgtqmx8"
config SYS_VENDOR
default "congatec"
config SYS_CONFIG_NAME
default "cgtqmx8"
source "board/congatec/common/Kconfig"
endif

7
board/congatec/cgtqmx8/MAINTAINERS Normal file
View File

@ -0,0 +1,7 @@
i.MX8QM CGTQMX8 BOARD
M: Oliver Graute <oliver.graute@kococonnector.com>
S: Maintained
F: board/congatec/cgtqmx8/
F: arch/arm/dts/imx8qm-cgtqmx8.dts
F: include/configs/cgtqmx8.h
F: configs/cgtqmx8_defconfig

11
board/congatec/cgtqmx8/Makefile Normal file
View File

@ -0,0 +1,11 @@
#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cgtqmx8.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif

460
board/congatec/cgtqmx8/cgtqmx8.c Normal file
View File

@ -0,0 +1,460 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 congatec AG
* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
*/
#include <common.h>
#include <errno.h>
#include <linux/libfdt.h>
#include <fsl_esdhc.h>
#include <init.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <usb.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <linux/delay.h>
#include <power-domain.h>
DECLARE_GLOBAL_DATA_PTR;
#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
static iomux_cfg_t uart0_pads[] = {
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
void board_late_mmc_env_init(void);
void init_clk_usdhc(u32 index);
int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
static void setup_iomux_uart(void)
{
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
}
int board_early_init_f(void)
{
/* sc_ipc_t ipcHndl = 0; */
sc_err_t scierr = 0;
/* When start u-boot in XEN VM, directly return */
/* if (IS_ENABLED(CONFIG_XEN)) */
/* return 0; */
/* ipcHndl = gd->arch.ipc_channel_handle; */
/* Power up UART0, this is very early while power domain is not working */
scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
if (scierr != SC_ERR_NONE)
return 0;
/* Set UART0 clock root to 80 MHz */
sc_pm_clock_rate_t rate = 80000000;
scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
if (scierr != SC_ERR_NONE)
return 0;
/* Enable UART0 clock root */
scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
if (scierr != SC_ERR_NONE)
return 0;
setup_iomux_uart();
return 0;
}
#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX)
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
};
static iomux_cfg_t emmc0[] = {
SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
static iomux_cfg_t usdhc1_sd[] = {
SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
static iomux_cfg_t usdhc2_sd[] = {
SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
struct power_domain pd;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 (onboard eMMC) USDHC1
* mmc1 (external SD card) USDHC2
* mmc2 (onboard µSD) USDHC3
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
/* onboard eMMC */
if (!imx8_power_domain_lookup_name("conn_sdhc0", &pd))
power_domain_on(&pd);
imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
init_clk_usdhc(0);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
/* external SD card */
if (!imx8_power_domain_lookup_name("conn_sdhc1", &pd))
power_domain_on(&pd);
imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
init_clk_usdhc(1);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gpio_request(USDHC1_CD_GPIO, "sd1_cd");
gpio_direction_input(USDHC1_CD_GPIO);
break;
case 2:
/* onboard µSD */
if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd))
power_domain_on(&pd);
imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
init_clk_usdhc(2);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
gpio_request(USDHC2_CD_GPIO, "sd2_cd");
gpio_direction_input(USDHC2_CD_GPIO);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
}
return ret;
}
#endif /* CONFIG_FSL_ESDHC_IMX */
#if (IS_ENABLED(CONFIG_FEC_MXC))
#include <miiphy.h>
static iomux_cfg_t pad_enet0[] = {
SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
}
static void enet_device_phy_reset(void)
{
gpio_set_value(FEC0_RESET, 0);
udelay(50);
gpio_set_value(FEC0_RESET, 1);
/* The board has a long delay for this reset to become stable */
mdelay(200);
}
int board_eth_init(struct bd_info *bis)
{
setup_iomux_fec();
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
static int setup_fec(void)
{
/* Reset ENET PHY */
enet_device_phy_reset();
return 0;
}
#endif
#ifdef CONFIG_MXC_GPIO
#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
#define BKL_ENABLE IMX_GPIO_NR(1, 7)
static iomux_cfg_t board_gpios[] = {
SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};
static void board_gpio_init(void)
{
imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
/* enable LVDS */
gpio_request(LVDS_ENABLE, "lvds_enable");
gpio_direction_output(LVDS_ENABLE, 1);
/* enable backlight */
gpio_request(BKL_ENABLE, "bkl_enable");
gpio_direction_output(BKL_ENABLE, 1);
/* ethernet reset */
gpio_request(FEC0_RESET, "enet0_reset");
gpio_direction_output(FEC0_RESET, 1);
}
#endif
int checkboard(void)
{
puts("Board: conga-QMX8\n");
build_info();
print_bootinfo();
return 0;
}
int board_init(void)
{
if (IS_ENABLED(CONFIG_XEN))
return 0;
#ifdef CONFIG_MXC_GPIO
board_gpio_init();
#endif
#if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
#endif
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(ulong addr)
{
/* TODO */
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
return 0;
}
#endif
int board_mmc_get_env_dev(int devno)
{
/* Use EMMC */
if (IS_ENABLED(CONFIG_XEN))
return 0;
return devno;
}
int mmc_map_to_kernel_blk(int dev_no)
{
/* Use EMMC */
if (IS_ENABLED(CONFIG_XEN))
return 0;
return dev_no;
}
extern u32 _end_ofs;
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "QMX8");
env_set("board_rev", "iMX8QM");
#endif
env_set("sec_boot", "no");
#ifdef CONFIG_AHAB_BOOT
env_set("sec_boot", "yes");
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
#ifdef IMX_LOAD_HDMI_FIMRWARE
char *end_of_uboot;
char command[256];
end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs
+ fdt_totalsize(gd->fdt_blob));
end_of_uboot += 9;
/* load hdmitxfw.bin and hdmirxfw.bin*/
memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
run_command(command, 0);
sprintf(command, "hdprx load 0x%x",
IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
run_command(command, 0);
#endif
return 0;
}
#ifdef CONFIG_FSL_FASTBOOT
#ifdef CONFIG_ANDROID_RECOVERY
int is_recovery_key_pressing(void)
{
return 0; /*TODO*/
}
#endif /*CONFIG_ANDROID_RECOVERY*/
#endif /*CONFIG_FSL_FASTBOOT*/
/* Only Enable USB3 resources currently */
int board_usb_init(int index, enum usb_init_type init)
{
return 0;
}

21
board/congatec/cgtqmx8/imximage.cfg Normal file
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@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
/* SoC type IMX8QM */
SOC_TYPE IMX8QM
/* Append seco container image */
APPEND mx8qm-ahab-container.img
/* Create the 2nd container */
CONTAINER
/* Add scfw image with exec attribute */
IMAGE SCU mx8qm-val-scfw-tcm.bin
/* Add ATF image with exec attribute */
IMAGE A35 bl31.bin 0x80000000
/* Add U-Boot image with load attribute */
DATA A35 u-boot-dtb.bin 0x80020000

77
board/congatec/cgtqmx8/spl.c Normal file
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@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
struct udevice *dev;
int offset;
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
while (offset != -FDT_ERR_NOTFOUND) {
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
NULL, true);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
"nxp,imx8-pd");
}
uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
arch_cpu_init();
board_early_init_f();
timer_init();
preloader_console_init();
puts("Normal Boot\n");
}
#if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}

48
board/congatec/common/Kconfig Normal file
View File

@ -0,0 +1,48 @@
if !ARCH_IMX8M && !ARCH_IMX8
config CHAIN_OF_TRUST
depends on !FIT_SIGNATURE && SECURE_BOOT
imply CMD_BLOB
imply CMD_HASH if ARM
select FSL_CAAM
select SPL_BOARD_INIT if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
bool
default y
config CMD_ESBC_VALIDATE
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
default y if CHAIN_OF_TRUST
help
This option enables two commands used for secure booting:
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
endif
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
default n
help
This option enables LTC3882 voltage monitor read
functionality. It is used by common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
default n
help
This option enables LTC3882 voltage monitor set
functionality. It is used by common VID driver.
config USB_TCPC
bool "USB Typec port controller simple driver"
default n
help
Enable USB type-c port controller (TCPC) driver

23
board/congatec/common/Makefile Normal file
View File

@ -0,0 +1,23 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
# necessary to create built-in.o
obj- := __dummy__.o
else
obj-y += mmc.o
endif

49
board/congatec/common/mmc.c Normal file
View File

@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
*/
#include <common.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <env.h>
#include <command.h>
#include <stdbool.h>
#include <mmc.h>
static int check_mmc_autodetect(void)
{
char *autodetect_str = env_get("mmcautodetect");
if ((autodetect_str) && (strcmp(autodetect_str, "yes") == 0))
return 1;
return 0;
}
/* This should be defined for each board */
__weak int mmc_map_to_kernel_blk(int dev_no)
{
return dev_no;
}
void board_late_mmc_env_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
if (!check_mmc_autodetect())
return;
env_set_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
mmc_map_to_kernel_blk(dev_no));
env_set("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}

11
board/freescale/common/vid.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-21 NXP
* Copyright 2020 Stephen Carlson <stcarlso@linux.microsoft.com>
*/
@ -793,13 +793,16 @@ static int do_vdd_override(struct cmd_tbl *cmdtp,
char *const argv[])
{
ulong override;
int ret = 0;
if (argc < 2)
return CMD_RET_USAGE;
if (!strict_strtoul(argv[1], 10, &override))
adjust_vdd(override); /* the value is checked by callee */
else
if (!strict_strtoul(argv[1], 10, &override)) {
ret = adjust_vdd(override);
if (ret < 0)
return CMD_RET_FAILURE;
} else
return CMD_RET_USAGE;
return 0;
}

8
board/freescale/ls1012afrdm/ls1012afrdm.c
View File

@ -23,6 +23,7 @@
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -185,6 +186,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
int ft_board_setup(void *blob, struct bd_info *bd)
{
arch_fixup_fdt(blob);

8
board/freescale/ls1012aqds/ls1012aqds.c
View File

@ -32,6 +32,7 @@
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -163,6 +164,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc0_path[] = "/soc/esdhc@1560000";

8
board/freescale/ls1012ardb/ls1012ardb.c
View File

@ -28,6 +28,7 @@
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -186,6 +187,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
#ifdef CONFIG_TARGET_LS1012ARDB
int esdhc_status_fixup(void *blob, const char *compat)
{

2
board/freescale/p1_p2_rdb_pc/MAINTAINERS
View File

@ -1,5 +1,5 @@
P1_P2_RDB_PC BOARD
#M: -
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/p1_p2_rdb_pc/
F: include/configs/p1_p2_rdb_pc.h

2
board/freescale/p2041rdb/MAINTAINERS
View File

@ -1,5 +1,5 @@
P2041RDB BOARD
#M: -
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/p2041rdb/
F: include/configs/P2041RDB.h

4
board/freescale/t102xrdb/MAINTAINERS
View File

@ -1,6 +1,6 @@
T102XRDB BOARD
#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
S: Orphan (since 2018-05)
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/t102xrdb/
F: include/configs/T102xRDB.h
F: configs/T1024RDB_defconfig

4
board/freescale/t208xrdb/Kconfig
View File

@ -9,6 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "T208xRDB"
config T2080RDB_REV_D
bool "Support for T2080RDB revisions D and up"
default n
source "board/freescale/common/Kconfig"
endif

4
board/freescale/t208xrdb/MAINTAINERS
View File

@ -8,6 +8,10 @@ F: configs/T2080RDB_NAND_defconfig
F: configs/T2080RDB_SDCARD_defconfig
F: configs/T2080RDB_SPIFLASH_defconfig
F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
F: configs/T2080RDB_revD_defconfig
F: configs/T2080RDB_revD_NAND_defconfig
F: configs/T2080RDB_revD_SDCARD_defconfig
F: configs/T2080RDB_revD_SPIFLASH_defconfig
T2080RDB_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>

112
board/freescale/t208xrdb/eth_t208xrdb.c
View File

@ -26,84 +26,7 @@
#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
int board_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x66:
case 0x6b:
fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
extern u8 get_hw_revision(void);
/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two
* "fsl,dpa-ethernet" nodes that reference them.
@ -139,6 +62,39 @@ void fdt_fixup_board_fman_ethernet(void *fdt)
}
}
/* Update the address of the second Aquantia PHY on boards revision D and up.
* Also rename the PHY node to align with the address change.
*/
void fdt_fixup_board_phy(void *fdt)
{
const char phy_path[] =
"/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1";
int ret, offset, new_addr = AQR113C_PHY_ADDR2;
char new_name[] = "ethernet-phy@00";
if (get_hw_revision() == 'C')
return;
offset = fdt_path_offset(fdt, phy_path);
if (offset < 0) {
printf("ethernet-phy@1 node not found in the dts\n");
return;
}
ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr));
if (ret < 0) {
printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
fdt_strerror(ret));
return;
}
sprintf(new_name, "ethernet-phy@%x", new_addr);
ret = fdt_set_name(fdt, offset, new_name);
if (ret < 0)
printf("Unable to rename node ethernet-phy@1: %s\n",
fdt_strerror(ret));
}
void fdt_fixup_board_enet(void *fdt)
{
return;

24
board/freescale/t208xrdb/t208xrdb.c
View File

@ -27,14 +27,29 @@
DECLARE_GLOBAL_DATA_PTR;
u8 get_hw_revision(void)
{
u8 ver = CPLD_READ(hw_ver);
switch (ver) {
default:
case 0x1:
return 'C';
case 0x0:
return 'D';
case 0x2:
return 'E';
}
}
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
get_hw_revision(), CPLD_READ(sw_ver));
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
@ -136,12 +151,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#else
fdt_fixup_board_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
fdt_fixup_board_phy(blob);
#endif
return 0;

1
board/freescale/t208xrdb/t208xrdb.h
View File

@ -10,5 +10,6 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
void fdt_fixup_board_fman_ethernet(void *blob);
void fdt_fixup_board_phy(void *blob);
#endif

4
board/freescale/t4rdb/MAINTAINERS
View File

@ -1,6 +1,6 @@
T4RDB BOARD
#M: Chunhe Lan <Chunhe.Lan@freescale.com>
S: Orphan (since 2018-05)
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/t4rdb/
F: include/configs/T4240RDB.h
F: configs/T4160RDB_defconfig

1
board/gateworks/gw_ventana/common.h
View File

@ -11,7 +11,6 @@
#include "ventana_eeprom.h"
/* GPIO's common to all baseboards */
#define GP_PHY_RST IMX_GPIO_NR(1, 30)
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)

99
board/gateworks/gw_ventana/gw_ventana.c
View File

@ -31,7 +31,6 @@
#include <linux/ctype.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
#include <pci.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
@ -54,42 +53,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct ventana_board_info ventana_info;
static int board_type;
/* ENET */
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* PHY nRST */
IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
};
static void setup_iomux_enet(int gpio)
{
SETUP_IOMUX_PADS(enet_pads);
/* toggle PHY_RST# */
gpio_request(gpio, "phy_rst#");
gpio_direction_output(gpio, 0);
mdelay(10);
gpio_set_value(gpio, 1);
mdelay(100);
}
#ifdef CONFIG_USB_EHCI_MX6
/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
int board_ehci_hcd_init(int port)
@ -195,40 +158,7 @@ int mv88e61xx_hw_reset(struct phy_device *phydev)
}
#endif // CONFIG_MV88E61XX_SWITCH
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_FEC_MXC
struct ventana_board_info *info = &ventana_info;
if (test_bit(EECONFIG_ETH0, info->config)) {
setup_iomux_enet(GP_PHY_RST);
cpu_eth_init(bis);
}
#endif
#ifdef CONFIG_E1000
e1000_initialize(bis);
#endif
#ifdef CONFIG_CI_UDC
/* For otg ethernet*/
usb_eth_initialize(bis);
#endif
/* default to the first detected enet dev */
if (!env_get("ethprime")) {
struct eth_device *dev = eth_get_dev_by_index(0);
if (dev) {
env_set("ethprime", dev->name);
printf("set ethprime to %s\n", env_get("ethprime"));
}
}
return 0;
}
#if defined(CONFIG_VIDEO_IPUV3)
static void enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
@ -427,7 +357,6 @@ int power_init_board(void)
return 0;
}
#if defined(CONFIG_CMD_PCI)
int imx6_pcie_toggle_reset(void)
{
if (board_type < GW_UNKNOWN) {
@ -448,6 +377,7 @@ int imx6_pcie_toggle_reset(void)
#define MAX_PCI_DEVS 32
struct pci_dev {
pci_dev_t devfn;
struct udevice *dev;
unsigned short vendor;
unsigned short device;
unsigned short class;
@ -458,18 +388,21 @@ struct pci_dev pci_devs[MAX_PCI_DEVS];
int pci_devno;
int pci_bridgeno;
void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
unsigned short vendor, unsigned short device,
unsigned short class)
void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
{
int i;
u32 dw;
struct pci_child_plat *pdata = dev_get_parent_plat(udev);
struct pci_dev *pdev = &pci_devs[pci_devno++];
unsigned short vendor = pdata->vendor;
unsigned short device = pdata->device;
unsigned int class = pdata->class;
pci_dev_t dev = dm_pci_get_bdf(udev);
int i;
debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
/* store array of devs for later use in device-tree fixup */
pdev->dev = udev;
pdev->devfn = dev;
pdev->vendor = vendor;
pdev->device = device;
@ -496,19 +429,19 @@ void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
if (vendor == PCI_VENDOR_ID_PLX &&
(device & 0xfff0) == 0x8600 &&
PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
ulong val;
debug("configuring PLX 860X downstream PERST#\n");
pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
dw |= 0xaaa8; /* GPIO1-7 outputs */
pci_hose_write_config_dword(hose, dev, 0x62c, dw);
pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
val |= 0xaaa8; /* GPIO1-7 outputs */
pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
pci_hose_read_config_dword(hose, dev, 0x644, &dw);
dw |= 0xfe; /* GPIO1-7 output high */
pci_hose_write_config_dword(hose, dev, 0x644, dw);
pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
val |= 0xfe; /* GPIO1-7 output high */
pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
mdelay(100);
}
}
#endif /* CONFIG_CMD_PCI */
#ifdef CONFIG_SERIAL_TAG
/*

7
board/keymile/Kconfig
View File

@ -64,6 +64,13 @@ config SYS_PAX_BASE
help
IFC Base Address for PAXx FPGA.
config SYS_CLIPS_BASE
hex "CLIPS IFC Base Address"
default 0x78000000
depends on ARCH_LS1021A
help
IFC Base Address for CLIPS FPGA.
config KM_CONSOLE_TTY
string "KM Console"
default "ttyS0"

11
board/keymile/common/common.c
View File

@ -46,12 +46,14 @@ int set_km_env(void)
unsigned int pram;
unsigned int varaddr;
unsigned int kernelmem;
char *p;
unsigned long rootfssize = 0;
char envval[16];
char *p;
pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
env_set_hex("pnvramaddr", pnvramaddr);
sprintf(envval, "0x%x", pnvramaddr);
env_set("pnvramaddr", envval);
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
@ -64,9 +66,12 @@ int set_km_env(void)
varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
sprintf(envval, "0x%x", varaddr);
env_set("varaddr", envval);
kernelmem = gd->ram_size - 0x400 * pram;
env_set_hex("kernelmem", kernelmem);
sprintf(envval, "0x%x", kernelmem);
env_set("kernelmem", envval);
return 0;
}

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