sh: Remove sh7763rdp board
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it. Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
f0debb2136
commit
73effc2dca
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@ -12,10 +12,6 @@ config TARGET_R2DPLUS
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bool "Renesas R2D-PLUS"
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select CPU_SH4
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config TARGET_SH7763RDP
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bool "SH7763RDP"
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select CPU_SH4
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endchoice
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config SYS_ARCH
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@ -27,6 +23,5 @@ config SYS_CPU
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source "arch/sh/lib/Kconfig"
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source "board/renesas/r2dplus/Kconfig"
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source "board/renesas/sh7763rdp/Kconfig"
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endmenu
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@ -1,12 +0,0 @@
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if TARGET_SH7763RDP
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config SYS_BOARD
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default "sh7763rdp"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "sh7763rdp"
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endif
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@ -1,7 +0,0 @@
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SH7763RDP BOARD
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M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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S: Maintained
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F: board/renesas/sh7763rdp/
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F: include/configs/sh7763rdp.h
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F: configs/sh7763rdp_defconfig
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2008 Renesas Solutions Corp.
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# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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# Copyright (C) 2007 Kenati Technologies, Inc.
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#
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# board/sh7763rdp/Makefile
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obj-y := sh7763rdp.o
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extra-y += lowlevel_init.o
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@ -1,259 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2007 Kenati Technologies, Inc.
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*
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* board/sh7763rdp/lowlevel_init.S
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
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write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
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write32 WDTBST_A, WDTBST_D /*
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* 0xFFCC0008
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* Watchdog Base Stop Time Register
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*/
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write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
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/* Instruction Cache Invalidate */
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write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
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/* TI == TLB Invalidate bit */
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write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
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write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
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write32 RAMCR_A, RAMCR_D
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mov.l MMSELR_A, r1
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mov.l MMSELR_D, r0
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synco
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mov.l r0, @r1
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mov.l @r1, r2 /* execute two reads after setting MMSELR */
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mov.l @r1, r2
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synco
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/* issue memory read */
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mov.l DDRSD_START_A, r1 /* memory address to read*/
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mov.l @r1, r0
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synco
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write32 MIM8_A, MIM8_D
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write32 MIMC_A, MIMC_D1
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write32 STRC_A, STRC_D
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write32 SDR4_A, SDR4_D
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write32 MIMC_A, MIMC_D2
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nop
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nop
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nop
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write32 SCR4_A, SCR4_D3
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write32 SCR4_A, SCR4_D2
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write32 SDMR02000_A, SDMR02000_D
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write32 SDMR00B08_A, SDMR00B08_D
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write32 SCR4_A, SCR4_D2
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write32 SCR4_A, SCR4_D4
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nop
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nop
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nop
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nop
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write32 SCR4_A, SCR4_D4
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nop
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nop
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nop
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nop
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write32 SDMR00308_A, SDMR00308_D
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write32 MIMC_A, MIMC_D3
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mov.l SCR4_A, r1
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mov.l SCR4_D1, r0
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mov.l DELAY60_D, r3
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delay_loop_60:
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mov.l r0, @r1
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dt r3
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bf delay_loop_60
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nop
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write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
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bsc_init:
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write32 BCR_A, BCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS1BCR_A, CS1BCR_D
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write32 CS2BCR_A, CS2BCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS5BCR_A, CS5BCR_D
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write32 CS6BCR_A, CS6BCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS1WCR_A, CS1WCR_D
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write32 CS2WCR_A, CS2WCR_D
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write32 CS4WCR_A, CS4WCR_D
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write32 CS5WCR_A, CS5WCR_D
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write32 CS6WCR_A, CS6WCR_D
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write32 CS5PCR_A, CS5PCR_D
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write32 CS6PCR_A, CS6PCR_D
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mov.l DELAY200_D, r3
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delay_loop_200:
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dt r3
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bf delay_loop_200
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nop
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write16 PSEL0_A, PSEL0_D
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write16 PSEL1_A, PSEL1_D
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write32 ICR0_A, ICR0_D
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stc sr, r0 /* BL bit off(init=ON) */
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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nop
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.align 2
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DELAY60_D: .long 60
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DELAY200_D: .long 17800
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CCR_A: .long 0xFF00001C
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MMUCR_A: .long 0xFF000010
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RAMCR_A: .long 0xFF000074
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/* Low power mode control */
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MSTPCR0_A: .long 0xFFC80030
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MSTPCR1_A: .long 0xFFC80038
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/* RWBT */
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WDTST_A: .long 0xFFCC0000
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WDTCSR_A: .long 0xFFCC0004
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WDTBST_A: .long 0xFFCC0008
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/* BSC */
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MMSELR_A: .long 0xFE600020
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BCR_A: .long 0xFF801000
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CS0BCR_A: .long 0xFF802000
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CS1BCR_A: .long 0xFF802010
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CS2BCR_A: .long 0xFF802020
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CS4BCR_A: .long 0xFF802040
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CS5BCR_A: .long 0xFF802050
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CS6BCR_A: .long 0xFF802060
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CS0WCR_A: .long 0xFF802008
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CS1WCR_A: .long 0xFF802018
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CS2WCR_A: .long 0xFF802028
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CS4WCR_A: .long 0xFF802048
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CS5WCR_A: .long 0xFF802058
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CS6WCR_A: .long 0xFF802068
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CS5PCR_A: .long 0xFF802070
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CS6PCR_A: .long 0xFF802080
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DDRSD_START_A: .long 0xAC000000
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/* INTC */
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ICR0_A: .long 0xFFD00000
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/* DDR I/F */
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MIM8_A: .long 0xFE800008
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MIMC_A: .long 0xFE80000C
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SCR4_A: .long 0xFE800014
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STRC_A: .long 0xFE80001C
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SDR4_A: .long 0xFE800034
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SDMR00308_A: .long 0xFE900308
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SDMR00B08_A: .long 0xFE900B08
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SDMR02000_A: .long 0xFE902000
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/* GPIO */
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PSEL0_A: .long 0xFFEF0070
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PSEL1_A: .long 0xFFEF0072
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CCR_CACHE_ICI_D:.long 0x00000800
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CCR_CACHE_D_2: .long 0x00000103
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MMU_CONTROL_TI_D:.long 0x00000004
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RAMCR_D: .long 0x00000200
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MSTPCR0_D: .long 0x00000000
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MSTPCR1_D: .long 0x00000000
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MMSELR_D: .long 0xa5a50000
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BCR_D: .long 0x00000000
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CS0BCR_D: .long 0x77777770
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CS1BCR_D: .long 0x77777670
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CS2BCR_D: .long 0x77777670
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CS4BCR_D: .long 0x77777670
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CS5BCR_D: .long 0x77777670
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CS6BCR_D: .long 0x77777670
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CS0WCR_D: .long 0x7777770F
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CS1WCR_D: .long 0x22000002
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CS2WCR_D: .long 0x7777770F
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CS4WCR_D: .long 0x7777770F
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CS5WCR_D: .long 0x7777770F
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CS6WCR_D: .long 0x7777770F
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CS5PCR_D: .long 0x77000000
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CS6PCR_D: .long 0x77000000
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ICR0_D: .long 0x00E00000
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MIM8_D: .long 0x00000000
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MIMC_D1: .long 0x01d10008
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MIMC_D2: .long 0x01d10009
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MIMC_D3: .long 0x01d10209
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SCR4_D1: .long 0x00000001
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SCR4_D2: .long 0x00000002
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SCR4_D3: .long 0x00000003
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SCR4_D4: .long 0x00000004
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STRC_D: .long 0x000f3980
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SDR4_D: .long 0x00000300
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SDMR00308_D: .long 0x00000000
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SDMR00B08_D: .long 0x00000000
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SDMR02000_D: .long 0x00000000
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PSEL0_D: .word 0x00000001
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PSEL1_D: .word 0x00000244
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SR_MASK_D: .long 0xEFFFFF0F
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WDTST_D: .long 0x5A000FFF
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WDTCSR_D: .long 0xA5000000
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WDTBST_D: .long 0x55000000
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@ -1,54 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2007 Kenati Technologies, Inc.
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*
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* board/sh7763rdp/sh7763rdp.c
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#define CPU_CMDREG 0xB1000006
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#define PDCR 0xffef0006
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#define PECR 0xffef0008
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#define PFCR 0xffef000a
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#define PGCR 0xffef000c
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#define PHCR 0xffef000e
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#define PJCR 0xffef0012
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#define PKCR 0xffef0014
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#define PLCR 0xffef0016
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#define PMCR 0xffef0018
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#define PSEL1 0xffef0072
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#define PSEL2 0xffef0074
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#define PSEL3 0xffef0076
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int checkboard(void)
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{
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puts("BOARD: Renesas SH7763 RDP\n");
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return 0;
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}
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int board_init(void)
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{
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vu_short dat;
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/* Enable mode */
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writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
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/* GPIO Setting (eth1) */
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dat = inw(PSEL1);
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writew(((dat & ~0xff00) | 0x2400), PSEL1);
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writew(0, PFCR);
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writew(0, PGCR);
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writew(0, PHCR);
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return 0;
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}
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void led_set_state(unsigned short value)
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{
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}
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@ -1,42 +0,0 @@
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CONFIG_SH=y
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CONFIG_SYS_TEXT_BASE=0x8FFC0000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_TARGET_SH7763RDP=y
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CONFIG_BOOTDELAY=-1
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttySC2,115200 root=1f01"
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# CONFIG_CMDLINE_EDITING is not set
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# CONFIG_AUTO_COMPLETE is not set
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_RUN is not set
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_EDITENV is not set
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# CONFIG_CMD_ENV_EXISTS is not set
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_SDRAM=y
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# CONFIG_CMD_ECHO is not set
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# CONFIG_CMD_ITEST is not set
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# CONFIG_CMD_SOURCE is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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# CONFIG_CMD_SLEEP is not set
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CONFIG_CMD_JFFS2=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_ENV_ADDR=0xA0020000
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CONFIG_ENV_ADDR_REDUND=0xA0040000
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CONFIG_VERSION_VARIABLE=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_BITBANGMII=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -1,66 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Renesas SH7763RDP board
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*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*/
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#ifndef __SH7763RDP_H
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#define __SH7763RDP_H
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#define CONFIG_CPU_SH7763 1
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#define __LITTLE_ENDIAN 1
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#define CONFIG_DISPLAY_BOARDINFO
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/* SCIF */
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#define CONFIG_CONS_SCIF2 1
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#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
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settings for this board */
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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/* Flash(NOR) */
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#define CONFIG_SYS_FLASH_BASE (0xA0000000)
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#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
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#define CONFIG_SYS_MAX_FLASH_BANKS (1)
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#define CONFIG_SYS_MAX_FLASH_SECT (520)
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/* U-Boot setting */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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/* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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/* Timeout for Flash erase operations (in ms) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
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/* Timeout for Flash write operations (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
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/* Timeout for Flash set sector lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
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/* Timeout for Flash clear lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
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/* Use hardware flash sectors protection instead of U-Boot software protection */
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#undef CONFIG_SYS_DIRECT_FLASH_TFTP
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/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
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||||
|
||||
/* Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
|
||||
/* Ether */
|
||||
#define CONFIG_SH_ETHER_USE_PORT (1)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
|
||||
|
||||
#endif /* __SH7763RDP_H */
|
||||
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Reference in New Issue