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powerpc, 8xx: Implement GLL2 ERRATA
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Acked-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
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@ -51,6 +51,26 @@ void cpu_init_f(immap_t __iomem *immr)
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clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
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clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
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CONFIG_SYS_SCCR);
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CONFIG_SYS_SCCR);
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/*
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* MPC866/885 ERRATA GLL2
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* Description:
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* In 1:2:1 mode, when HRESET is detected at the positive edge of
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* EXTCLK, then there will be a loss of phase between
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* EXTCLK and CLKOUT.
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*
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* Workaround:
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* Reprogram the SCCR:
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* 1. Write 1'b00 to SCCR[EBDF].
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* 2. Write 1'b01 to SCCR[EBDF].
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* 3. Rewrite the desired value to the PLPRCR register.
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*/
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reg = in_be32(&immr->im_clkrst.car_sccr);
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/* Are we in mode 1:2:1 ? */
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if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
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clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
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setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
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}
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/* PLL (CPU clock) settings (15-30) */
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/* PLL (CPU clock) settings (15-30) */
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out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
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out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
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