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powerpc, 8xx: Implement GLL2 ERRATA

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Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Christophe Leroy 2017-07-06 16:49:56 +02:00 committed by Tom Rini
parent ba3da7348a
commit 73bc94c6b7
1 changed files with 20 additions and 0 deletions
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20
arch/powerpc/cpu/mpc8xx/cpu_init.c
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@ -51,6 +51,26 @@ void cpu_init_f(immap_t __iomem *immr)
clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
CONFIG_SYS_SCCR);
/*
* MPC866/885 ERRATA GLL2
* Description:
* In 1:2:1 mode, when HRESET is detected at the positive edge of
* EXTCLK, then there will be a loss of phase between
* EXTCLK and CLKOUT.
*
* Workaround:
* Reprogram the SCCR:
* 1. Write 1'b00 to SCCR[EBDF].
* 2. Write 1'b01 to SCCR[EBDF].
* 3. Rewrite the desired value to the PLPRCR register.
*/
reg = in_be32(&immr->im_clkrst.car_sccr);
/* Are we in mode 1:2:1 ? */
if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
}
/* PLL (CPU clock) settings (15-30) */
out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);