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https://github.com/brain-hackers/u-boot-brain
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ddr: altera: Restructure Stratix 10 SDRAM driver
Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
a6e5b06bea
commit
733cc6cbcc
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@ -9,5 +9,5 @@
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ifdef CONFIG_$(SPL_)ALTERA_SDRAM
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obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
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obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
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obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
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endif
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@ -15,28 +15,14 @@
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#include "sdram_s10.h"
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#include <wait_bit.h>
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#include <asm/arch/firewall.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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struct altera_sdram_priv {
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struct ram_info info;
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struct reset_ctl_bulk resets;
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};
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struct altera_sdram_platdata {
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void __iomem *hmc;
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void __iomem *ddr_sch;
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void __iomem *iomhc;
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};
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DECLARE_GLOBAL_DATA_PTR;
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#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
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#define PGTABLE_OFF 0x4000
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/* The followring are the supported configurations */
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u32 ddr_config[] = {
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/* DDR_CONFIG(Address order,Bank,Column,Row) */
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@ -63,28 +49,6 @@ u32 ddr_config[] = {
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DDR_CONFIG(1, 4, 10, 17),
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};
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static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
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{
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return readl(plat->iomhc + reg);
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}
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static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
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{
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return readl(plat->hmc + reg);
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}
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static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
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u32 data, u32 reg)
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{
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return writel(data, plat->hmc + reg);
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}
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static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
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u32 reg)
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{
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return writel(data, plat->ddr_sch + reg);
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}
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int match_ddr_conf(u32 ddr_conf)
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{
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int i;
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@ -96,193 +60,12 @@ int match_ddr_conf(u32 ddr_conf)
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return 0;
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}
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static int emif_clear(struct altera_sdram_platdata *plat)
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{
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hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
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return wait_for_bit_le32((const void *)(plat->hmc +
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RSTHANDSHAKESTAT),
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DDR_HMC_RSTHANDSHAKE_MASK,
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false, 1000, false);
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}
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static int emif_reset(struct altera_sdram_platdata *plat)
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{
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u32 c2s, s2c, ret;
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c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
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s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
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debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
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c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
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hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
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hmc_readl(plat, DRAMSTS));
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if (s2c && emif_clear(plat)) {
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printf("DDR: emif_clear() failed\n");
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return -1;
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}
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debug("DDR: Triggerring emif reset\n");
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hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
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/* if seq2core[3] = 0, we are good */
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ret = wait_for_bit_le32((const void *)(plat->hmc +
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RSTHANDSHAKESTAT),
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DDR_HMC_SEQ2CORE_INT_RESP_MASK,
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false, 1000, false);
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if (ret) {
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printf("DDR: failed to get ack from EMIF\n");
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return ret;
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}
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ret = emif_clear(plat);
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if (ret) {
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printf("DDR: emif_clear() failed\n");
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return ret;
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}
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debug("DDR: %s triggered successly\n", __func__);
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return 0;
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}
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static int poll_hmc_clock_status(void)
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{
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return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_HMC_CLK),
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SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
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}
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static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
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{
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phys_size_t i;
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if (addr % CONFIG_SYS_CACHELINE_SIZE) {
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printf("DDR: address 0x%llx is not cacheline size aligned.\n",
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addr);
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hang();
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}
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if (size % CONFIG_SYS_CACHELINE_SIZE) {
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printf("DDR: size 0x%llx is not multiple of cacheline size\n",
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size);
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hang();
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}
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/* Use DC ZVA instruction to clear memory to zeros by a cache line */
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for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
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asm volatile("dc zva, %0"
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:
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: "r"(addr)
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: "memory");
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addr += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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static void sdram_init_ecc_bits(bd_t *bd)
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{
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phys_size_t size, size_init;
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phys_addr_t start_addr;
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int bank = 0;
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unsigned int start = get_timer(0);
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icache_enable();
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start_addr = bd->bi_dram[0].start;
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size = bd->bi_dram[0].size;
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/* Initialize small block for page table */
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memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
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gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
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gd->arch.tlb_size = PGTABLE_SIZE;
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start_addr += PGTABLE_SIZE + PGTABLE_OFF;
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size -= (PGTABLE_OFF + PGTABLE_SIZE);
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dcache_enable();
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while (1) {
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while (size) {
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size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
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sdram_clear_mem(start_addr, size_init);
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size -= size_init;
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start_addr += size_init;
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WATCHDOG_RESET();
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}
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bank++;
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if (bank >= CONFIG_NR_DRAM_BANKS)
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break;
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start_addr = bd->bi_dram[bank].start;
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size = bd->bi_dram[bank].size;
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}
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dcache_disable();
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icache_disable();
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printf("SDRAM-ECC: Initialized success with %d ms\n",
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(unsigned int)get_timer(start));
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}
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static void sdram_size_check(bd_t *bd)
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{
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phys_size_t total_ram_check = 0;
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phys_size_t ram_check = 0;
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phys_addr_t start = 0;
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int bank;
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/* Sanity check ensure correct SDRAM size specified */
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debug("DDR: Running SDRAM size sanity check\n");
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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start = bd->bi_dram[bank].start;
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while (ram_check < bd->bi_dram[bank].size) {
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ram_check += get_ram_size((void *)(start + ram_check),
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(phys_size_t)SZ_1G);
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}
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total_ram_check += ram_check;
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ram_check = 0;
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}
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/* If the ram_size is 2GB smaller, we can assume the IO space is
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* not mapped in. gd->ram_size is the actual size of the dram
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* not the accessible size.
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*/
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if (total_ram_check != gd->ram_size) {
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puts("DDR: SDRAM size check failed!\n");
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hang();
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}
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debug("DDR: SDRAM size check passed!\n");
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}
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/**
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* sdram_calculate_size() - Calculate SDRAM size
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*
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* Calculate SDRAM device size based on SDRAM controller parameters.
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* Size is specified in bytes.
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*/
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static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
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{
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u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
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phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
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size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
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DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
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return size;
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}
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/**
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* sdram_mmr_init_full() - Function to initialize SDRAM MMR
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*
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* Initialize the SDRAM MMR.
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*/
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static int sdram_mmr_init_full(struct udevice *dev)
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int sdram_mmr_init_full(struct udevice *dev)
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{
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struct altera_sdram_platdata *plat = dev->platdata;
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struct altera_sdram_priv *priv = dev_get_priv(dev);
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@ -535,80 +318,3 @@ static int sdram_mmr_init_full(struct udevice *dev)
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return 0;
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}
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static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
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{
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struct altera_sdram_platdata *plat = dev->platdata;
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fdt_addr_t addr;
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->ddr_sch = (void __iomem *)addr;
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addr = dev_read_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->iomhc = (void __iomem *)addr;
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addr = dev_read_addr_index(dev, 2);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->hmc = (void __iomem *)addr;
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return 0;
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}
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static int altera_sdram_probe(struct udevice *dev)
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{
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int ret;
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struct altera_sdram_priv *priv = dev_get_priv(dev);
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ret = reset_get_bulk(dev, &priv->resets);
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if (ret) {
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dev_err(dev, "Can't get reset: %d\n", ret);
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return -ENODEV;
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}
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reset_deassert_bulk(&priv->resets);
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if (sdram_mmr_init_full(dev) != 0) {
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puts("SDRAM init failed.\n");
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goto failed;
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}
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return 0;
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failed:
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reset_release_bulk(&priv->resets);
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return -ENODEV;
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}
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static int altera_sdram_get_info(struct udevice *dev,
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struct ram_info *info)
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{
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struct altera_sdram_priv *priv = dev_get_priv(dev);
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info->base = priv->info.base;
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info->size = priv->info.size;
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return 0;
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}
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static struct ram_ops altera_sdram_ops = {
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.get_info = altera_sdram_get_info,
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};
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static const struct udevice_id altera_sdram_ids[] = {
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{ .compatible = "altr,sdr-ctl-s10" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(altera_sdram) = {
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.name = "altr_sdr_ctl",
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.id = UCLASS_RAM,
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.of_match = altera_sdram_ids,
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.ops = &altera_sdram_ops,
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.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
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.probe = altera_sdram_probe,
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.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
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};
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@ -11,48 +11,6 @@
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#define DDR_READ_LATENCY_DELAY 40
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#define DDR_ACTIVATE_FAWBANK 0x1
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/* ECC HMC registers */
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#define DDRIOCTRL 0x8
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#define DDRCALSTAT 0xc
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#define DRAMADDRWIDTH 0xe0
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#define ECCCTRL1 0x100
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#define ECCCTRL2 0x104
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#define ERRINTEN 0x110
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#define ERRINTENS 0x114
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#define INTMODE 0x11c
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#define INTSTAT 0x120
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#define AUTOWB_CORRADDR 0x138
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#define ECC_REG2WRECCDATABUS 0x144
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#define ECC_DIAGON 0x150
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#define ECC_DECSTAT 0x154
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#define HPSINTFCSEL 0x210
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#define RSTHANDSHAKECTRL 0x214
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#define RSTHANDSHAKESTAT 0x218
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#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
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#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
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#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
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#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
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#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
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#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
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#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
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#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
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#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
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#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
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#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
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#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
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#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
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#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
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#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
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#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
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#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
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#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
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#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
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#define DDR_HMC_ERRINTEN_INTMASK \
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(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
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DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
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/* NOC DDR scheduler */
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#define DDR_SCH_ID_COREID 0
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#define DDR_SCH_ID_REVID 0x4
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@ -79,110 +37,6 @@
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#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2
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#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
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/* HMC MMR IO48 registers */
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#define CTRLCFG0 0x28
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#define CTRLCFG1 0x2c
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#define DRAMTIMING0 0x50
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#define CALTIMING0 0x7c
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#define CALTIMING1 0x80
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#define CALTIMING2 0x84
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#define CALTIMING3 0x88
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#define CALTIMING4 0x8c
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#define CALTIMING9 0xa0
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#define DRAMADDRW 0xa8
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#define DRAMSTS 0xec
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#define NIOSRESERVED0 0x110
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#define NIOSRESERVED1 0x114
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#define NIOSRESERVED2 0x118
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#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
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(((x) >> 0) & 0x1F)
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#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
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(((x) >> 5) & 0x1F)
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#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
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(((x) >> 10) & 0xF)
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#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
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(((x) >> 14) & 0x3)
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#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
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(((x) >> 16) & 0x7)
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#define CTRLCFG0_CFG_MEMTYPE(x) \
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(((x) >> 0) & 0xF)
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#define CTRLCFG0_CFG_DIMM_TYPE(x) \
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(((x) >> 4) & 0x7)
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#define CTRLCFG0_CFG_AC_POS(x) \
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(((x) >> 7) & 0x3)
|
||||
#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
|
||||
(((x) >> 9) & 0x1F)
|
||||
|
||||
#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
|
||||
(((x) >> 0) & 0x1F)
|
||||
#define CTRLCFG1_CFG_ADDR_ORDER(x) \
|
||||
(((x) >> 5) & 0x3)
|
||||
#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
|
||||
(((x) >> 7) & 0x1)
|
||||
|
||||
#define DRAMTIMING0_CFG_TCL(x) \
|
||||
(((x) >> 0) & 0x7F)
|
||||
|
||||
#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_PCH(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_ACT(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
|
||||
#define CALTIMING1_CFG_RD_TO_RD(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_WR(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING2_CFG_WR_TO_WR(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_PCH(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING4_CFG_PCH_TO_VALID(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING4_CFG_ARF_TO_VALID(x) \
|
||||
(((x) >> 18) & 0xFF)
|
||||
#define CALTIMING4_CFG_PDN_TO_VALID(x) \
|
||||
(((x) >> 26) & 0x3F)
|
||||
|
||||
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
|
||||
(((x) >> 0) & 0xFF)
|
||||
|
||||
/* Firewall DDR scheduler MPFE */
|
||||
#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
|
||||
#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
|
||||
#include "sdram_soc64.h"
|
||||
|
||||
#endif /* _SDRAM_S10_H_ */
|
||||
|
|
|
|||
304
drivers/ddr/altera/sdram_soc64.c
Normal file
304
drivers/ddr/altera/sdram_soc64.c
Normal file
|
|
@ -0,0 +1,304 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <div64.h>
|
||||
#include <fdtdec.h>
|
||||
#include <ram.h>
|
||||
#include <reset.h>
|
||||
#include "sdram_soc64.h"
|
||||
#include <wait_bit.h>
|
||||
#include <asm/arch/firewall.h>
|
||||
#include <asm/arch/system_manager.h>
|
||||
#include <asm/arch/reset_manager.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#define PGTABLE_OFF 0x4000
|
||||
|
||||
u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
|
||||
{
|
||||
return readl(plat->iomhc + reg);
|
||||
}
|
||||
|
||||
u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
|
||||
{
|
||||
return readl(plat->hmc + reg);
|
||||
}
|
||||
|
||||
u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
|
||||
u32 data, u32 reg)
|
||||
{
|
||||
return writel(data, plat->hmc + reg);
|
||||
}
|
||||
|
||||
u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
|
||||
u32 reg)
|
||||
{
|
||||
return writel(data, plat->ddr_sch + reg);
|
||||
}
|
||||
|
||||
int emif_clear(struct altera_sdram_platdata *plat)
|
||||
{
|
||||
hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
|
||||
|
||||
return wait_for_bit_le32((const void *)(plat->hmc +
|
||||
RSTHANDSHAKESTAT),
|
||||
DDR_HMC_RSTHANDSHAKE_MASK,
|
||||
false, 1000, false);
|
||||
}
|
||||
|
||||
int emif_reset(struct altera_sdram_platdata *plat)
|
||||
{
|
||||
u32 c2s, s2c, ret;
|
||||
|
||||
c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
|
||||
s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
|
||||
|
||||
debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
|
||||
c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
|
||||
hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
|
||||
hmc_readl(plat, DRAMSTS));
|
||||
|
||||
if (s2c && emif_clear(plat)) {
|
||||
printf("DDR: emif_clear() failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
debug("DDR: Triggerring emif reset\n");
|
||||
hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
|
||||
|
||||
/* if seq2core[3] = 0, we are good */
|
||||
ret = wait_for_bit_le32((const void *)(plat->hmc +
|
||||
RSTHANDSHAKESTAT),
|
||||
DDR_HMC_SEQ2CORE_INT_RESP_MASK,
|
||||
false, 1000, false);
|
||||
if (ret) {
|
||||
printf("DDR: failed to get ack from EMIF\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = emif_clear(plat);
|
||||
if (ret) {
|
||||
printf("DDR: emif_clear() failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
debug("DDR: %s triggered successly\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int poll_hmc_clock_status(void)
|
||||
{
|
||||
return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
|
||||
SYSMGR_SOC64_HMC_CLK),
|
||||
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
|
||||
}
|
||||
|
||||
void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
|
||||
{
|
||||
phys_size_t i;
|
||||
|
||||
if (addr % CONFIG_SYS_CACHELINE_SIZE) {
|
||||
printf("DDR: address 0x%llx is not cacheline size aligned.\n",
|
||||
addr);
|
||||
hang();
|
||||
}
|
||||
|
||||
if (size % CONFIG_SYS_CACHELINE_SIZE) {
|
||||
printf("DDR: size 0x%llx is not multiple of cacheline size\n",
|
||||
size);
|
||||
hang();
|
||||
}
|
||||
|
||||
/* Use DC ZVA instruction to clear memory to zeros by a cache line */
|
||||
for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
|
||||
asm volatile("dc zva, %0"
|
||||
:
|
||||
: "r"(addr)
|
||||
: "memory");
|
||||
addr += CONFIG_SYS_CACHELINE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void sdram_init_ecc_bits(bd_t *bd)
|
||||
{
|
||||
phys_size_t size, size_init;
|
||||
phys_addr_t start_addr;
|
||||
int bank = 0;
|
||||
unsigned int start = get_timer(0);
|
||||
|
||||
icache_enable();
|
||||
|
||||
start_addr = bd->bi_dram[0].start;
|
||||
size = bd->bi_dram[0].size;
|
||||
|
||||
/* Initialize small block for page table */
|
||||
memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
|
||||
gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
|
||||
gd->arch.tlb_size = PGTABLE_SIZE;
|
||||
start_addr += PGTABLE_SIZE + PGTABLE_OFF;
|
||||
size -= (PGTABLE_OFF + PGTABLE_SIZE);
|
||||
dcache_enable();
|
||||
|
||||
while (1) {
|
||||
while (size) {
|
||||
size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
|
||||
sdram_clear_mem(start_addr, size_init);
|
||||
size -= size_init;
|
||||
start_addr += size_init;
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
bank++;
|
||||
if (bank >= CONFIG_NR_DRAM_BANKS)
|
||||
break;
|
||||
|
||||
start_addr = bd->bi_dram[bank].start;
|
||||
size = bd->bi_dram[bank].size;
|
||||
}
|
||||
|
||||
dcache_disable();
|
||||
icache_disable();
|
||||
|
||||
printf("SDRAM-ECC: Initialized success with %d ms\n",
|
||||
(unsigned int)get_timer(start));
|
||||
}
|
||||
|
||||
void sdram_size_check(bd_t *bd)
|
||||
{
|
||||
phys_size_t total_ram_check = 0;
|
||||
phys_size_t ram_check = 0;
|
||||
phys_addr_t start = 0;
|
||||
int bank;
|
||||
|
||||
/* Sanity check ensure correct SDRAM size specified */
|
||||
debug("DDR: Running SDRAM size sanity check\n");
|
||||
|
||||
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
|
||||
start = bd->bi_dram[bank].start;
|
||||
while (ram_check < bd->bi_dram[bank].size) {
|
||||
ram_check += get_ram_size((void *)(start + ram_check),
|
||||
(phys_size_t)SZ_1G);
|
||||
}
|
||||
total_ram_check += ram_check;
|
||||
ram_check = 0;
|
||||
}
|
||||
|
||||
/* If the ram_size is 2GB smaller, we can assume the IO space is
|
||||
* not mapped in. gd->ram_size is the actual size of the dram
|
||||
* not the accessible size.
|
||||
*/
|
||||
if (total_ram_check != gd->ram_size) {
|
||||
puts("DDR: SDRAM size check failed!\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
debug("DDR: SDRAM size check passed!\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* sdram_calculate_size() - Calculate SDRAM size
|
||||
*
|
||||
* Calculate SDRAM device size based on SDRAM controller parameters.
|
||||
* Size is specified in bytes.
|
||||
*/
|
||||
phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
|
||||
{
|
||||
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
|
||||
|
||||
phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
|
||||
|
||||
size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
|
||||
DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct altera_sdram_platdata *plat = dev->platdata;
|
||||
fdt_addr_t addr;
|
||||
|
||||
addr = dev_read_addr_index(dev, 0);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
plat->ddr_sch = (void __iomem *)addr;
|
||||
|
||||
addr = dev_read_addr_index(dev, 1);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
plat->iomhc = (void __iomem *)addr;
|
||||
|
||||
addr = dev_read_addr_index(dev, 2);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
plat->hmc = (void __iomem *)addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int altera_sdram_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
struct altera_sdram_priv *priv = dev_get_priv(dev);
|
||||
|
||||
ret = reset_get_bulk(dev, &priv->resets);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get reset: %d\n", ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
reset_deassert_bulk(&priv->resets);
|
||||
|
||||
if (sdram_mmr_init_full(dev) != 0) {
|
||||
puts("SDRAM init failed.\n");
|
||||
goto failed;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
failed:
|
||||
reset_release_bulk(&priv->resets);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int altera_sdram_get_info(struct udevice *dev,
|
||||
struct ram_info *info)
|
||||
{
|
||||
struct altera_sdram_priv *priv = dev_get_priv(dev);
|
||||
|
||||
info->base = priv->info.base;
|
||||
info->size = priv->info.size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ram_ops altera_sdram_ops = {
|
||||
.get_info = altera_sdram_get_info,
|
||||
};
|
||||
|
||||
static const struct udevice_id altera_sdram_ids[] = {
|
||||
{ .compatible = "altr,sdr-ctl-s10" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(altera_sdram) = {
|
||||
.name = "altr_sdr_ctl",
|
||||
.id = UCLASS_RAM,
|
||||
.of_match = altera_sdram_ids,
|
||||
.ops = &altera_sdram_ops,
|
||||
.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
|
||||
.probe = altera_sdram_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
|
||||
};
|
||||
186
drivers/ddr/altera/sdram_soc64.h
Normal file
186
drivers/ddr/altera/sdram_soc64.h
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef _SDRAM_SOC64_H_
|
||||
#define _SDRAM_SOC64_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
struct altera_sdram_priv {
|
||||
struct ram_info info;
|
||||
struct reset_ctl_bulk resets;
|
||||
};
|
||||
|
||||
struct altera_sdram_platdata {
|
||||
void __iomem *hmc;
|
||||
void __iomem *ddr_sch;
|
||||
void __iomem *iomhc;
|
||||
};
|
||||
|
||||
/* ECC HMC registers */
|
||||
#define DDRIOCTRL 0x8
|
||||
#define DDRCALSTAT 0xc
|
||||
#define DRAMADDRWIDTH 0xe0
|
||||
#define ECCCTRL1 0x100
|
||||
#define ECCCTRL2 0x104
|
||||
#define ERRINTEN 0x110
|
||||
#define ERRINTENS 0x114
|
||||
#define INTMODE 0x11c
|
||||
#define INTSTAT 0x120
|
||||
#define AUTOWB_CORRADDR 0x138
|
||||
#define ECC_REG2WRECCDATABUS 0x144
|
||||
#define ECC_DIAGON 0x150
|
||||
#define ECC_DECSTAT 0x154
|
||||
#define HPSINTFCSEL 0x210
|
||||
#define RSTHANDSHAKECTRL 0x214
|
||||
#define RSTHANDSHAKESTAT 0x218
|
||||
|
||||
#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
|
||||
#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
|
||||
#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
|
||||
#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
|
||||
#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
|
||||
#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
|
||||
#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
|
||||
#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
|
||||
#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
|
||||
#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
|
||||
#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
|
||||
#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
|
||||
#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
|
||||
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
|
||||
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
|
||||
|
||||
#define DDR_HMC_ERRINTEN_INTMASK \
|
||||
(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
|
||||
DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
|
||||
|
||||
/* HMC MMR IO48 registers */
|
||||
#define CTRLCFG0 0x28
|
||||
#define CTRLCFG1 0x2c
|
||||
#define DRAMTIMING0 0x50
|
||||
#define CALTIMING0 0x7c
|
||||
#define CALTIMING1 0x80
|
||||
#define CALTIMING2 0x84
|
||||
#define CALTIMING3 0x88
|
||||
#define CALTIMING4 0x8c
|
||||
#define CALTIMING9 0xa0
|
||||
#define DRAMADDRW 0xa8
|
||||
#define DRAMSTS 0xec
|
||||
#define NIOSRESERVED0 0x110
|
||||
#define NIOSRESERVED1 0x114
|
||||
#define NIOSRESERVED2 0x118
|
||||
|
||||
#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
|
||||
(((x) >> 0) & 0x1F)
|
||||
#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
|
||||
(((x) >> 5) & 0x1F)
|
||||
#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
|
||||
(((x) >> 10) & 0xF)
|
||||
#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
|
||||
(((x) >> 14) & 0x3)
|
||||
#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
|
||||
(((x) >> 16) & 0x7)
|
||||
|
||||
#define CTRLCFG0_CFG_MEMTYPE(x) \
|
||||
(((x) >> 0) & 0xF)
|
||||
#define CTRLCFG0_CFG_DIMM_TYPE(x) \
|
||||
(((x) >> 4) & 0x7)
|
||||
#define CTRLCFG0_CFG_AC_POS(x) \
|
||||
(((x) >> 7) & 0x3)
|
||||
#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
|
||||
(((x) >> 9) & 0x1F)
|
||||
|
||||
#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
|
||||
(((x) >> 0) & 0x1F)
|
||||
#define CTRLCFG1_CFG_ADDR_ORDER(x) \
|
||||
(((x) >> 5) & 0x3)
|
||||
#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
|
||||
(((x) >> 7) & 0x1)
|
||||
|
||||
#define DRAMTIMING0_CFG_TCL(x) \
|
||||
(((x) >> 0) & 0x7F)
|
||||
|
||||
#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_PCH(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_ACT(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
|
||||
#define CALTIMING1_CFG_RD_TO_RD(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_WR(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING2_CFG_WR_TO_WR(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_PCH(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING4_CFG_PCH_TO_VALID(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING4_CFG_ARF_TO_VALID(x) \
|
||||
(((x) >> 18) & 0xFF)
|
||||
#define CALTIMING4_CFG_PDN_TO_VALID(x) \
|
||||
(((x) >> 26) & 0x3F)
|
||||
|
||||
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
|
||||
(((x) >> 0) & 0xFF)
|
||||
|
||||
/* Firewall DDR scheduler MPFE */
|
||||
#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
|
||||
#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
|
||||
|
||||
u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg);
|
||||
u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg);
|
||||
u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
|
||||
u32 data, u32 reg);
|
||||
u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
|
||||
u32 reg);
|
||||
int emif_clear(struct altera_sdram_platdata *plat);
|
||||
int emif_reset(struct altera_sdram_platdata *plat);
|
||||
int poll_hmc_clock_status(void);
|
||||
void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
|
||||
void sdram_init_ecc_bits(bd_t *bd);
|
||||
void sdram_size_check(bd_t *bd);
|
||||
phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat);
|
||||
int sdram_mmr_init_full(struct udevice *dev);
|
||||
|
||||
#endif /* _SDRAM_SOC64_H_ */
|
||||
Loading…
Reference in New Issue
Block a user