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https://github.com/brain-hackers/u-boot-brain
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mips: mscc: serval: Fix reset
In case the ddr training was failing, it couldn't reset, it was just hanging. Therefore reimplement it, so when ddr training is failing it would call _machine_restart, which power downs the DDR and does a force reset. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
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@ -401,23 +401,7 @@ static inline void sleep_100ns(u32 val)
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;
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}
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#if defined(CONFIG_SOC_OCELOT)
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static inline void hal_vcoreiii_ddr_reset_assert(void)
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{
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/* DDR has reset pin on GPIO 19 toggle Low-High to release */
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setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
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writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
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sleep_100ns(10000);
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}
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static inline void hal_vcoreiii_ddr_reset_release(void)
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{
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/* DDR has reset pin on GPIO 19 toggle Low-High to release */
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setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
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writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
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sleep_100ns(10000);
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}
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#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
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/*
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* DDR memory sanity checking failed, tally and do hard reset
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*
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@ -427,9 +411,11 @@ static inline void hal_vcoreiii_ddr_failed(void)
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{
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register u32 reset;
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#if defined(CONFIG_SOC_OCELOT)
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writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
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clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
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#endif
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/* We have to execute the reset function from cache. Indeed,
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* the reboot workaround in _machine_restart() will change the
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@ -452,6 +438,33 @@ static inline void hal_vcoreiii_ddr_failed(void)
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panic("DDR init failed\n");
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}
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#else /* JR2 || ServalT */
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static inline void hal_vcoreiii_ddr_failed(void)
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{
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writel(0, BASE_CFG + ICPU_RESET);
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writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
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panic("DDR init failed\n");
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}
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#endif
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#if defined(CONFIG_SOC_OCELOT)
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static inline void hal_vcoreiii_ddr_reset_assert(void)
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{
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/* DDR has reset pin on GPIO 19 toggle Low-High to release */
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setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
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writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
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sleep_100ns(10000);
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}
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static inline void hal_vcoreiii_ddr_reset_release(void)
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{
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/* DDR has reset pin on GPIO 19 toggle Low-High to release */
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setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
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writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
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sleep_100ns(10000);
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}
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#else /* JR2 || ServalT || Serval */
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static inline void hal_vcoreiii_ddr_reset_assert(void)
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{
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@ -463,14 +476,6 @@ static inline void hal_vcoreiii_ddr_reset_assert(void)
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writel(readl(BASE_CFG + ICPU_RESET) |
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ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
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}
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static inline void hal_vcoreiii_ddr_failed(void)
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{
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writel(0, BASE_CFG + ICPU_RESET);
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writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
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panic("DDR init failed\n");
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}
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#endif /* JR2 || ServalT || Serval */
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/*
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@ -36,7 +36,7 @@ void _machine_restart(void)
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/* Do global reset */
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writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
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for (i = 0; i < 1000; i++)
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for (i = 0; i < 2000; i++)
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;
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/* Power down DDR for clean DDR re-training */
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