From 7eace38d5418a6330f6d0918ed319ff605d3020b Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 9 Nov 2020 13:02:17 +0200 Subject: [PATCH 001/222] mmc: atmel-sdhci: fix the clk_enable call in case of no ops If the clock driver does not offer a clk_enable ops, then the system will return -ENOSYS. The clk_enable works with CCF (common clock framework). Some clocks in some cases (like the generic clock for some products: sama5d2) do not have the clk_enable primitive, and in this case probing of the driver will fail. This patch changes the behavior to return an error in case there is really an error, and not a missing primitive. If the clock driver does not have an enable primitive, most likely clocks are always enabled or enabled in the set_rate primitives. Fixes: 81f16438d4 ("mmc: atmel-sdhci: enable the required generic clock") Signed-off-by: Eugen Hristev Reviewed-by: Jaehoon Chung --- drivers/mmc/atmel_sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index f56ae63bc2..ca7a98bf1d 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -86,7 +86,8 @@ static int atmel_sdhci_probe(struct udevice *dev) return -EINVAL; ret = clk_enable(&clk); - if (ret) + /* return error only if the clock really has a clock enable func */ + if (ret && ret != -ENOSYS) return ret; ret = mmc_of_parse(dev, &plat->cfg); From 1a5c5b716cf1d41cc1eb0f115a44a72387242f86 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 9 Nov 2020 17:35:01 +0200 Subject: [PATCH 002/222] ARM: dts: at91: sam9x60: enable slewrate/high drive for sdhci0 pinout Align the pin setup for sdhci0 with linux kernel. This means to have slew rate enable and high drive strength. Signed-off-by: Eugen Hristev --- arch/arm/dts/sam9x60.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 7f3eae3f5d..007646fcb4 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -153,12 +153,18 @@ sdhci0 { pinctrl_sdhci0: sdhci0 { atmel,pins = - ; /* PA20 DAT3 periph A with pullup */ + ; /* PA20 DAT3 periph A with pullup */ }; }; }; From 62495e2cdb2e26f74281a0f7f0195b55e6d92abe Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 11 Nov 2020 13:15:08 +0200 Subject: [PATCH 003/222] ARM: at91: armv7: sama7g5 uses CCF clock driver SAMA7G5 uses CCF driver under drivers/clk/at91/ and not the custom older at91 clock.c driver. Remove it from the compilation list and adapt cpu.c arch_cpu_init() to avoid calling at91_clock_init() which is wrong anyway. Signed-off-by: Nicolas Ferre Reviewed-by: Claudiu Beznea --- arch/arm/mach-at91/armv7/Makefile | 7 +++---- arch/arm/mach-at91/armv7/cpu.c | 4 ++++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 55477560a8..b46b90b28e 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -6,11 +6,10 @@ # (C) Copyright 2013 # Bo Shen -obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o -obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o -obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o +obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o clock.o +obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o clock.o +obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o -obj-y += clock.o obj-y += cpu.o obj-y += reset.o ifeq ($(CONFIG_ATMEL_PIT_TIMER),) diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 8b7355042b..9b3753491e 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -24,7 +24,11 @@ int arch_cpu_init(void) { +#if defined(CONFIG_CLK_CCF) + return 0; +#else return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); +#endif } void arch_preboot_os(void) From 6c5f79d0cec40b4637883d13c4312f08afeca5d3 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Wed, 11 Nov 2020 18:46:03 +0200 Subject: [PATCH 004/222] ARM: mach-at91: fix timer.o compile condition The AT91 architecture now has two possible timer blocks, the old PIT timer and the new PIT64B. The timer.c file has an old non DM driver that works for platforms that do not use the ATMEL_PIT_TIMER DM-based driver. Update the Makefile to select this old driver in case neither of the ATMEL_PIT_TIMER and the MCHP_PIT64B_TIMER are selected. Suggested-by: Claudiu Beznea Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/armv7/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index b46b90b28e..f5b2665957 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -12,6 +12,9 @@ obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o obj-y += cpu.o obj-y += reset.o -ifeq ($(CONFIG_ATMEL_PIT_TIMER),) +ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) +ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y) +# old non-DM timer driver obj-y += timer.o endif +endif From de24bc7e0e3528f3d3c4731ab053a3e8d621ab7a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 28 Oct 2020 15:09:59 +0100 Subject: [PATCH 005/222] mips: start.S: Add Octeon boot header compatibility Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck Reviewed-by: Daniel Schwierzeck --- arch/mips/cpu/start.S | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index d0c412236d..335aafa6a8 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -74,9 +74,14 @@ .endm ENTRY(_start) - /* U-Boot entry point */ + /* + * U-Boot entry point. + * Do not add instructions to the branch delay slot! Some SoC's + * like Octeon might patch the final U-Boot binary at this location + * with additional boot headers. + */ b reset - mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing + nop #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) /* @@ -123,6 +128,7 @@ ENTRY(_start) #endif reset: + mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing #if __mips_isa_rev >= 6 mfc0 t0, CP0_CONFIG, 5 and t0, t0, MIPS_CONF5_VP From 8a138257dd4d6b7de27de9645a868dd56e6018f1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 28 Oct 2020 15:10:00 +0100 Subject: [PATCH 006/222] mips: octeon: Fix Octeon DDR driver to use the correct struct Don't use "platdata_auto_alloc_size" but "priv_auto_alloc_size" instead to auto allocate the private data struct, which is referenced via dev_get_priv() in this driver. This fixes an ugly bug detected while trying to boot via SPI NOR. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck --- drivers/ram/octeon/octeon_ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c index 757436b9d3..aaff9c3687 100644 --- a/drivers/ram/octeon/octeon_ddr.c +++ b/drivers/ram/octeon/octeon_ddr.c @@ -2724,5 +2724,5 @@ U_BOOT_DRIVER(octeon_ddr) = { .of_match = octeon_ids, .ops = &octeon_ops, .probe = octeon_ddr_probe, - .platdata_auto_alloc_size = sizeof(struct ddr_priv), + .priv_auto_alloc_size = sizeof(struct ddr_priv), }; From 8bab2c893c33b0245c51a71e91effe3547a73524 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 28 Oct 2020 15:10:01 +0100 Subject: [PATCH 007/222] mips: octeon: Report full DDR size in dram_init() to gd->ram_size With this patch, gd->ram_size now holds to full RAM size detected by the DDR init code. It introduces the get_effective_memsize() function to report the maximum usable RAM size in U-Boot to the system instead. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck Reviewed-by: Daniel Schwierzeck --- arch/mips/mach-octeon/dram.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 6dc08e19da..4679260f17 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -33,7 +33,7 @@ int dram_init(void) return ret; } - gd->ram_size = min_t(size_t, ram.size, UBOOT_RAM_SIZE_MAX); + gd->ram_size = ram.size; debug("SDRAM base=%lx, size=%lx\n", (unsigned long)ram.base, (unsigned long)ram.size); } else { @@ -72,6 +72,11 @@ void board_add_ram_info(int use_default) } } +phys_size_t get_effective_memsize(void) +{ + return UBOOT_RAM_SIZE_MAX; +} + ulong board_get_usable_ram_top(ulong total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { From b7eac19a3d91fae05250688ed4047c1a5d68dd42 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 28 Oct 2020 15:10:02 +0100 Subject: [PATCH 008/222] mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info() Using ram_get_info() is complicated and does not work after relocation. Now that gd->ram_size holds the full RAM size, let's use it instead and remove the ram_get_size logic completely. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck Reviewed-by: Daniel Schwierzeck --- arch/mips/mach-octeon/bootoctlinux.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/mips/mach-octeon/bootoctlinux.c b/arch/mips/mach-octeon/bootoctlinux.c index 75d7e83bd7..26136902f3 100644 --- a/arch/mips/mach-octeon/bootoctlinux.c +++ b/arch/mips/mach-octeon/bootoctlinux.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include @@ -370,8 +369,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, struct cvmx_coremask avail_coremask; int first_core; int core; - struct ram_info ram; - struct udevice *dev; const u64 *nmi_code; int num_dwords; u8 node_mask = 0x01; @@ -470,19 +467,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, */ cvmx_coremask_or(&coremask_to_run, &coremask_to_run, &core_mask); - /* Get RAM size */ - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - /* * Load kernel ELF image, or try binary if ELF is not detected. * This way the much smaller vmlinux.bin can also be started but @@ -498,7 +482,7 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, /* Init bootmem list for Linux kernel booting */ if (!cvmx_bootmem_phy_mem_list_init( - ram.size, OCTEON_RESERVED_LOW_MEM_SIZE, + gd->ram_size, OCTEON_RESERVED_LOW_MEM_SIZE, (void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_SPACE))) { printf("FATAL: Error initializing free memory list\n"); return 0; @@ -517,7 +501,8 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int argc, if (core == first_core) cvmx_bootinfo_array[core].flags |= BOOT_FLAG_INIT_CORE; - cvmx_bootinfo_array[core].dram_size = ram.size / (1024 * 1024); + cvmx_bootinfo_array[core].dram_size = gd->ram_size / + (1024 * 1024); cvmx_bootinfo_array[core].dclock_hz = gd->mem_clk * 1000000; cvmx_bootinfo_array[core].eclock_hz = gd->cpu_clk; From 540a2bcec1389a3a31c23b5275e73186be6102b2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 30 Nov 2020 13:14:23 +0100 Subject: [PATCH 009/222] mips: octeon: tools: Add update_octeon_header tool Add a tool to update or insert an Octeon specific header into the U-Boot image. This is needed e.g. for booting via SPI NOR, eMMC and NAND. While working on this, move enum cvmx_board_types_enum and cvmx_board_type_to_string() to cvmx-bootloader.h and remove the unreferenced (unsupported) board definition. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck Reviewed-by: Daniel Schwierzeck --- .../mach-octeon/include/mach/cvmx-bootinfo.h | 222 --------- .../include/mach/cvmx-bootloader.h | 172 +++++++ tools/.gitignore | 1 + tools/Makefile | 3 + tools/update_octeon_header.c | 456 ++++++++++++++++++ 5 files changed, 632 insertions(+), 222 deletions(-) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootloader.h create mode 100644 tools/update_octeon_header.c diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h index 337987178f..97438ff787 100644 --- a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h +++ b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h @@ -125,226 +125,4 @@ struct cvmx_bootinfo { #endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ -/* Type defines for board and chip types */ -enum cvmx_board_types_enum { - CVMX_BOARD_TYPE_NULL = 0, - CVMX_BOARD_TYPE_SIM = 1, - CVMX_BOARD_TYPE_EBT3000 = 2, - CVMX_BOARD_TYPE_KODAMA = 3, - CVMX_BOARD_TYPE_NIAGARA = 4, - CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */ - CVMX_BOARD_TYPE_THUNDER = 6, - CVMX_BOARD_TYPE_TRANTOR = 7, - CVMX_BOARD_TYPE_EBH3000 = 8, - CVMX_BOARD_TYPE_EBH3100 = 9, - CVMX_BOARD_TYPE_HIKARI = 10, - CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11, - CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12, - CVMX_BOARD_TYPE_KBP = 13, - /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */ - CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14, - CVMX_BOARD_TYPE_EBT5800 = 15, - CVMX_BOARD_TYPE_NICPRO2 = 16, - CVMX_BOARD_TYPE_EBH5600 = 17, - CVMX_BOARD_TYPE_EBH5601 = 18, - CVMX_BOARD_TYPE_EBH5200 = 19, - CVMX_BOARD_TYPE_BBGW_REF = 20, - CVMX_BOARD_TYPE_NIC_XLE_4G = 21, - CVMX_BOARD_TYPE_EBT5600 = 22, - CVMX_BOARD_TYPE_EBH5201 = 23, - CVMX_BOARD_TYPE_EBT5200 = 24, - CVMX_BOARD_TYPE_CB5600 = 25, - CVMX_BOARD_TYPE_CB5601 = 26, - CVMX_BOARD_TYPE_CB5200 = 27, - /* Special 'generic' board type, supports many boards */ - CVMX_BOARD_TYPE_GENERIC = 28, - CVMX_BOARD_TYPE_EBH5610 = 29, - CVMX_BOARD_TYPE_LANAI2_A = 30, - CVMX_BOARD_TYPE_LANAI2_U = 31, - CVMX_BOARD_TYPE_EBB5600 = 32, - CVMX_BOARD_TYPE_EBB6300 = 33, - CVMX_BOARD_TYPE_NIC_XLE_10G = 34, - CVMX_BOARD_TYPE_LANAI2_G = 35, - CVMX_BOARD_TYPE_EBT5810 = 36, - CVMX_BOARD_TYPE_NIC10E = 37, - CVMX_BOARD_TYPE_EP6300C = 38, - CVMX_BOARD_TYPE_EBB6800 = 39, - CVMX_BOARD_TYPE_NIC4E = 40, - CVMX_BOARD_TYPE_NIC2E = 41, - CVMX_BOARD_TYPE_EBB6600 = 42, - CVMX_BOARD_TYPE_REDWING = 43, - CVMX_BOARD_TYPE_NIC68_4 = 44, - CVMX_BOARD_TYPE_NIC10E_66 = 45, - CVMX_BOARD_TYPE_MAX, - - /* - * The range from CVMX_BOARD_TYPE_MAX to - * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future - * SDK use. - */ - - /* - * Set aside a range for customer boards. These numbers are managed - * by Cavium. - */ - CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000, - CVMX_BOARD_TYPE_CUST_WSX16 = 10001, - CVMX_BOARD_TYPE_CUST_NS0216 = 10002, - CVMX_BOARD_TYPE_CUST_NB5 = 10003, - CVMX_BOARD_TYPE_CUST_WMR500 = 10004, - CVMX_BOARD_TYPE_CUST_ITB101 = 10005, - CVMX_BOARD_TYPE_CUST_NTE102 = 10006, - CVMX_BOARD_TYPE_CUST_AGS103 = 10007, - CVMX_BOARD_TYPE_CUST_GST104 = 10008, - CVMX_BOARD_TYPE_CUST_GCT105 = 10009, - CVMX_BOARD_TYPE_CUST_AGS106 = 10010, - CVMX_BOARD_TYPE_CUST_SGM107 = 10011, - CVMX_BOARD_TYPE_CUST_GCT108 = 10012, - CVMX_BOARD_TYPE_CUST_AGS109 = 10013, - CVMX_BOARD_TYPE_CUST_GCT110 = 10014, - CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015, - CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016, - CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017, - CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018, - CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019, - CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020, - CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021, - CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, - - /* - * Set aside a range for customer private use. The SDK won't - * use any numbers in this range. - */ - CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, - CVMX_BOARD_TYPE_UBNT_E100 = 20002, - CVMX_BOARD_TYPE_CUST_DSR1000N = 20006, - CVMX_BOARD_TYPE_KONTRON_S1901 = 21901, - CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, - - /* The remaining range is reserved for future use. */ -}; - -enum cvmx_chip_types_enum { - CVMX_CHIP_TYPE_NULL = 0, - CVMX_CHIP_SIM_TYPE_DEPRECATED = 1, - CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2, - CVMX_CHIP_TYPE_MAX, -}; - -/* - * Compatibility alias for NAC38 name change, planned to be removed - * from SDK 1.7 - */ -#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38 - -/* Functions to return string based on type */ -#define ENUM_BRD_TYPE_CASE(x) \ - case x: \ - return(#x + 16) /* Skip CVMX_BOARD_TYPE_ */ - -static inline const char *cvmx_board_type_to_string(enum - cvmx_board_types_enum type) -{ - switch (type) { - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX); - - /* Customer boards listed here */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX); - - /* Customer private range */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901); - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX); - } - - return NULL; -} - -#define ENUM_CHIP_TYPE_CASE(x) \ - case x: \ - return(#x + 15) /* Skip CVMX_CHIP_TYPE */ - -static inline const char *cvmx_chip_type_to_string(enum - cvmx_chip_types_enum type) -{ - switch (type) { - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL); - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED); - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE); - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX); - } - - return "Unsupported Chip"; -} - #endif /* __CVMX_BOOTINFO_H__ */ diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootloader.h b/arch/mips/mach-octeon/include/mach/cvmx-bootloader.h new file mode 100644 index 0000000000..9abe021452 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-bootloader.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +/* + * Bootloader definitions that are shared with other programs + */ + +#ifndef __CVMX_BOOTLOADER__ +#define __CVMX_BOOTLOADER__ + +/* + * The bootloader_header_t structure defines the header that is present + * at the start of binary u-boot images. This header is used to locate + * the bootloader image in NAND, and also to allow verification of images + * for normal NOR booting. This structure is placed at the beginning of a + * bootloader binary image, and remains in the executable code. + */ +#define BOOTLOADER_HEADER_MAGIC 0x424f4f54 /* "BOOT" in ASCII */ + +#define BOOTLOADER_HEADER_COMMENT_LEN 64 +#define BOOTLOADER_HEADER_VERSION_LEN 64 +/* limited by the space to the next exception handler */ +#define BOOTLOADER_HEADER_MAX_SIZE 0x200 + +#define BOOTLOADER_HEADER_CURRENT_MAJOR_REV 1 +#define BOOTLOADER_HEADER_CURRENT_MINOR_REV 2 +/* + * Revision history + * 1.1 Initial released revision. (SDK 1.9) + * 1.2 TLB based relocatable image (SDK 2.0) + */ + +#ifndef __ASSEMBLY__ +struct bootloader_header { + uint32_t jump_instr; /* + * Jump to executable code following the + * header. This allows this header to be + * (and remain) part of the executable image) + */ + uint32_t nop_instr; /* Must be 0x0 */ + uint32_t magic; /* Magic number to identify header */ + uint32_t hcrc; /* CRC of all of header excluding this field */ + + uint16_t hlen; /* Length of header in bytes */ + uint16_t maj_rev; /* Major revision */ + uint16_t min_rev; /* Minor revision */ + uint16_t board_type; /* Board type that the image is for */ + + uint32_t dlen; /* Length of data (following header) in bytes */ + uint32_t dcrc; /* CRC of data */ + uint64_t address; /* Mips virtual address */ + uint32_t flags; + uint16_t image_type; /* Defined in bootloader_image_t enum */ + uint16_t resv0; /* pad */ + + uint32_t reserved1; + uint32_t reserved2; + uint32_t reserved3; + uint32_t reserved4; + + /* Optional, for descriptive purposes */ + char comment_string[BOOTLOADER_HEADER_COMMENT_LEN]; + /* Optional, for descriptive purposes */ + char version_string[BOOTLOADER_HEADER_VERSION_LEN]; +} __packed; + +/* Defines for flag field */ +#define BL_HEADER_FLAG_FAILSAFE 1 + +enum bootloader_image { + BL_HEADER_IMAGE_UNKNOWN = 0x0, + BL_HEADER_IMAGE_STAGE2, /* Binary bootloader stage2 image */ + BL_HEADER_IMAGE_STAGE3, /* Binary bootloader stage3 image */ + BL_HEADER_IMAGE_NOR, /* Binary bootloader for NOR boot */ + BL_HEADER_IMAGE_PCIBOOT, /* Binary bootloader for PCI boot */ + BL_HEADER_IMAGE_UBOOT_ENV, /* Environment for u-boot */ + /* Bootloader before U-Boot (stage 1/1.5) */ + BL_HEADER_IMAGE_PRE_UBOOT, + BL_HEADER_IMAGE_STAGE1, /* NOR stage 1 bootloader */ + BL_HEADER_IMAGE_MAX, + /* Range for customer private use. Will not be used by Cavium Inc. */ + BL_HEADER_IMAGE_CUST_RESERVED_MIN = 0x1000, + BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff +}; + +#endif /* __ASSEMBLY__ */ + +/* + * Maximum address searched for NAND boot images and environments. + * This is used by stage1 and stage2. + */ +#define MAX_NAND_SEARCH_ADDR 0x800000 + +/* Maximum address to look for start of normal bootloader */ +#define MAX_NOR_SEARCH_ADDR 0x400000 + +/* + * Defines for RAM based environment set by the host or the previous + * bootloader in a chain boot configuration. + */ + +#define U_BOOT_RAM_ENV_ADDR 0x1000 +#define U_BOOT_RAM_ENV_SIZE 0x1000 +#define U_BOOT_RAM_ENV_CRC_SIZE 0x4 +#define U_BOOT_RAM_ENV_ADDR_2 (U_BOOT_RAM_ENV_ADDR + U_BOOT_RAM_ENV_SIZE) +/* Address of environment in L2 cache if booted from cache */ +#define U_BOOT_CACHE_ENV_ADDR 0x000ff000 +/* Size of environment in L2 cache */ +#define U_BOOT_CACHE_ENV_SIZE 0x1000 + +/* Board numbers and names */ + +/* Type defines for board and chip types */ +enum cvmx_board_types_enum { + CVMX_BOARD_TYPE_NULL = 0, + CVMX_BOARD_TYPE_SIM = 1, + /* Special 'generic' board type, supports many boards */ + CVMX_BOARD_TYPE_GENERIC = 28, + CVMX_BOARD_TYPE_EBB7304 = 76, + CVMX_BOARD_TYPE_MAX, + /* NOTE: 256-257 are being used by a customer. */ + + /* + * The range from CVMX_BOARD_TYPE_MAX to + * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved + * for future SDK use. + */ + + /* + * Set aside a range for customer boards. These numbers are managed + * by Cavium. + */ + CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000, + CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, + + /* + * Set aside a range for customer private use. The SDK won't + * use any numbers in this range. + */ + CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, +}; + +/* Functions to return string based on type */ +/* Skip CVMX_BOARD_TYPE_ */ +#define ENUM_BRD_TYPE_CASE(x) case x: return(#x + 16) + +static inline const char +*cvmx_board_type_to_string(enum cvmx_board_types_enum type) +{ + switch (type) { + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB7304); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX); + + /* Customer boards listed here */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX); + + /* Customer private range */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN); + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX); + } + + return "Unsupported Board"; +} + +#endif /* __CVMX_BOOTLOADER__ */ diff --git a/tools/.gitignore b/tools/.gitignore index 82bdce2782..a021ea95cd 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -32,5 +32,6 @@ /spl_size_limit /sunxi-spl-image-builder /ubsha1 +/update_octeon_header /version.h /xway-swap-bytes diff --git a/tools/Makefile b/tools/Makefile index 51123fd929..253a6b9706 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -206,6 +206,9 @@ hostprogs-y += proftool hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela hostprogs-$(CONFIG_RISCV) += prelink-riscv +hostprogs-$(CONFIG_ARCH_OCTEON) += update_octeon_header +update_octeon_header-objs := update_octeon_header.o lib/crc32.o + hostprogs-y += fdtgrep fdtgrep-objs += $(LIBFDT_OBJS) common/fdt_region.o fdtgrep.o diff --git a/tools/update_octeon_header.c b/tools/update_octeon_header.c new file mode 100644 index 0000000000..8054ceec85 --- /dev/null +++ b/tools/update_octeon_header.c @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mkimage.h" + +#include "../arch/mips/mach-octeon/include/mach/cvmx-bootloader.h" + +#define BUF_SIZE (16 * 1024) +#define NAME_LEN 100 + +/* word offset */ +#define WOFFSETOF(type, elem) (offsetof(type, elem) / 4) + +static int stage2_flag; +static int stage_1_5_flag; +static int stage_1_flag; + +/* Getoptions variables must be global */ +static int failsafe_flag; +static int pciboot_flag; +static int env_flag; + +static const struct option long_options[] = { + /* These options set a flag. */ + {"failsafe", no_argument, &failsafe_flag, 1}, + {"pciboot", no_argument, &pciboot_flag, 1}, + {"nandstage2", no_argument, &stage2_flag, 1}, + {"spistage2", no_argument, &stage2_flag, 1}, + {"norstage2", no_argument, &stage2_flag, 1}, + {"stage2", no_argument, &stage2_flag, 1}, + {"stage1.5", no_argument, &stage_1_5_flag, 1}, + {"stage1", no_argument, &stage_1_flag, 1}, + {"environment", no_argument, &env_flag, 1}, + /* + * These options don't set a flag. + * We distinguish them by their indices. + */ + {"board", required_argument, 0, 0}, + {"text_base", required_argument, 0, 0}, + {0, 0, 0, 0} +}; + +static int lookup_board_type(char *board_name) +{ + int i; + int board_type = 0; + char *substr = NULL; + + /* Detect stage 2 bootloader boards */ + if (strcasestr(board_name, "_stage2")) { + printf("Stage 2 bootloader detected from substring %s in name %s\n", + "_stage2", board_name); + stage2_flag = 1; + } else { + printf("Stage 2 bootloader NOT detected from name \"%s\"\n", + board_name); + } + + if (strcasestr(board_name, "_stage1")) { + printf("Stage 1 bootloader detected from substring %s in name %s\n", + "_stage1", board_name); + stage_1_flag = 1; + } + + /* Generic is a special case since there are numerous sub-types */ + if (!strncasecmp("generic", board_name, strlen("generic"))) + return CVMX_BOARD_TYPE_GENERIC; + + /* + * If we're an eMMC stage 2 bootloader, cut off the _emmc_stage2 + * part of the name. + */ + substr = strcasestr(board_name, "_emmc_stage2"); + if (substr && (substr[strlen("_emmc_stage2")] == '\0')) { + /*return CVMX_BOARD_TYPE_GENERIC;*/ + + printf(" Converting board name %s to ", board_name); + *substr = '\0'; + printf("%s\n", board_name); + } + + /* + * If we're a NAND stage 2 bootloader, cut off the _nand_stage2 + * part of the name. + */ + substr = strcasestr(board_name, "_nand_stage2"); + if (substr && (substr[strlen("_nand_stage2")] == '\0')) { + /*return CVMX_BOARD_TYPE_GENERIC;*/ + + printf(" Converting board name %s to ", board_name); + *substr = '\0'; + printf("%s\n", board_name); + } + + /* + * If we're a SPI stage 2 bootloader, cut off the _spi_stage2 + * part of the name. + */ + substr = strcasestr(board_name, "_spi_stage2"); + if (substr && (substr[strlen("_spi_stage2")] == '\0')) { + printf(" Converting board name %s to ", board_name); + *substr = '\0'; + printf("%s\n", board_name); + } + + for (i = CVMX_BOARD_TYPE_NULL; i < CVMX_BOARD_TYPE_MAX; i++) + if (!strcasecmp(cvmx_board_type_to_string(i), board_name)) + board_type = i; + + for (i = CVMX_BOARD_TYPE_CUST_DEFINED_MIN; + i < CVMX_BOARD_TYPE_CUST_DEFINED_MAX; i++) + if (!strncasecmp(cvmx_board_type_to_string(i), board_name, + strlen(cvmx_board_type_to_string(i)))) + board_type = i; + + for (i = CVMX_BOARD_TYPE_CUST_PRIVATE_MIN; + i < CVMX_BOARD_TYPE_CUST_PRIVATE_MAX; i++) + if (!strncasecmp(cvmx_board_type_to_string(i), board_name, + strlen(cvmx_board_type_to_string(i)))) + board_type = i; + + return board_type; +} + +static void usage(void) +{ + printf("Usage: update_octeon_header [--failsafe] [--text_base=0xXXXXX]\n"); +} + +int main(int argc, char *argv[]) +{ + int fd; + uint8_t buf[BUF_SIZE]; + uint32_t data_crc = 0; + int len; + int data_len = 0; + struct bootloader_header header; + char filename[NAME_LEN]; + int i; + int option_index = 0; /* getopt_long stores the option index here. */ + char board_name[NAME_LEN] = { 0 }; + char tmp_board_name[NAME_LEN] = { 0 }; + int c; + int board_type = 0; + unsigned long long address = 0; + ssize_t ret; + const char *type_str = NULL; + int hdr_size = sizeof(struct bootloader_header); + + /* + * Compile time check, if the size of the bootloader_header structure + * has changed. + */ + compiletime_assert(sizeof(struct bootloader_header) == 192, + "Octeon bootloader header size changed (!= 192)!"); + + /* Bail out, if argument count is incorrect */ + if (argc < 3) { + usage(); + return -1; + } + + debug("header size is: %d bytes\n", hdr_size); + + /* Parse command line options using getopt_long */ + while (1) { + c = getopt_long(argc, argv, "h", long_options, &option_index); + + /* Detect the end of the options. */ + if (c == -1) + break; + + switch (c) { + /* All long options handled in case 0 */ + case 0: + /* If this option set a flag, do nothing else now. */ + if (long_options[option_index].flag != 0) + break; + debug("option(l) %s", long_options[option_index].name); + + if (!optarg) { + usage(); + return -1; + } + debug(" with arg %s\n", optarg); + + if (!strcmp(long_options[option_index].name, "board")) { + if (strlen(optarg) >= NAME_LEN) { + printf("strncpy() issue detected!"); + exit(-1); + } + strncpy(board_name, optarg, NAME_LEN); + + printf("Using user supplied board name: %s\n", + board_name); + } else if (!strcmp(long_options[option_index].name, + "text_base")) { + address = strtoull(optarg, NULL, 0); + printf("Address of image is: 0x%llx\n", + (unsigned long long)address); + if (!(address & 0xFFFFFFFFULL << 32)) { + if (address & 1 << 31) { + address |= 0xFFFFFFFFULL << 32; + printf("Converting address to 64 bit compatibility space: 0x%llx\n", + address); + } + } + } + break; + + case 'h': + case '?': + /* getopt_long already printed an error message. */ + usage(); + return -1; + + default: + abort(); + } + } + + if (optind < argc) { + /* + * We only support one argument - an optional bootloader + * file name + */ + if (argc - optind > 2) { + fprintf(stderr, "non-option ARGV-elements: "); + while (optind < argc) + fprintf(stderr, "%s ", argv[optind++]); + fprintf(stderr, "\n"); + + usage(); + return -1; + } + } + + if (strlen(argv[optind]) >= NAME_LEN) { + fprintf(stderr, "strncpy() issue detected!"); + exit(-1); + } + strncpy(filename, argv[optind], NAME_LEN); + + if (board_name[0] == '\0') { + if (strlen(argv[optind + 1]) >= NAME_LEN) { + fprintf(stderr, "strncpy() issue detected!"); + exit(-1); + } + strncpy(board_name, argv[optind + 1], NAME_LEN); + } + + if (strlen(board_name) >= NAME_LEN) { + fprintf(stderr, "strncpy() issue detected!"); + exit(-1); + } + strncpy(tmp_board_name, board_name, NAME_LEN); + + fd = open(filename, O_RDWR); + if (fd < 0) { + fprintf(stderr, "Unable to open file: %s\n", filename); + exit(-1); + } + + if (failsafe_flag) + printf("Setting failsafe flag\n"); + + if (strlen(board_name)) { + int offset = 0; + + printf("Supplied board name of: %s\n", board_name); + + if (strstr(board_name, "failsafe")) { + failsafe_flag = 1; + printf("Setting failsafe flag based on board name\n"); + } + /* Skip leading octeon_ if present. */ + if (!strncmp(board_name, "octeon_", 7)) + offset = 7; + + /* + * Check to see if 'failsafe' is in the name. If so, set the + * failsafe flag. Also, ignore extra trailing characters on + * passed parameter when comparing against board names. + * We actually use the configuration name from u-boot, so it + * may have some other variant names. Variants other than + * failsafe _must_ be passed to this program explicitly + */ + + board_type = lookup_board_type(board_name + offset); + if (!board_type) { + /* Retry with 'cust_' prefix to catch boards that are + * in the customer section (such as nb5) + */ + sprintf(tmp_board_name, "cust_%s", board_name + offset); + board_type = lookup_board_type(tmp_board_name); + } + + /* reset to original value */ + strncpy(tmp_board_name, board_name, NAME_LEN); + if (!board_type) { + /* + * Retry with 'cust_private_' prefix to catch boards + * that are in the customer private section + */ + sprintf(tmp_board_name, "cust_private_%s", + board_name + offset); + board_type = lookup_board_type(tmp_board_name); + } + + if (!board_type) { + fprintf(stderr, + "ERROR: unable to determine board type\n"); + exit(-1); + } + printf("Board type is: %d: %s\n", board_type, + cvmx_board_type_to_string(board_type)); + } else { + fprintf(stderr, "Board name must be specified!\n"); + exit(-1); + } + + /* + * Check to see if there is either an existing header, or that there + * are zero valued bytes where we want to put the header + */ + len = read(fd, buf, BUF_SIZE); + if (len > 0) { + /* + * Copy the header, as the first word (jump instruction, needs + * to remain the same. + */ + memcpy(&header, buf, hdr_size); + /* + * Check to see if we have zero bytes (excluding first 4, which + * are the jump instruction) + */ + for (i = 1; i < hdr_size / 4; i++) { + if (((uint32_t *)buf)[i]) { + fprintf(stderr, + "ERROR: non-zero word found %x in location %d required for header, aborting\n", + ((uint32_t *)buf)[i], i); + exit(-1); + } + } + printf("Zero bytes found in header location, adding header.\n"); + + } else { + fprintf(stderr, "Unable to read from file %s\n", filename); + exit(-1); + } + + /* Read data bytes and generate CRC */ + lseek(fd, hdr_size, SEEK_SET); + + while ((len = read(fd, buf, BUF_SIZE)) > 0) { + data_crc = crc32(data_crc, buf, len); + data_len += len; + } + printf("CRC of data: 0x%x, length: %d\n", data_crc, data_len); + + /* Now create the new header */ + header.magic = htonl(BOOTLOADER_HEADER_MAGIC); + header.maj_rev = htons(BOOTLOADER_HEADER_CURRENT_MAJOR_REV); + header.min_rev = htons(BOOTLOADER_HEADER_CURRENT_MINOR_REV); + header.dlen = htonl(data_len); + header.dcrc = htonl(data_crc); + header.board_type = htons(board_type); + header.address = address; + if (failsafe_flag) + header.flags |= htonl(BL_HEADER_FLAG_FAILSAFE); + + printf("Stage 2 flag is %sset\n", stage2_flag ? "" : "not "); + printf("Stage 1 flag is %sset\n", stage_1_flag ? "" : "not "); + if (pciboot_flag) + header.image_type = htons(BL_HEADER_IMAGE_PCIBOOT); + else if (stage2_flag) + header.image_type = htons(BL_HEADER_IMAGE_STAGE2); + else if (stage_1_flag) + header.image_type = htons(BL_HEADER_IMAGE_STAGE1); + else if (env_flag) + header.image_type = htons(BL_HEADER_IMAGE_UBOOT_ENV); + else if (stage_1_5_flag || stage_1_flag) + header.image_type = htons(BL_HEADER_IMAGE_PRE_UBOOT); + else + header.image_type = htons(BL_HEADER_IMAGE_NOR); + + switch (ntohs(header.image_type)) { + case BL_HEADER_IMAGE_UNKNOWN: + type_str = "Unknown"; + break; + case BL_HEADER_IMAGE_STAGE1: + type_str = "Stage 1"; + break; + case BL_HEADER_IMAGE_STAGE2: + type_str = "Stage 2"; + break; + case BL_HEADER_IMAGE_PRE_UBOOT: + type_str = "Pre-U-Boot"; + break; + case BL_HEADER_IMAGE_STAGE3: + type_str = "Stage 3"; + break; + case BL_HEADER_IMAGE_NOR: + type_str = "NOR"; + break; + case BL_HEADER_IMAGE_PCIBOOT: + type_str = "PCI Boot"; + break; + case BL_HEADER_IMAGE_UBOOT_ENV: + type_str = "U-Boot Environment"; + break; + default: + if (ntohs(header.image_type) >= BL_HEADER_IMAGE_CUST_RESERVED_MIN && + ntohs(header.image_type) <= BL_HEADER_IMAGE_CUST_RESERVED_MAX) + type_str = "Customer Reserved"; + else + type_str = "Unsupported"; + } + printf("Header image type: %s\n", type_str); + header.hlen = htons(hdr_size); + + /* Now compute header CRC over all of the header excluding the CRC */ + header.hcrc = crc32(0, (void *)&header, 12); + header.hcrc = htonl(crc32(header.hcrc, ((void *)&(header)) + 16, + hdr_size - 16)); + + /* Seek to beginning of file */ + lseek(fd, 0, SEEK_SET); + + /* Write header to file */ + ret = write(fd, &header, hdr_size); + if (ret < 0) + perror("write"); + + close(fd); + + printf("Header CRC: 0x%x\n", ntohl(header.hcrc)); + return 0; +} From f31e83d6cf44fccd25be48b67dd69aaff6c5e1f4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 9 Nov 2020 07:45:02 -0700 Subject: [PATCH 010/222] binman: Handle tool paths containing '~' correctly At present if CROSS_COMPILE contains a tilde, such as ~/.buildman-toolchains/gcc-7.3.0-nolibc/i386-linux/bin/i386-linux-gcc then binman gives a confusing error: binman: Error 255 running '~/..buildman-toolchains/gcc-7.3.0- ... Fix this by expanding it out before running the tool. Signed-off-by: Simon Glass --- tools/patman/tools.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/patman/tools.py b/tools/patman/tools.py index bbb157da87..05b1a1d4b0 100644 --- a/tools/patman/tools.py +++ b/tools/patman/tools.py @@ -333,6 +333,7 @@ def Run(name, *args, **kwargs): elif for_host: name, extra_args = GetHostCompileTool(name) args = tuple(extra_args) + args + name = os.path.expanduser(name) # Expand paths containing ~ all_args = (name,) + args result = command.RunPipe([all_args], capture=True, capture_stderr=True, env=env, raise_on_error=False, binary=binary) From 87d07ccc237a5bfd8be119af46140a4467122ca7 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Sat, 14 Nov 2020 01:01:42 +0300 Subject: [PATCH 011/222] sandbox: cros_ec: Basic support for EC_CMD_GET_NEXT_EVENT Since commit 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") the cros-ec-keyb driver has started using this command, but the sandbox EC emulator does not recognize it and continuously prints: ** Unknown EC command 0x67 This patch makes the sandbox driver send basic responses to the command, but the response only supports keyboard scans for now. The EC side of this command stores and returns events from a queue, and returns -EC_RES_UNAVAILABLE when there are no new events. This should be possible to implement by hooking into the SDL event queue (perhaps via sandbox_sdl_poll_events). Implementing that is a bit harder to do since the existing sandbox code is discarding pending keyboard events, then reading the current keyboard state. Since the EC emulator never explicitly fails to work on this command, the fallback to the older command will not trigger and will not be tested anymore. Fixes: 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") Reported-by: Heinrich Schuchardt Signed-off-by: Alper Nebi Yasak Tested-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- drivers/misc/cros_ec_sandbox.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index ff7f782742..d72db3eace 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -460,16 +460,14 @@ static int process_cmd(struct ec_state *ec, case EC_CMD_ENTERING_MODE: len = 0; break; - case EC_CMD_GET_NEXT_EVENT: - /* - * TODO: - * This driver emulates an old keyboard device supporting - * EC_CMD_MKBP_STATE. Current Chrome OS keyboards use - * EC_CMD_GET_NEXT_EVENT. Cf. - * "mkbp: Add support for buttons and switches" - * https://chromium.googlesource.com/chromiumos/platform/ec/+/87a071941b89e3f7fd3eb329b682e60b3fbd6c73 - */ - return -EC_RES_INVALID_COMMAND; + case EC_CMD_GET_NEXT_EVENT: { + struct ec_response_get_next_event *resp = resp_data; + + resp->event_type = EC_MKBP_EVENT_KEY_MATRIX; + cros_ec_keyscan(ec, resp->data.key_matrix); + len = sizeof(*resp); + break; + } default: printf(" ** Unknown EC command %#02x\n", req_hdr->command); return -1; From e7e7e1093b5243b058c420eaebf9373cf2d3f270 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 15 Nov 2020 21:22:53 +0100 Subject: [PATCH 012/222] dm: core: Fix incorrect flag check The test should be checking whether $flags are non-zero and $drv_flags contain specific flags, however these two sets of flags are separate, and the two tests should be logically ANDed, not bitwise ANDed. Signed-off-by: Marek Vasut Cc: Simon Glass Reviewed-by: Simon Glass --- drivers/core/device-remove.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index efdb0f2905..0924a575f5 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -152,7 +152,7 @@ void device_free(struct udevice *dev) static bool flags_remove(uint flags, uint drv_flags) { if ((flags & DM_REMOVE_NORMAL) || - (flags & (drv_flags & (DM_FLAG_ACTIVE_DMA | DM_FLAG_OS_PREPARE)))) + (flags && (drv_flags & (DM_FLAG_ACTIVE_DMA | DM_FLAG_OS_PREPARE)))) return true; return false; From a9e73d287bfd6bfc778c532128a20767ee305193 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 23 Nov 2020 09:08:19 +0100 Subject: [PATCH 013/222] binman: Remove additional backslash The origin patch didn't have this change and it was caused by manual resolution where additional backslash was added. Fixes: 6723b4c6ca7b ("binman: Call helper function binman_set_rom_offset() to fill offset") Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- lib/binman.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/binman.c b/lib/binman.c index d395b1cf70..f027d1b304 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -104,6 +104,6 @@ int binman_init(void) binman->image = node; } binman_set_rom_offset(ROM_OFFSET_NONE); -\ + return 0; } From 7e932ac790b3615a67a3c24041c194aa748c0d98 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Tue, 24 Nov 2020 18:07:52 +0100 Subject: [PATCH 014/222] fs/squashfs: sqfs_close/sqfs_read_sblk: set ctxt.sblk to NULL after free This will prevent a double free error if sqfs_close() is called twice. Signed-off-by: Richard Genoud --- fs/squashfs/sqfs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 608a2bb454..5de69ac3ca 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -49,6 +49,7 @@ static int sqfs_read_sblk(struct squashfs_super_block **sblk) if (sqfs_disk_read(0, 1, *sblk) != 1) { free(*sblk); + sblk = NULL; return -EINVAL; } @@ -1689,9 +1690,10 @@ free_strings: void sqfs_close(void) { - free(ctxt.sblk); - ctxt.cur_dev = NULL; sqfs_decompressor_cleanup(&ctxt); + free(ctxt.sblk); + ctxt.sblk = NULL; + ctxt.cur_dev = NULL; } void sqfs_closedir(struct fs_dir_stream *dirs) From c2ba01c082b4ab21e43bb15e1c3a7e19573d1133 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Wed, 25 Nov 2020 12:55:47 +0800 Subject: [PATCH 015/222] watchdog: sbsa: timeout should be in "millisecond" timeout should be in "millisecond" instead of second, so divided it by 1000 when calculate the load value. Signed-off-by: Zhao Qiang --- drivers/watchdog/sbsa_gwdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 2eae431ba6..96285c1a9b 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -61,7 +61,7 @@ static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags) * to half value of timeout. */ clk = get_tbclk(); - writel(clk / 2 * timeout, + writel(clk / (2 * 1000) * timeout, priv->reg_control + SBSA_GWDT_WOR); /* writing WCS will cause an explicit watchdog refresh */ From 3cbb026f17332b70d352ae3659179ca2b51f418c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 19 Nov 2020 21:26:20 +0200 Subject: [PATCH 016/222] linux/compat.h: Remove debug() from spin_lock_irqsave() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It seems nobody tested the debug() option in spin_lock_irqsave(). Currently, when #define DEBUG, it spoils the compiler with In file included from drivers/usb/dwc3/gadget.c:18: drivers/usb/dwc3/gadget.c: In function ‘dwc3_gadget_set_selfpowered’: include/log.h:235:4: warning: ‘flags’ is used uninitialized in this function [-Wuninitialized] 235 | printf(pr_fmt(fmt), ##args); \ | ^~~~~~ drivers/usb/dwc3/gadget.c:1347:17: note: ‘flags’ was declared here 1347 | unsigned long flags; | ^~~~~ and so on... Drop useless debug() call to make compiler happy. Fixes: 0c06db598367 ("lib, linux: move linux specific defines to linux/compat.h") Cc: Heiko Schocher Cc: Tom Rini Signed-off-by: Andy Shevchenko Reviewed-by: Oleksandr Andrushchenko Reviewed-by: Heiko Schocher --- include/linux/compat.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/compat.h b/include/linux/compat.h index 38549baa25..3d0acbd582 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -248,7 +248,7 @@ typedef int wait_queue_head_t; #define spin_lock_init(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0) +#define spin_lock_irqsave(lock, flags) do {} while (0) #define spin_unlock_irqrestore(lock, flags) do { flags = 0; } while (0) #define DEFINE_MUTEX(...) From d61e784136f16e9142ccc56b34f706b6e5002c5e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 29 Nov 2020 17:07:04 -0700 Subject: [PATCH 017/222] log: Fix comment for LOGC_BOOT This comment is in the wrong format, so reports an error with 'make htmldocs'. Fix it. Fixes: b73d61a5565 ("x86: zimage: Add a little more logging") Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- include/log.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/log.h b/include/log.h index 29f18a82dc..e53afa490e 100644 --- a/include/log.h +++ b/include/log.h @@ -96,8 +96,8 @@ enum log_category_t { LOGC_DEVRES, /** @LOGC_ACPI: Advanced Configuration and Power Interface (ACPI) */ LOGC_ACPI, - LOGC_BOOT, /* Related to boot process / boot image processing */ - + /** @LOGC_BOOT: Related to boot process / boot image processing */ + LOGC_BOOT, /** @LOGC_COUNT: Number of log categories */ LOGC_COUNT, /** @LOGC_END: Sentinel value for lists of log categories */ From d211e0418fed8adf4ffa7c31f067e367fb26a081 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 29 Nov 2020 17:07:05 -0700 Subject: [PATCH 018/222] global_data: Fix comment for dm_driver_rt This comment is in the wrong format, so reports an error with 'make htmldocs'. Fix it. Fixes: a294ead8d25 ("dm: Use an allocated array for run-time device info") Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- include/asm-generic/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 87d827d0f4..887b5c268d 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -196,7 +196,7 @@ struct global_data { */ struct list_head uclass_root; # if CONFIG_IS_ENABLED(OF_PLATDATA) - /** Dynamic info about the driver */ + /** @dm_driver_rt: Dynamic info about the driver */ struct driver_rt *dm_driver_rt; # endif #endif From 50efdf2c6ffe82a14cb7bf20a1abf55cff2ad135 Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Thu, 19 Nov 2020 09:37:19 +0900 Subject: [PATCH 019/222] common: update: fix an "unused" warning against update_flash() Since update_flash() is used only in update_tftp(), it should be guarded with appropriate config options. After the commit 3149e524fc1e, common/update.c will be built under either CONFIG_UDATE_TFTP, CONFIG_DFU_TFTP or CONFIG_UPDATE_FIT. Since CONFIG_UPDATE_FIT, hence fit_update(), doesn't rely on update_flash(), the compiler may cause an "unused" warning if CONFIG_UPDATE_FIT=y and CONFIG_UPDATE_TFTP=n and CONFIG_DFU_TFTP=n. This is, for example, the case for sandbox defconfig where EFI_CAPSULE_FIRMWARE_FIT is enabled for test purpose. Fixes: 3149e524fc1e ("common: update: add a generic interface for FIT image") Signed-off-by: AKASHI Takahiro --- common/update.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/update.c b/common/update.c index 808be0880d..a5879cb52c 100644 --- a/common/update.c +++ b/common/update.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_DFU_TFTP +#if defined(CONFIG_DFU_TFTP) || defined(CONFIG_UPDATE_TFTP) /* env variable holding the location of the update file */ #define UPDATE_FILE_ENV "updatefile" @@ -99,7 +99,6 @@ static int update_load(char *filename, ulong msec_max, int cnt_max, ulong addr) return rv; } -#endif /* CONFIG_DFU_TFTP */ #ifdef CONFIG_MTD_NOR_FLASH static int update_flash_protect(int prot, ulong addr_first, ulong addr_last) @@ -216,6 +215,7 @@ static int update_flash(ulong addr_source, ulong addr_first, ulong size) #endif return 0; } +#endif /* CONFIG_DFU_TFTP || CONFIG_UPDATE_TFTP */ static int update_fit_getparams(const void *fit, int noffset, ulong *addr, ulong *fladdr, ulong *size) @@ -233,7 +233,7 @@ static int update_fit_getparams(const void *fit, int noffset, ulong *addr, return 0; } -#ifdef CONFIG_DFU_TFTP +#if defined(CONFIG_DFU_TFTP) || defined(CONFIG_UPDATE_TFTP) int update_tftp(ulong addr, char *interface, char *devstring) { char *filename, *env_addr, *fit_image_name; @@ -340,7 +340,7 @@ next_node: return ret; } -#endif /* CONFIG_DFU_UPDATE */ +#endif /* CONFIG_DFU_UPDATE || CONFIG_UPDATE_TFTP */ #ifdef CONFIG_UPDATE_FIT /** From 9e925d0c47871c5e38e70334d6485c504c0552e0 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 30 Nov 2020 09:04:48 +0100 Subject: [PATCH 020/222] log: typos in include/log.h Correct several typos. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- include/log.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/log.h b/include/log.h index e53afa490e..6bce560648 100644 --- a/include/log.h +++ b/include/log.h @@ -29,7 +29,7 @@ enum log_level_t { LOGL_CRIT, /** @LOGL_ERR: Error that prevents something from working */ LOGL_ERR, - /** @LOGL_WARNING: Warning may prevent optimial operation */ + /** @LOGL_WARNING: Warning may prevent optimal operation */ LOGL_WARNING, /** @LOGL_NOTICE: Normal but significant condition, printf() */ LOGL_NOTICE, @@ -322,7 +322,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, * * Members marked as 'not allocated' are stored as pointers and the caller is * responsible for making sure that the data pointed to is not overwritten. - * Memebers marked as 'allocated' are allocated (e.g. via strdup()) by the log + * Members marked as 'allocated' are allocated (e.g. via strdup()) by the log * system. * * TODO(sjg@chromium.org): Compress this struct down a bit to reduce space, e.g. @@ -379,7 +379,7 @@ struct log_driver { * the run-time aspects of drivers (currently just a list of filters to apply * to records send to this device). * - * @next_filter_num: Seqence number of next filter filter added (0=no filters + * @next_filter_num: Sequence number of next filter filter added (0=no filters * yet). This increments with each new filter on the device, but never * decrements * @flags: Flags for this filter (enum log_device_flags) @@ -412,7 +412,7 @@ enum log_filter_flags { }; /** - * struct log_filter - criterial to filter out log messages + * struct log_filter - criteria to filter out log messages * * If a message matches all criteria, then it is allowed. If LOGFF_DENY is set, * then it is denied instead. From e405efcf4b62810bdd08974d2a928353dba8d6ae Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 30 Nov 2020 09:08:12 +0100 Subject: [PATCH 021/222] MAINTAINERS: assign include/log.h include/log.h belongs to LOGGING. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 874cf2c0e5..2625fc629c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -758,6 +758,7 @@ T: git https://gitlab.denx.de/u-boot/u-boot.git F: common/log* F: cmd/log.c F: doc/develop/logging.rst +F: include/log.h F: lib/getopt.c F: test/log/ F: test/py/tests/test_log.py From 382985675c7576d05969f61edbe14fb0a5ef1f0a Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 1 Dec 2020 00:12:39 +0100 Subject: [PATCH 022/222] mtd: spi-nor-ids: add Winbond W25Q32JW-IM flash The Kontron SMARC-sAL28 board uses that flash. This is the same change as in the linux commit f3418718c0ec ("mtd: spi-nor: Add support for w25q32jwm"). Signed-off-by: Michael Walle Reported-by: Leo Krueger --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index bc9d4f7e9f..09e8196048 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -278,6 +278,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, From 4cb8a10f7e6f50a8c71e41df1207264266bfa305 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Nov 2020 10:15:37 +0100 Subject: [PATCH 023/222] remove obsolete option CONFIG_JFFS2_CMDLINE This option is obsolete since 2009 and can be removed globally. CC: Stefan Roese Signed-off-by: Holger Brunck Reviewed-by: Stefan Roese --- include/configs/ethernut5.h | 1 - include/configs/km/km-powerpc.h | 2 -- include/configs/kmp204x.h | 3 --- include/configs/pm9263.h | 1 - include/configs/stmark2.h | 1 - scripts/config_whitelist.txt | 1 - 6 files changed, 9 deletions(-) diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index b513b4bc68..ca249d9d2b 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -62,7 +62,6 @@ /* JFFS2 */ #ifdef CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_NAND #endif diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 7bfe12fecb..3be926c103 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -9,8 +9,6 @@ /* Do boardspecific init for all boards */ -#define CONFIG_JFFS2_CMDLINE - /* EEprom support 24C08, 24C16, 24C64 */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index ec1254e747..d1eb7b574b 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -337,9 +337,6 @@ int get_scl(void); * additionnal command line configuration. */ -/* we don't need flash support */ -#undef CONFIG_JFFS2_CMDLINE - /* * For booting Linux, the board info and command line data * have to be in the first 64 MB of memory, since this is diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 0ed4b1aaa2..6c882b6ff9 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -190,7 +190,6 @@ #endif -#define CONFIG_JFFS2_CMDLINE 1 #define CONFIG_JFFS2_NAND 1 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index d9a2f75e73..da162cbb11 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 /* spi not partitions */ -#define CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nor0" /* Timer */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8b4fcba395..c0339dcc00 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -848,7 +848,6 @@ CONFIG_IRAM_STACK CONFIG_IRAM_TOP CONFIG_IRDA_BASE CONFIG_IS_ENABLED -CONFIG_JFFS2_CMDLINE CONFIG_JFFS2_DEV CONFIG_JFFS2_LZO CONFIG_JFFS2_NAND From a6cd384b9c37596ca9035f26922dd65991ddcb85 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Nov 2020 10:28:51 +0100 Subject: [PATCH 024/222] km/common: remove CONFIG_MTD_CONCAT This was used for a board which is not supproted anymore and can therefore be dropped. CC: Stefan Roese Signed-off-by: Holger Brunck Reviewed-by: Stefan Roese --- include/configs/km/keymile-common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 851b13e063..ad0041d8a9 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -32,9 +32,6 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE -/* UBI Support for all Keymile boards */ -#define CONFIG_MTD_CONCAT - #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ "actual_bank=0\0" From bfe682e9ddbd8d13903f5e51452d8bff07706f85 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:52 +0200 Subject: [PATCH 025/222] apalis/colibri_t30: add comment about tristate and input vs. output pinmuxing Add pinmuxing comment stating that TRISTATE means the output driver is tri-stated and INPUT means the input driver is enabled vs. OUTPUT where it is disabled. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- board/toradex/apalis_t30/pinmux-config-apalis_t30.h | 2 ++ board/toradex/colibri_t30/pinmux-config-colibri_t30.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h index 49c2df7ab2..8d6696aaad 100644 --- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -11,7 +11,9 @@ .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ +/* TRISTATE here means output driver is tri-stated */ \ .tristate = PMUX_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_DEFAULT, \ .od = PMUX_PIN_OD_DEFAULT, \ diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index bdbbf5e49a..6181b506a4 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -11,7 +11,9 @@ .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ +/* TRISTATE here means output driver is tri-stated */ \ .tristate = PMUX_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_DEFAULT, \ .od = PMUX_PIN_OD_DEFAULT, \ From a6094e1b0a8e1707ad43c5911b8cf902d98951a4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:53 +0200 Subject: [PATCH 026/222] colibri_t30: fix spi1 and uart2/3 resp. uartb/c pinmuxing Fix SPI1 and UART2/3 resp. UARTB/C pinmuxing. Note: The former was illegally muxing multiple SoC balls onto the same internal SoC signal which caused rather strange behaviour regarding the RS232 serial transceiver ForceOFF# pins as available on Iris. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- .../colibri_t30/pinmux-config-colibri_t30.h | 23 ++++++++++--------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index 6181b506a4..c583583b3f 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -181,13 +181,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), @@ -270,10 +271,10 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, INPUT), /* LAN_RESET */ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT), From 4ba4bd0f87b48d34b5ca68968037fc3aa7658cb7 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:54 +0200 Subject: [PATCH 027/222] apalis/colibri_t30: avoid uart input from floating pins Avoid UART input from floating RX pins on UARTB and UARTC (Colibri T30) and UARTB, UARTC and UARTD (Apalis T30). Note: Floating pins may cause spurious break conditions potentially interrupting U-Boot's autoboot. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- board/toradex/apalis_t30/pinmux-config-apalis_t30.h | 9 ++++++--- board/toradex/colibri_t30/pinmux-config-colibri_t30.h | 7 ++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h index 8d6696aaad..3a2cf4606e 100644 --- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -120,7 +120,8 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), + /* UARTD RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), @@ -189,12 +190,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + /* UARTB RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + /* UARTC RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT), diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index c583583b3f..5ac1a6da97 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -180,7 +180,8 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + /* UARTC RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT), @@ -207,11 +208,11 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + /* UARTB RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, UP, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT), - /* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT), DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), From 8e487f38cc6408d0045194eec2271695da31b321 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:55 +0200 Subject: [PATCH 028/222] apalis/colibri_t30: add note about colibri vs. nvidia uart mapping The following mapping is applicable for Apalis T30: Apalis UART1: NVIDIA UARTA Apalis UART2: NVIDIA UARTD Apalis UART3: NVIDIA UARTB Apalis UART4: NVIDIA UARTC The following mapping is applicable for Colibri T30: Colibri UART-A: NVIDIA UARTA Colibri UART-B: NVIDIA UARTD Colibri UART-C: NVIDIA UARTB Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- include/configs/apalis_t30.h | 9 ++++++++- include/configs/colibri_t30.h | 8 +++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index bf0aefda2a..f0c003d2fe 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -12,7 +12,14 @@ #include "tegra30-common.h" -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Apalis UART1: NVIDIA UARTA + * Apalis UART2: NVIDIA UARTD + * Apalis UART3: NVIDIA UARTB + * Apalis UART4: NVIDIA UARTC + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index fa0fa93b03..94802a66f7 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -14,7 +14,13 @@ /* High-level configuration options */ -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Colibri UART-A: NVIDIA UARTA + * Colibri UART-B: NVIDIA UARTD + * Colibri UART-C: NVIDIA UARTB + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE From 1b56cd868e3c691625aa9bce2f475fcd4cf0405a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:56 +0200 Subject: [PATCH 029/222] colibri_t30: disable rs232 serial transceiver forceoff pins Use gpio_early_init_uart() function to disable RS232 serial transceiver ForceOFF# pins on Iris. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- board/toradex/colibri_t30/colibri_t30.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index c5562f6d57..20cbb75a36 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -57,6 +57,17 @@ void pinmux_init(void) ARRAY_SIZE(colibri_t30_padctrl)); } +/* + * Disable RS232 serial transceiver ForceOFF# pins on Iris + */ +void gpio_early_init_uart(void) +{ + gpio_request(TEGRA_GPIO(X, 6), "Force OFF# X13"); + gpio_direction_output(TEGRA_GPIO(X, 6), 1); + gpio_request(TEGRA_GPIO(X, 7), "Force OFF# X14"); + gpio_direction_output(TEGRA_GPIO(X, 7), 1); +} + /* * Enable AX88772B USB to LAN controller */ From 632fb978a513e22e4cbc8410156a185716216649 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 2 Apr 2020 00:28:54 +0100 Subject: [PATCH 030/222] arm: tegra: define fdtfile option for distro boot For booting via UEFI we need to define the fdtfile option so bootefi has the option to load a fdtfile from disk. For arm64 the kernel dtb is located in a vendor directory so we define that as nvidia for that architecture. Signed-off-by: Peter Robinson Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 6 ++++++ include/configs/tegra114-common.h | 1 + include/configs/tegra124-common.h | 1 + include/configs/tegra186-common.h | 1 + include/configs/tegra20-common.h | 1 + include/configs/tegra210-common.h | 1 + include/configs/tegra30-common.h | 1 + 7 files changed, 12 insertions(+) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2b968917d3..432eceaf35 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -49,6 +49,12 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#ifdef CONFIG_ARM64 +#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index d3a7045697..9d751b6740 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -50,6 +50,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 522993b958..0eb8f92809 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -52,6 +52,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index b4936cc731..5c3ad35c76 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -49,6 +49,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 1e31d82574..fdd8996955 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -51,6 +51,7 @@ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x03000000\0" \ "ramdisk_addr_r=0x03100000\0" diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1b8e94b60c..2226effe16 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,6 +46,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83200000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 54bc6756ab..6c5dc24b26 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -47,6 +47,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" From fe669925cb4276b881a0b444e660378293585093 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 2 Apr 2020 00:28:55 +0100 Subject: [PATCH 031/222] arm: tegra: add options for BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 Upstream linux DT naming doesn't align with the U-Boot DT, which may not always be the case so this allows using BOOTENV_EFI_SET_FDTFILE_FALLBACK where it might be appropriate for some boards. Signed-off-by: Peter Robinson Signed-off-by: Tom Warren --- include/config_distro_bootcmd.h | 2 ++ include/configs/tegra186-common.h | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index ff29ef5a90..82a3a365c5 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -118,8 +118,10 @@ "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \ "fi; " #else +#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK #define BOOTENV_EFI_SET_FDTFILE_FALLBACK #endif +#endif #define BOOTENV_SHARED_EFI \ diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index 5c3ad35c76..d5f21e0907 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -20,6 +20,12 @@ /* Generic Interrupt Controller */ #define CONFIG_GICV2 +#undef FDTFILE +#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ + "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \ + "fi; " + /* * Memory layout for where various images get loaded by boot scripts: * @@ -49,7 +55,6 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" From 4f5128ff899d0cb13a7b010f6dbffd0aba71bb25 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 18 Jun 2020 09:41:34 +0200 Subject: [PATCH 032/222] configs: cei-tk1-som: remove CONFIG_ARMV7_PSCI in include file Activate ARCH_SUPPORT_PSCI as other TEGRA124 target and remove CONFIG_ARMV7_PSCI and CONFIG_ARMV7_PSCI_NR_CPUS in configs file as they are migrated in Kconfig. Select CONFIG_ARMV7_PSCI_0_1 (the first PSCI version), because CONFIG_ARMV7_PSCI_0_2 and CONFIG_ARMV7_PSCI_1_0 are not activated in this product. Hi, This patch depend on the previous serie [1]. I don't test this patch on real hardware but after this patch the size of the binary don't change. In .config we have: CONFIG_ARCH_SUPPORT_PSCI=y CONFIG_ARMV7_PSCI=y # CONFIG_ARMV7_PSCI_1_0 is not set # CONFIG_ARMV7_PSCI_0_2 is not set CONFIG_ARMV7_PSCI_0_1=y CONFIG_ARMV7_PSCI_NR_CPUS=4 In u-boot.cfg, this patch only add the 2 lines #define CONFIG_ARCH_SUPPORT_PSCI 1 #define CONFIG_ARMV7_PSCI_0_1 1 [1] "Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig" http://patchwork.ozlabs.org/project/uboot/list/?series=184029 Regards Patrick END Signed-off-by: Patrick Delaunay Reviewed-by: Peter Chubb Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra124/Kconfig | 1 + configs/cei-tk1-som_defconfig | 1 + include/configs/cei-tk1-som.h | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 6fa31ea0a1..fb016aa46c 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -19,6 +19,7 @@ config TARGET_JETSON_TK1 config TARGET_CEI_TK1_SOM bool "Colorado Engineering Inc Tegra124 TK1-som board" + select ARCH_SUPPORT_PSCI select BOARD_LATE_INIT select CPU_V7_HAS_NONSEC if !SPL_BUILD select CPU_V7_HAS_VIRT if !SPL_BUILD diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index a1b494ec0f..987e3ac8e9 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_ARMV7_PSCI_0_1=y CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index dd3bdacc2c..2c406d3186 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -28,8 +28,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define CONFIG_ARMV7_PSCI 1 -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 From 3cf02f5ffa4f85c3934495cddae1f39bc61314b6 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Nov 2020 20:46:02 +0100 Subject: [PATCH 033/222] imx6: remove not longer supported aristainetos boards Removed aristainetos2, 2b, 2b-csl. This boards have been recalled and destroyed. Adapt board code to remove stuff not needed anymore. Fix checkpatch warning, remove fdt_high and initrd_high from default environment. Signed-off-by: Heiko Schocher zu remove --- arch/arm/dts/Makefile | 7 - .../dts/imx6dl-aristainetos2_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2_4.dts | 51 --- arch/arm/dts/imx6dl-aristainetos2_4.dtsi | 84 ----- .../dts/imx6dl-aristainetos2_7-u-boot.dtsi | 19 - arch/arm/dts/imx6dl-aristainetos2_7.dts | 16 - arch/arm/dts/imx6dl-aristainetos2_7.dtsi | 11 +- .../dts/imx6dl-aristainetos2b_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2b_4.dts | 50 --- .../dts/imx6dl-aristainetos2b_7-u-boot.dtsi | 19 - arch/arm/dts/imx6dl-aristainetos2b_7.dts | 16 - .../imx6dl-aristainetos2b_csl_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts | 50 --- .../imx6dl-aristainetos2b_csl_7-u-boot.dtsi | 19 - arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts | 16 - .../dts/imx6dl-aristainetos2c_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2c_4.dts | 50 --- arch/arm/dts/imx6dl-aristainetos2c_7.dts | 2 +- .../arm/dts/imx6qdl-aristainetos2-common.dtsi | 23 +- .../arm/dts/imx6qdl-aristainetos2-u-boot.dtsi | 22 -- arch/arm/dts/imx6qdl-aristainetos2.dtsi | 244 ------------- .../dts/imx6qdl-aristainetos2b-u-boot.dtsi | 77 ----- arch/arm/dts/imx6qdl-aristainetos2b.dtsi | 266 -------------- .../imx6qdl-aristainetos2b_csl-u-boot.dtsi | 77 ----- arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi | 248 ------------- arch/arm/dts/imx6qdl-aristainetos2c.dtsi | 12 +- arch/arm/mach-imx/mx6/Kconfig | 33 -- board/aristainetos/Kconfig | 36 -- board/aristainetos/MAINTAINERS | 29 +- board/aristainetos/aristainetos.c | 263 +++----------- board/aristainetos/common/Kconfig | 5 +- configs/aristainetos2_defconfig | 121 ------- configs/aristainetos2b_defconfig | 115 ------ configs/aristainetos2bcsl_defconfig | 115 ------ configs/aristainetos2c_defconfig | 6 +- include/configs/aristainetos2.h | 326 +++++++++--------- 36 files changed, 249 insertions(+), 2231 deletions(-) delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4.dts delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi delete mode 100644 configs/aristainetos2_defconfig delete mode 100644 configs/aristainetos2b_defconfig delete mode 100644 configs/aristainetos2bcsl_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e2e8a5fb7a..457ccfe08f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -643,13 +643,6 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ - imx6dl-aristainetos2_4.dtb \ - imx6dl-aristainetos2_7.dtb \ - imx6dl-aristainetos2b_4.dtb \ - imx6dl-aristainetos2b_7.dtb \ - imx6dl-aristainetos2b_csl_4.dtb \ - imx6dl-aristainetos2b_csl_7.dtb \ - imx6dl-aristainetos2c_4.dtb \ imx6dl-aristainetos2c_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-cubox-i.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi deleted file mode 100644 index ac7052c7b7..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dts b/arch/arm/dts/imx6dl-aristainetos2_4.dts deleted file mode 100644 index 0157e244ae..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * parts for 4.3 inch LG display on spi1 port0 - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi deleted file mode 100644 index be4601b4b2..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * parts for 4.3 inch LG display on the parallel port and atmel maxtouch - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl.dtsi" - -/ { - display0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi deleted file mode 100644 index 25bc562064..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dts b/arch/arm/dts/imx6dl-aristainetos2_7.dts deleted file mode 100644 index 0d1e83cb68..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi index 52d6a517a7..ec633b8ed1 100644 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0) /* * support for the imx6 based aristainetos2 board - * parts for 7 inch LG display connected to the LVDS port and atmel maxtouch + * parts for 7 inch LG display connected to the LVDS port * * Copyright (C) 2019 Heiko Schocher * Copyright (C) 2015 Heiko Schocher @@ -26,15 +26,6 @@ }; }; -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - &ldb { status = "okay"; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi deleted file mode 100644 index ee02df39c1..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_4.dts deleted file mode 100644 index a48a25c119..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2b.dtsi" - -/ { - model = "aristainetos2b i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi deleted file mode 100644 index 0cb4f1974b..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_7.dts deleted file mode 100644 index f1496cbfdd..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2b.dtsi" - -/ { - model = "aristainetos2b i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi deleted file mode 100644 index 654ac122a1..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts deleted file mode 100644 index bfbb799f20..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b csl board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2b_csl.dtsi" - -/ { - model = "aristainetos2b csl i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi deleted file mode 100644 index 70d195ecbf..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts deleted file mode 100644 index ecf767da6c..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2b_csl.dtsi" - -/ { - model = "aristainetos2b csl i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi deleted file mode 100644 index 052d51852b..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4.dts b/arch/arm/dts/imx6dl-aristainetos2c_4.dts deleted file mode 100644 index 142b108ace..0000000000 --- a/arch/arm/dts/imx6dl-aristainetos2c_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2c board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2c.dtsi" - -/ { - model = "aristainetos2c i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts index 35435e1c10..00eec82bf4 100644 --- a/arch/arm/dts/imx6dl-aristainetos2c_7.dts +++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts @@ -11,6 +11,6 @@ #include "imx6qdl-aristainetos2c.dtsi" / { - model = "aristainetos2c i.MX6 Dual Lite Board 7"; + model = "aristainetos2c+2d i.MX6 Dual Lite Boards 7"; compatible = "fsl,imx6dl"; }; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi index 2aa531b1ab..570143694e 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0) /* - * support for the imx6 based aristainetos2 board + * support for the imx6 based aristainetos2 boards * parts common to all versions * * Copyright (C) 2019 Heiko Schocher @@ -13,6 +13,8 @@ / { aliases { eeprom0 = &i2c_eeprom0; + eeprom1 = &i2c_eeprom1; + eeprom2 = &i2c_eeprom2; pmic0 = &i2c_pmic0; }; @@ -250,6 +252,12 @@ }; }; + i2c_eeprom2: eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + rtc@68 { compatible = "st,m41t11"; reg = <0x68>; @@ -274,6 +282,19 @@ }; }; +&gpio2 { + tpm_pp { + gpio-hog; + output-low; + gpios = <17 GPIO_ACTIVE_HIGH>; + }; + tpm_reset { + gpio-hog; + output-high; + gpios = <18 GPIO_ACTIVE_HIGH>; + }; +}; + &gpio6 { spi_bus_ena { gpio-hog; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi index c713efd84c..3063f01d70 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -50,28 +50,6 @@ }; }; -&iomuxc { - pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>; - u-boot,dm-pre-reloc; - - pinctrl_gpio_fix: gpiofixgrp { - /* - * usdhc2 has a levelshifter on the carrier board Rev. DV1, - * that will automatically detect the driving direction. - * During initialisation this isn't working correctly, - * which causes DAT3 to be driven low towards the SD-card. - * This causes a SD-card enetring the SPI-Mode - * and therefore getting inaccessible until next power cycle. - * As workaround we drive the DAT3 line as GPIO and set it high. - * This makes usdhc2 unusable in u-boot, but works for the - * initialisation in Linux - */ - fsl,pins = < - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x20000 - >; - }; -}; - &gpio1 { usdhc_fix { gpio-hog; diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi deleted file mode 100644 index 788e13edad..0000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -#include -#include - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - }; -}; - -&gpio7 { - sd2_driver_ena { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - /* SD1 write protect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - /* SD2 level shifter output enable */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - /* SD2 card detect input */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - /* SD2 write protect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi deleted file mode 100644 index 88826a2634..0000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -/ { - chosen { - u-boot,dm-pre-reloc; - stdout-path = &uart2; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - }; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_gpio { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart2 { - u-boot,dm-pre-reloc; -}; - -&iomuxc { - u-boot,dm-pre-reloc; -}; - -&aips2 { - u-boot,dm-pre-reloc; -}; - -&backlight { - pwms = <&pwm1 0 300000>; - default-brightness-level = <2>; -}; - -/* - * allow switching write protect / reset pin by gpio, - * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot - */ -&gpio2 { - u-boot,dm-pre-reloc; - - wp_spi_nor { - gpio-hog; - output-high; - gpios = <15 GPIO_ACTIVE_HIGH>; - }; - - reset_spi_nor { - gpio-hog; - output-high; - gpios = <28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio4 { - u-boot,dm-pre-reloc; -}; - -&ecspi1 { - u-boot,dm-pre-reloc; -}; - -&flash { - u-boot,dm-pre-reloc; -}; - -&pinctrl_ecspi1 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi deleted file mode 100644 index 7d92ea2af7..0000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -#include -#include - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; -}; - -&i2c1 { - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; -}; - -&gpio7 { - sd2_driver_ena { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - /* - * comment out this line to make the WiFi Eval-Module work in - * SD-Slot2, and add line: - * broken-cd; - * causes 6% CPU load if no WiFi module installed (polling) - */ - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SS0# */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - /* SS1# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 - /* SS2# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 - /* WP pin NOR Flash */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 - /* Flash nReset */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - /* make sure pin is GPIO and not ENET_REF_CLK */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 - /* SD2 level shifter output enable / SD2 Reset# */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - /* SD1 write protect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - /* SD2 card detect input */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - /* SD2 write protect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi deleted file mode 100644 index 8c2ed70075..0000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -/ { - chosen { - u-boot,dm-pre-reloc; - stdout-path = &uart1; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - }; -}; - -&uart1 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_gpio { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart1 { - u-boot,dm-pre-reloc; -}; - -&iomuxc { - u-boot,dm-pre-reloc; -}; - -&aips1 { - u-boot,dm-pre-reloc; -}; - -&backlight { - pwms = <&pwm1 0 300000>; - default-brightness-level = <2>; -}; - -/* - * allow switching write protect / reset pin by gpio, - * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot - */ -&gpio2 { - u-boot,dm-pre-reloc; - - wp_spi_nor { - gpio-hog; - output-high; - gpios = <15 GPIO_ACTIVE_HIGH>; - }; - - reset_spi_nor { - gpio-hog; - output-high; - gpios = <28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio4 { - u-boot,dm-pre-reloc; -}; - -&ecspi1 { - u-boot,dm-pre-reloc; -}; - -&flash { - u-boot,dm-pre-reloc; -}; - -&pinctrl_ecspi1 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi deleted file mode 100644 index fa4dadefb6..0000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b-csl board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -#include -#include - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - }; - - LED_blue_2 { - label = "led_blue2"; - gpios = <&expander 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_green_2 { - label = "led_green2"; - gpios = <&expander 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_red_2 { - label = "led_red2"; - gpios = <&expander 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_yellow_2 { - label = "led_yellow2"; - gpios = <&expander 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; -}; - -&i2c1 { - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; -}; - -&gpio7 { - wlan_reset { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SS0# */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - /* SS1# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 - /* SS2# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 - /* WP pin NOR Flash */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 - /* Flash nReset */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - /* make sure pin is GPIO and not ENET_REF_CLK */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 - /* WLAN Module Reset# */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi index ba13d55f41..70c0177d29 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0) /* - * support for the imx6 based aristainetos2c board + * support for the imx6 based aristainetos2c+2d boards * * Copyright (C) 2019 Heiko Schocher * Copyright (C) 2015 Heiko Schocher @@ -79,6 +79,14 @@ }; }; +&gpio7 { + eMMC_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; @@ -172,6 +180,8 @@ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 /* TPM Reset */ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + /* eMMC Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 >; }; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 0646b7369c..9d6c344064 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -128,39 +128,6 @@ config TARGET_APALIS_IMX6 imply CMD_DM imply CMD_SATA -config TARGET_ARISTAINETOS2 - bool "aristainetos2" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - -config TARGET_ARISTAINETOS2B - bool "Support aristainetos2-revB" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - -config TARGET_ARISTAINETOS2BCSL - bool "Support aristainetos2-revB CSL" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - config TARGET_ARISTAINETOS2C bool "Support aristainetos2-revC" depends on MX6DL diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 2ad3dbd56c..d67002503d 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -1,39 +1,3 @@ -if TARGET_ARISTAINETOS2 - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 2 - -endif - -if TARGET_ARISTAINETOS2B - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 3 - -endif - -if TARGET_ARISTAINETOS2BCSL - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 4 - -endif - if TARGET_ARISTAINETOS2C source "board/aristainetos/common/Kconfig" diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index b4ca7abb9c..1c3fb3aeb1 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -3,34 +3,11 @@ M: Heiko Schocher S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h -F: configs/aristainetos2_defconfig -F: configs/aristainetos2b_defconfig -F: configs/aristainetos2bcsl_defconfig F: configs/aristainetos2c_defconfig -F: arch/arm/dts/imx6qdl-aristainetos2.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_7.dts -F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_4.dts -F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_4.dts -F: arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_7.dts -F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts -F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts -F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2c_4.dts -F: arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi F: arch/arm/dts/imx6dl-aristainetos2c_7.dts F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 14931120f6..6bfaaed666 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -194,87 +194,6 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[3]); } -static void enable_spi_display(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - s32 timeout = 100000; - -#if defined(CONFIG_VIDEO_BMP_LOGO) - rotate_logo(3); /* portrait display in landscape mode */ -#endif - - reg = readl(&ccm->cs2cdr); - - /* select pll 5 clock */ - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - writel(reg, &ccm->cs2cdr); - - /* set PLL5 to 197994996Hz */ - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); - writel(reg, &ccm->analog_pll_video); - - writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), - &ccm->analog_pll_video_num); - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), - &ccm->analog_pll_video_denom); - - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - while (timeout--) - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) - break; - if (timeout < 0) - printf("Warning: video pll lock timeout!\n"); - - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_ENABLE; - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; - writel(reg, &ccm->analog_pll_video); - - /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ - reg = readl(&ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &ccm->cs2cdr); - - reg = readl(&ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &ccm->cscmr2); - - reg = readl(&ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); - writel(reg, &ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT - | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); -} - static void setup_display(void) { enable_ipu_clock(); @@ -331,25 +250,36 @@ static void setup_board_gpio(void) setup_one_led("led_blue", LEDST_OFF); } -#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \ - " rescueReason=%d " - static void aristainetos_run_rescue_command(int reason) { - char rescue_reason_command[80]; + char rescue_reason_command[20]; - sprintf(rescue_reason_command, ARI_RESC_FMT, reason); + sprintf(rescue_reason_command, "setenv rreason %d", reason); run_command(rescue_reason_command, 0); } -static int aristainetos_eeprom(void) +static int aristainetos_bootmode_settings(void) { + struct gpio_desc *desc; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int sbmr1 = readl(&psrc->sbmr1); + char *my_bootdelay; + char bootmode = 0; + int ret; struct udevice *dev; int off; - int ret; u8 data[0x10]; u8 rescue_reason; + /* jumper controlled reset of the environment */ + ret = gpio_hog_lookup_name("env_reset", &desc); + if (!ret) { + if (dm_gpio_get_value(desc)) { + printf("\nReset u-boot environment (jumper)\n"); + run_command("run default_env; saveenv; saveenv", 0); + } + } + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); if (off < 0) { printf("%s: No eeprom0 path offset\n", __func__); @@ -366,37 +296,26 @@ static int aristainetos_eeprom(void) if (ret) return ret; - ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6); + ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data)); if (ret) { printf("%s: Could not read EEPROM\n", __func__); return ret; } - if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { - rescue_reason = *(uint8_t *)&data[9]; - memset(&data[3], 0xff, 7); - i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); - printf("\nBooting into Rescue System (EEPROM)\n"); - aristainetos_run_rescue_command(rescue_reason); - run_command("run rescue_load_fit rescueboot", 0); - } else if (strncmp((char *)data, "DeF", 3) == 0) { + /* software controlled reset of the environment (EEPROM magic) */ + if (strncmp((char *)data, "DeF", 3) == 0) { memset(data, 0xff, 3); i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3); - printf("\nClear u-boot environment (set back to defaults)\n"); + printf("\nReset u-boot environment (EEPROM)\n"); run_command("run default_env; saveenv; saveenv", 0); } - return 0; -}; - -static void aristainetos_bootmode_settings(void) -{ - struct gpio_desc *desc; - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned int sbmr1 = readl(&psrc->sbmr1); - char *my_bootdelay; - char bootmode = 0; - int ret; + if (sbmr1 & 0x40) { + env_set("bootmode", "1"); + printf("SD bootmode jumper set!\n"); + } else { + env_set("bootmode", "0"); + } /* * Check the boot-source. If booting from NOR Flash, @@ -420,28 +339,27 @@ static void aristainetos_bootmode_settings(void) env_set("bootdelay", "-2"); } - if (sbmr1 & 0x40) { - env_set("bootmode", "1"); - printf("SD bootmode jumper set!\n"); - } else { - env_set("bootmode", "0"); - } - - /* read out some jumper values*/ - ret = gpio_hog_lookup_name("env_reset", &desc); - if (!ret) { - if (dm_gpio_get_value(desc)) { - printf("\nClear env (set back to defaults)\n"); - run_command("run default_env; saveenv; saveenv", 0); - } - } + /* jumper controlled boot of the rescue system */ ret = gpio_hog_lookup_name("boot_rescue", &desc); if (!ret) { if (dm_gpio_get_value(desc)) { + printf("\nBooting into Rescue System (jumper)\n"); aristainetos_run_rescue_command(16); run_command("run rescue_xload_boot", 0); } } + + /* software controlled boot of the rescue system (EEPROM magic) */ + if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { + rescue_reason = *(uint8_t *)&data[9]; + memset(&data[3], 0xff, 7); + i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); + printf("\nBooting into Rescue System (EEPROM)\n"); + aristainetos_run_rescue_command(rescue_reason); + run_command("run rescue_xload_boot", 0); + } + + return 0; } #if defined(CONFIG_DM_PMIC_DA9063) @@ -497,15 +415,15 @@ static int setup_pmic_voltages(void) int board_late_init(void) { int x, y; + int ret; led_default_state(); splash_get_pos(&x, &y); bmp_display((ulong)&bmp_logo_bitmap[0], x, y); - aristainetos_bootmode_settings(); - - /* eeprom work */ - aristainetos_eeprom(); + ret = aristainetos_bootmode_settings(); + if (ret) + return ret; /* set board_type */ if (gd->board_type == BOARD_TYPE_4) @@ -549,97 +467,9 @@ struct display_info_t const displays[] = { .vmode = FB_VMODE_NONINTERLACED } } -#if ((CONFIG_SYS_BOARD_VERSION == 2) || \ - (CONFIG_SYS_BOARD_VERSION == 3) || \ - (CONFIG_SYS_BOARD_VERSION == 4) || \ - (CONFIG_SYS_BOARD_VERSION == 5)) - , { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = NULL, - .enable = enable_spi_display, - .mode = { - .name = "lg4573", - .refresh = 57, - .xres = 480, - .yres = 800, - .pixclock = 37037, - .left_margin = 59, - .right_margin = 10, - .upper_margin = 15, - .lower_margin = 15, - .hsync_len = 10, - .vsync_len = 15, - .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED - } - } -#endif }; size_t display_count = ARRAY_SIZE(displays); -#if defined(CONFIG_MTD_RAW_NAND) -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, - ARRAY_SIZE(nfc_pads)); - - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable ENFC_CLK_ROOT clock */ - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#else -static void setup_gpmi_nand(void) -{ -} -#endif - int board_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -648,7 +478,6 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; setup_board_gpio(); - setup_gpmi_nand(); setup_display(); /* GPIO_1 for USB_OTG_ID */ diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index e26de5144d..945a2c4df9 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -2,10 +2,7 @@ config SYS_BOARD_VERSION int "select version of aristainetos board" help version of aristainetos board version - 2 version 2 - 3 version 2b - 4 version 2bcsl - 5 version 2c + 5 version 2c and 2d config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig deleted file mode 100644 index 35e4b09715..0000000000 --- a/configs/aristainetos2_defconfig +++ /dev/null @@ -1,121 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -# CONFIG_CMD_NANDBCB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2_4 imx6dl-aristainetos2_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 -CONFIG_SF_DEFAULT_CS=1 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig deleted file mode 100644 index d47a074645..0000000000 --- a/configs/aristainetos2b_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2B=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig deleted file mode 100644 index 30139621d8..0000000000 --- a/configs/aristainetos2bcsl_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2BCSL=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 50cadb749a..f602b6eda1 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -10,11 +10,10 @@ CONFIG_DM_GPIO=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 +CONFIG_BOOTDELAY=-2 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" @@ -51,7 +50,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7" +CONFIG_OF_LIST="imx6dl-aristainetos2c_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 6e8595caad..916bd5a59c 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -13,14 +13,15 @@ #define CONFIG_HOSTNAME "aristainetos2" +#if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" +#endif #define CONFIG_FEC_XCV_TYPE RGMII /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 28341000 -#define CONFIG_LG4573 #include "mx6_common.h" @@ -77,6 +78,8 @@ "enable_hab_check=1\0" #else #define HAB_EXTRA_SETTINGS \ + "hab_check_addr=echo HAB check addr always returns " \ + "true;true\0" \ "hab_check_file_fit=echo HAB check FIT file always returns " \ "true;true\0" \ "hab_check_flash_fit=echo HAB check flash FIT always returns " \ @@ -86,96 +89,12 @@ "enable_hab_check=0\0" #endif -#if (CONFIG_SYS_BOARD_VERSION == 3) +#if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" -#elif (CONFIG_SYS_BOARD_VERSION == 4) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on;led led_red2 on;\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" -#elif (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "emmcpart=1\0" \ - "emmc_rescue_part=3\0" \ - "emmcdev=1\0" \ - "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ - "dead=led led_red on\0" \ - "mtdids=nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart} " \ - "emmcpart=${emmcpart}\0" \ - "mainboot=echo Booting from eMMC ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${emmcroot} rootfstype=ext4\0 " \ - "main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ - "${fit_file}; " \ - "imi ${fit_addr_r}\0 " \ - "rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \ - "${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0" -#else -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ - "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" + "dead=while true; do; " \ + "led led_red on; sleep 1;" \ + "led led_red off; sleep 1;" \ + "done\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -183,17 +102,24 @@ "usb_pgood_delay=2000\0" \ "nor_bootdelay=-2\0" \ "script=u-boot.scr\0" \ - "fit_file=/boot/system.itb\0" \ - "rescue_fit_file=/boot/rescue.itb\0" \ "loadaddr=0x12000000\0" \ "fit_addr_r=0x14000000\0" \ - "uboot=/boot/u-boot.imx\0" \ "uboot_sz=d0000\0" \ "panel=lb07wv8\0" \ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ + "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "mtdids=nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor)\0" \ + "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \ + "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \ + "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \ + "mk_pubkey_path=setenv pubkey /${sysnum}/PCR.pem\0" \ + "mk_rescue_pubkey_path=setenv pubkey /${rescue_sysnum}/PCR.pem\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} rng_core.default_quality=1000 " \ + "mmcpart=${mmcpart} emmcpart=${emmcpart} sysnum=${sysnum}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "boot_board_type=bootm ${fit_addr_r}#${board_type}\0" \ "get_env=mw ${loadaddr} 0 0x20000;" \ @@ -205,7 +131,7 @@ "sf protect unlock 0 0x1000000;" \ "mw ${loadaddr} 0 0x20000;" \ "env export -t ${loadaddr} serial# ethaddr " \ - "board_type panel addmisc addmiscM addmiscC addmiscD;" \ + "board_type panel;" \ "env default -a;" \ "env import -t ${loadaddr}\0" \ "loadbootscript=" \ @@ -216,28 +142,62 @@ "loadbootscriptUSBf=" \ "fatload usb 0 ${loadaddr} ${script};\0" \ "bootscriptUSB=echo Running bootscript from usb-stick ...; " \ - "source\0" \ + "source \0" \ "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ + "source \0" \ "mmcpart=1\0" \ - "mmcrescuepart=3\0" \ "mmcdev=0\0" \ + "emmcpart=1\0" \ + "emmcdev=1\0" \ + "sysnum=1\0" \ + "rescue_sysnum=0\0" \ + "rreason=18\0" \ + "mainboot=echo Booting from eMMC ...; " \ + "run mainargs addmtd addmisc;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${emmcroot} rootfstype=ext4\0 " \ + "main_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${fit_file}; " \ + "imi ${fit_addr_r}\0 " \ + "rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${rescue_fit_file}; " \ + "imi ${fit_addr_r}\0" \ + "main_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mainRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ + "mmcRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${mmcroot}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ - "mmc_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "mmc_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ "${fit_file}\0" \ - "mmc_load_uboot=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${uboot}\0" \ - "mmc_rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "imi ${fit_addr_r}\0" \ + "mmc_rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} " \ "${fit_addr_r} ${rescue_fit_file}\0" \ + "imi ${fit_addr_r}\0" \ + "mmc_load_uboot=run mk_uboot_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${uboot}\0" \ "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ "setexpr uboot_maxsize ${uboot_sz} - 400;" \ @@ -246,14 +206,19 @@ "sf write ${loadaddr} 400 ${filesize};" \ "sf read ${cmp_buf} 400 ${uboot_sz};" \ "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ - "rescueargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/ram rw\0 " \ + "mmc_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mmc_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ "rescueboot=echo Booting rescue system ...; " \ - "run rescueargs addmtd addmisc;" \ + "run addmtd addmisc;" \ "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "if bootm ${fit_addr_r}; then ; " \ "else " \ @@ -261,50 +226,73 @@ "fi; \0" \ "r_reason_syserr=setenv rescue_reason setenv bootargs " \ "\\\\${bootargs} " \ - "rescueReason=18\0 " \ - "usb_load_fit=ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ - "usb_load_fitf=fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ - "usb_load_rescuefit=ext4load usb 0 ${fit_addr_r} " \ + "rescueReason=$rreason\0 " \ + "usb_load_fit=run mk_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_fitf=run mk_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_rescuefit=run mk_rescue_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} " \ "${rescue_fit_file}\0" \ - "usb_load_rescuefitf=fatload usb 0 ${fit_addr_r} " \ + "usb_load_rescuefitf=run mk_rescue_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} " \ "${rescue_fit_file}\0" \ + "usb_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_load_pubkeyf=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkeyf=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ "usbroot=/dev/sda1 rootwait rw\0" \ "usbboot=echo Booting from usb-stick ...; " \ "run usbargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ "usbargs=setenv bootargs console=${console},${baudrate} " \ "root=${usbroot}\0" \ + "usbRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${usbroot} rw\0 " \ "mmc_rescue_boot=" \ "run r_reason_syserr;" \ - "if run mmc_rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run mmc_rescue_load_pubkey hab_check_addr " \ + "mmc_rescue_load_fit hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM FROM SD-CARD BOOT FAILURE;" \ + "run dead; " \ "fi;\0" \ "main_rescue_boot=" \ - "if run main_load_fit hab_check_flash_fit; then " \ + "if run main_load_pubkey hab_check_addr " \ + "main_load_fit hab_check_flash_fit; then " \ "if run mainboot; then ; " \ "else " \ "run r_reason_syserr;" \ - "if run rescue_load_fit hab_check_file_fit;" \ - "then run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi; " \ "else " \ "run r_reason_syserr;" \ - "if run rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi;\0" \ "usb_mmc_rescue_boot=" \ @@ -318,17 +306,21 @@ "hab_check_file_bootscript;" \ "then run bootscriptUSB; " \ "fi; " \ - "if run usb_load_fit hab_check_file_fit; then " \ + "if run usb_load_pubkey hab_check_addr " \ + "usb_load_fit hab_check_file_fit; then " \ "run usbboot; " \ "fi; " \ - "if run usb_load_fitf hab_check_file_fit; then " \ + "if run usb_load_pubkeyf hab_check_addr " \ + "usb_load_fitf hab_check_file_fit; then " \ "run usbboot; " \ "fi; "\ - "if run usb_load_rescuefit hab_check_file_fit;" \ - "then run r_reason_syserr rescueboot;" \ + "if run usb_rescue_load_pubkey hab_check_addr " \ + "usb_load_rescuefit hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf hab_check_file_fit;" \ - "then run r_reason_syserr rescueboot;" \ + "if run usb_rescue_load_pubkeyf hab_check_addr " \ + "usb_load_rescuefitf hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ "fi; " \ "run mmc_rescue_boot;" \ "fi; "\ @@ -338,48 +330,57 @@ "if test ${bootmode} -ne 0 ; then " \ "mmc dev ${mmcdev};" \ "if mmc rescan; then " \ - "if run mmc_rescue_load_fit " \ - "hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run mmc_rescue_load_pubkey " \ + "hab_check_addr " \ + "mmc_rescue_load_fit " \ + "hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ "else " \ "usb start;" \ "if usb storage; then " \ - "if run usb_load_rescuefit " \ - "hab_check_file_fit;"\ - "then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf "\ - "hab_check_file_fit;"\ - "then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ "fi;" \ "fi;" \ - "run dead; " \ "echo RESCUE SYSTEM ON SD OR " \ "USB BOOT FAILURE;" \ + "run dead; " \ "else " \ "usb start;" \ "if usb storage; then " \ - "if run usb_load_rescuefit " \ - "hab_check_file_fit; then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf " \ - "hab_check_file_fit; then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ "fi;" \ - "run dead; " \ "echo RESCUE SYSTEM ON USB BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "else "\ - "if run rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM ON BOARD BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi;\0" \ "ari_boot=if test ${bootmode} -ne 0 ; then " \ @@ -388,7 +389,8 @@ "if run loadbootscript hab_check_file_bootscript;" \ "then run bootscript; " \ "fi; " \ - "if run mmc_load_fit hab_check_file_fit; then " \ + "if run mmc_load_pubkey hab_check_addr " \ + "mmc_load_fit hab_check_file_fit; then " \ "if run mmcboot; then ; " \ "else " \ "run mmc_rescue_boot;" \ @@ -421,12 +423,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ From 015c026f7a51dccae4040bc3912101e1e5a30b12 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Nov 2020 20:46:03 +0100 Subject: [PATCH 034/222] imx6: add support for aristainetos2c_cslb board variant add support for aristainetos2c_cslb board variant. Signed-off-by: Heiko Schocher --- arch/arm/dts/Makefile | 1 + .../imx6dl-aristainetos2c_cslb_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts | 16 ++ .../imx6qdl-aristainetos2c_cslb-u-boot.dtsi | 77 ++++++ arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi | 232 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 + board/aristainetos/MAINTAINERS | 5 + board/aristainetos/common/Kconfig | 1 + configs/aristainetos2c_defconfig | 3 +- configs/aristainetos2ccslb_defconfig | 118 +++++++++ include/configs/aristainetos2.h | 9 + 12 files changed, 502 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi create mode 100644 configs/aristainetos2ccslb_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 457ccfe08f..089dfb73a3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -644,6 +644,7 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ imx6dl-aristainetos2c_7.dtb \ + imx6dl-aristainetos2c_cslb_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi new file mode 100644 index 0000000000..b069debc1e --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts new file mode 100644 index 0000000000..b40ddafeb9 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c cslb board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2c_cslb.dtsi" + +/ { + model = "aristainetos2c cslb i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi new file mode 100644 index 0000000000..8c2ed70075 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart1; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi new file mode 100644 index 0000000000..c3724ec86f --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c-cslb board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +#include +#include + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_blue_2 { + label = "led_blue2"; + gpios = <&expander 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_green_2 { + label = "led_green2"; + gpios = <&expander 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_red_2 { + label = "led_red2"; + gpios = <&expander 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_yellow_2 { + label = "led_yellow2"; + gpios = <&expander 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&gpio7 { + eMMC_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* TPM PP */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 + /* TPM Reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + /* eMMC Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9d6c344064..513d007ce7 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -139,6 +139,17 @@ config TARGET_ARISTAINETOS2C imply CMD_SATA imply CMD_DM +config TARGET_ARISTAINETOS2CCSLB + bool "Support aristainetos2-revC CSL" + depends on MX6DL + select BOARD_LATE_INIT + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" depends on MX6QDL diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index d67002503d..cc603c1bc2 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -9,3 +9,15 @@ config SYS_BOARD_VERSION default 5 endif + +if TARGET_ARISTAINETOS2CCSLB + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 6 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 1c3fb3aeb1..c81bef9cb7 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,10 +4,15 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2c_defconfig +F: configs/aristainetos2ccslb_defconfig F: arch/arm/dts/imx6dl-aristainetos2c_7.dts F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts +F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 945a2c4df9..328243c2f9 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -3,6 +3,7 @@ config SYS_BOARD_VERSION help version of aristainetos board version 5 version 2c and 2d + 6 version 2c-cslb config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index f602b6eda1..773d7f6774 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -10,6 +10,7 @@ CONFIG_DM_GPIO=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" @@ -50,8 +51,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7" -CONFIG_OF_LIST="imx6dl-aristainetos2c_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig new file mode 100644 index 0000000000..16d3c88fe1 --- /dev/null +++ b/configs/aristainetos2ccslb_defconfig @@ -0,0 +1,118 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_MX6DL=y +CONFIG_TARGET_ARISTAINETOS2CCSLB=y +CONFIG_DM_GPIO=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_cslb_7" +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=-2 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_APBH_DMA=y +CONFIG_APBH_DMA_BURST=y +CONFIG_APBH_DMA_BURST8=y +CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_DA9063=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_DA9063=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 916bd5a59c..c1e8b4a10c 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -16,6 +16,9 @@ #if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" +#elif (CONFIG_SYS_BOARD_VERSION == 6) +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" #endif #define CONFIG_FEC_XCV_TYPE RGMII @@ -95,6 +98,12 @@ "led led_red on; sleep 1;" \ "led led_red off; sleep 1;" \ "done\0" +#elif (CONFIG_SYS_BOARD_VERSION == 6) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=while true; do; " \ + "led led_red on; led led_red2 on; sleep 1;" \ + "led led_red off; led led_red2 off;; sleep 1;" \ + "done\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ From 68163c3bf0fee9a32e4a31f2d678561ed833264f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Nov 2020 20:46:04 +0100 Subject: [PATCH 035/222] arm: dts: aristainetos: sync with changes in linux sync with comaptible changes in linux from Krzysztof Kozlowski. https://patchwork.kernel.org/project/linux-arm-kernel/patch/20200930190143.27032-12-krzk@kernel.org/ Signed-off-by: Heiko Schocher --- arch/arm/dts/imx6dl-aristainetos2c_7.dts | 2 +- arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts index 00eec82bf4..e1f9e88291 100644 --- a/arch/arm/dts/imx6dl-aristainetos2c_7.dts +++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts @@ -12,5 +12,5 @@ / { model = "aristainetos2c+2d i.MX6 Dual Lite Boards 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; }; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts index b40ddafeb9..7f839ca5e2 100644 --- a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts +++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts @@ -12,5 +12,5 @@ / { model = "aristainetos2c cslb i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; }; From 7a8d18da4bb2a92246af1129337164e9a41a9abf Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Nov 2020 20:46:05 +0100 Subject: [PATCH 036/222] imx: aristainetos: enable U-Boot Environment variables protection enable Environment protection with: CONFIG_ENV_APPEND=y CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE and add board specific env_get_location() function. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 20 ++++++++++++++++++++ configs/aristainetos2c_defconfig | 8 +++++++- configs/aristainetos2ccslb_defconfig | 10 +++++++++- include/configs/aristainetos2.h | 3 +++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 6bfaaed666..07d2e3ec7b 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -527,3 +528,22 @@ int embedded_dtb_select(void) return 0; } #endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_SPI_FLASH; + + switch (prio) { + case 0: + return ENVL_NOWHERE; + + case 1: + return ENVL_SPI_FLASH; + + default: + return ENVL_UNKNOWN; + } + + return ENVL_UNKNOWN; +} diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 773d7f6774..df0b26d6a0 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_SYS_MALLOC_F_LEN=0x13000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0xD0000 CONFIG_MX6DL=y @@ -30,6 +30,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_NVEDIT_INFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -54,10 +56,14 @@ CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_APBH_DMA=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 16d3c88fe1..0156493934 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_SYS_MALLOC_F_LEN=0x13000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0xD0000 CONFIG_MX6DL=y @@ -30,6 +30,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_NVEDIT_INFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -54,10 +56,14 @@ CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_APBH_DMA=y @@ -114,5 +120,7 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index c1e8b4a10c..78fa1a969e 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -449,4 +449,7 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 +#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ + "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" + #endif /* __ARISTAINETOS2_CONFIG_H */ From 61eb1fe56849c1418f35c5a9579047ab113e914f Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Thu, 12 Nov 2020 11:51:04 +0100 Subject: [PATCH 037/222] imx: clk: added IPG Clock for I2C on imx8qm This patch fixes this clk issue on I2C on imx8qm => i2c bus Bus 3: i2c@5a830000 => i2c dev 3 Setting bus to 3 Failed to enable ipg clk Failure changing bus number (-524) Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Peng Fan Cc: uboot-imx Reviewed-by: Stefano Babic --- drivers/clk/imx/clk-imx8qm.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 54fb09fda4..7e466d630a 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -53,19 +53,27 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_A53; pm_clk = SC_PM_CLK_CPU; break; + case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: + case IMX8QM_I2C0_DIV: resource = SC_R_I2C_0; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C1_IPG_CLK: case IMX8QM_I2C1_CLK: + case IMX8QM_I2C1_DIV: resource = SC_R_I2C_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C2_IPG_CLK: case IMX8QM_I2C2_CLK: + case IMX8QM_I2C2_DIV: resource = SC_R_I2C_2; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C3_IPG_CLK: case IMX8QM_I2C3_CLK: + case IMX8QM_I2C3_DIV: resource = SC_R_I2C_3; pm_clk = SC_PM_CLK_PER; break; @@ -148,19 +156,27 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); switch (clk->id) { + case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: + case IMX8QM_I2C0_DIV: resource = SC_R_I2C_0; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C1_IPG_CLK: case IMX8QM_I2C1_CLK: + case IMX8QM_I2C1_DIV: resource = SC_R_I2C_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C2_IPG_CLK: case IMX8QM_I2C2_CLK: + case IMX8QM_I2C2_DIV: resource = SC_R_I2C_2; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C3_IPG_CLK: case IMX8QM_I2C3_CLK: + case IMX8QM_I2C3_DIV: resource = SC_R_I2C_3; pm_clk = SC_PM_CLK_PER; break; @@ -242,19 +258,27 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id); switch (clk->id) { + case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: + case IMX8QM_I2C0_DIV: resource = SC_R_I2C_0; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C1_IPG_CLK: case IMX8QM_I2C1_CLK: + case IMX8QM_I2C1_DIV: resource = SC_R_I2C_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C2_IPG_CLK: case IMX8QM_I2C2_CLK: + case IMX8QM_I2C2_DIV: resource = SC_R_I2C_2; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_I2C3_IPG_CLK: case IMX8QM_I2C3_CLK: + case IMX8QM_I2C3_DIV: resource = SC_R_I2C_3; pm_clk = SC_PM_CLK_PER; break; From f4433e7f27d36b3b81e23c0e8139fe28a6e97951 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 6 Nov 2020 09:09:31 +0100 Subject: [PATCH 038/222] imx: ahab: Fix compiler warnings in printf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit arch/arm/mach-imx/imx8/ahab.c:110:63: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘u64 {aka long long unsigned int}’ [-Wformat=] Fix those by using %llx Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: uboot-imx --- arch/arm/mach-imx/imx8/ahab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 5dbe1d56e0..bbdced5513 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -106,7 +106,7 @@ int authenticate_os_container(ulong addr) /* Find the memreg and set permission for seco pt */ err = sc_rm_find_memreg(-1, &mr, s, e); if (err) { - printf("Error: can't find memreg for image load address 0x%x, error %d\n", img->dst, err); + printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err); ret = -ENOMEM; goto exit; } From 492b728f9f5af73ee407d800170935429d8dcf90 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 6 Nov 2020 09:09:30 +0100 Subject: [PATCH 039/222] imx: ahab: fix compiler warnings in debug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit arch/arm/mach-imx/imx8/ahab.c: In function ‘authenticate_os_container’: arch/arm/mach-imx/imx8/ahab.c:96:9: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 9 has type ‘ulong {aka long unsigned int}’ [-Wformat=] debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n", Fix those by using "%lu" specified. Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: uboot-imx --- arch/arm/mach-imx/imx8/ahab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index bbdced5513..9df7474139 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -92,7 +92,7 @@ int authenticate_os_container(ulong addr) sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); - debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n", + debug("img %d, dst 0x%x, src 0x%lux, size 0x%x\n", i, (uint32_t) img->dst, img->offset + addr, img->size); memcpy((void *)img->dst, (const void *)(img->offset + addr), From b15cd88b225ad5a4e81d9144c5e5c265c8588933 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 6 Nov 2020 09:09:29 +0100 Subject: [PATCH 040/222] imx: ahab: fix implicit declaration warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the following warning: arch/arm/mach-imx/imx8/ahab.c:105:3: warning: implicit declaration of function ‘flush_dcache_range’ [-Wimplicit-function-declaration] flush_dcache_range(s, e); ^~~~~~~~~~~~~~~~~~ Include cpu_func.h header which declares the flush_dcache_range() function. Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: uboot-imx --- arch/arm/mach-imx/imx8/ahab.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 9df7474139..4bb7c46921 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -14,6 +14,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; From b5874b552ffa09bc1dc5dec6b5dd376c62dab45d Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Thu, 5 Nov 2020 14:57:13 +0800 Subject: [PATCH 041/222] mmc: fsl_esdhc_imx: add wait_dat0() support Add wait_dat0() support, upper layer will use this callback. Signed-off-by: Haibo Chen Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc_imx.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 22040c67a8..29592d1f2c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1646,6 +1646,20 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev) } #endif +static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, + int timeout_us) +{ + int ret; + u32 tmp; + struct fsl_esdhc_priv *priv = dev_get_priv(dev); + struct fsl_esdhc *regs = priv->esdhc_regs; + + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, + !!(tmp & PRSSTAT_DAT0) == !!state, + timeout_us); + return ret; +} + static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, @@ -1656,6 +1670,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe, #endif + .wait_dat0 = fsl_esdhc_wait_dat0, }; #endif From c4c2d2465eb9a03061ac5ae3898f720124c23138 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 4 Nov 2020 17:18:38 +0100 Subject: [PATCH 042/222] board: ge: common: vpd: fix name Commit f692b479f02d changed the VPD partition name from "vpd" to "vpd@0". Fix the VPD reader code to use the new name, so that the VPD code keeps working. Fixes: f692b479f02d ("i2c: eeprom: Use reg property instead of offset and size") Signed-off-by: Sebastian Reichel --- board/ge/common/vpd_reader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c index 421fee5922..c28d2c03cf 100644 --- a/board/ge/common/vpd_reader.c +++ b/board/ge/common/vpd_reader.c @@ -209,7 +209,7 @@ int read_i2c_vpd(struct vpd_cache *cache, u8 *data; int size; - ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd", &dev); + ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd@0", &dev); if (ret) return ret; From f2ac6f7796bbb8aae18998794fddf59198090c3f Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 4 Nov 2020 17:18:39 +0100 Subject: [PATCH 043/222] board: ge: bx50v3: correct CONFIG_CMD_NFS Fix typo in NFS command configuration check. Signed-off-by: Ian Ray Signed-off-by: Sebastian Reichel --- include/configs/ge_bx50v3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 4fdc2b6596..c328a12ce1 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -48,7 +48,7 @@ #define CONFIG_LOADADDR 0x12000000 -#ifdef CONFIG_NFS_CMD +#ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ @@ -130,7 +130,7 @@ #define CONFIG_USBBOOTCOMMAND \ "echo Unsupported; " \ -#ifdef CONFIG_NFS_CMD +#ifdef CONFIG_CMD_NFS #define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND #elif CONFIG_CMD_USB #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND From 822e1b31bdf6abec87375a8e4fd1fe2b830bdce0 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 4 Nov 2020 17:18:40 +0100 Subject: [PATCH 044/222] board: ge: bx50v3: drop unused pinmux defines Remove pinmux defines, that are no longer used after converting the code to devicetree. Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 8a38ac5d4e..5ad265af8a 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -50,21 +50,6 @@ static struct vpd_cache vpd; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - int dram_init(void) { gd->ram_size = imx_ddr_size(); From 2d86fb31bdee7d428a3e423d54b51e5e02221682 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 4 Nov 2020 17:18:41 +0100 Subject: [PATCH 045/222] board: ge: bx50v3: reduce magic numbers Use VPD product ID instead of confidx, so that we can easily reuse the product ID defines and avoid some magic numbers. Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 5ad265af8a..8e7b90a10c 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -43,7 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; -static int confidx; /* Default to generic. */ +#define VPD_PRODUCT_B850 1 +#define VPD_PRODUCT_B650 2 +#define VPD_PRODUCT_B450 3 + +static int productid; /* Default to generic. */ static struct vpd_cache vpd; #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -112,7 +116,7 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int is_b850v3(void) { - return confidx == 3; + return productid == VPD_PRODUCT_B850; } static int detect_lcd(struct display_info_t const *dev) @@ -299,9 +303,6 @@ int overwrite_console(void) #define VPD_TYPE_INVALID 0x00 #define VPD_BLOCK_NETWORK 0x20 #define VPD_BLOCK_HWID 0x44 -#define VPD_PRODUCT_B850 1 -#define VPD_PRODUCT_B650 2 -#define VPD_PRODUCT_B450 3 #define VPD_HAS_MAC1 0x1 #define VPD_HAS_MAC2 0x2 #define VPD_MAC_ADDRESS_LENGTH 6 @@ -397,28 +398,13 @@ int board_early_init_f(void) return 0; } -static void set_confidx(const struct vpd_cache* vpd) -{ - switch (vpd->product_id) { - case VPD_PRODUCT_B450: - confidx = 1; - break; - case VPD_PRODUCT_B650: - confidx = 2; - break; - case VPD_PRODUCT_B850: - confidx = 3; - break; - } -} - int board_init(void) { if (!read_i2c_vpd(&vpd, vpd_callback)) { int ret, rescan; vpd.is_read = true; - set_confidx(&vpd); + productid = vpd.product_id; ret = fdtdec_resetup(&rescan); if (!ret && rescan) { From 559aaa2526dc0c1e1cca2ff3b1614f2991d1a7e6 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 4 Nov 2020 17:18:42 +0100 Subject: [PATCH 046/222] board: ge: reduce VPD EEPROM partition size Reduce vital product data size to match the latest specification. Signed-off-by: Ian Ray Signed-off-by: Sebastian Reichel --- arch/arm/dts/imx53-ppd-uboot.dtsi | 2 +- arch/arm/dts/imx6q-bx50v3-uboot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx53-ppd-uboot.dtsi b/arch/arm/dts/imx53-ppd-uboot.dtsi index d61b7cb876..b293e27a03 100644 --- a/arch/arm/dts/imx53-ppd-uboot.dtsi +++ b/arch/arm/dts/imx53-ppd-uboot.dtsi @@ -28,7 +28,7 @@ #size-cells = <1>; vpd@0 { - reg = <0 1022>; + reg = <0 800>; }; bootcount: bootcount@1022 { diff --git a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi index 01321cab78..2de3b850ec 100644 --- a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi +++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi @@ -27,7 +27,7 @@ #size-cells = <1>; vpd@0 { - reg = <0 1022>; + reg = <0 800>; }; bootcount: bootcount { From 4f1970f4373566190fc447bf7e27e9e95ec84cf8 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 4 Nov 2020 17:18:43 +0100 Subject: [PATCH 047/222] board: ge: bx50v3: check b850v3 power management watchdog Set `bootcause' from b850v3 power management watchdog status. Boot cause "REVERT" is no longer used, remove it. Signed-off-by: Ian Ray Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 17 +++++++++++++++++ include/configs/ge_bx50v3.h | 4 +--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 8e7b90a10c..4754647fb4 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -384,6 +384,7 @@ static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL), }; #define SUS_S3_OUT IMX_GPIO_NR(4, 11) +#define PWGIN_IN IMX_GPIO_NR(4, 14) #define WIFI_EN IMX_GPIO_NR(6, 14) int board_early_init_f(void) @@ -416,6 +417,9 @@ int board_init(void) gpio_request(SUS_S3_OUT, "sus_s3_out"); gpio_direction_output(SUS_S3_OUT, 1); + gpio_request(PWGIN_IN, "pwgin_in"); + gpio_direction_input(PWGIN_IN); + gpio_request(WIFI_EN, "wifi_en"); gpio_direction_output(WIFI_EN, 1); @@ -465,6 +469,17 @@ void pmic_init(void) } } +static void detect_boot_cause(void) +{ + const char *cause = "POR"; + + if (is_b850v3()) + if (!gpio_get_value(PWGIN_IN)) + cause = "PM_WDOG"; + + env_set("bootcause", cause); +} + int board_late_init(void) { process_vpd(&vpd); @@ -478,6 +493,8 @@ int board_late_init(void) else env_set("videoargs", "video=LVDS-1:1024x768@65"); + detect_boot_cause(); + /* board specific pmic init */ pmic_init(); diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index c328a12ce1..e5c580b3f9 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -56,7 +56,7 @@ "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ - "setenv bootargs $bootargs cma=128M bootcause=POR ${videoargs} " \ + "setenv bootargs $bootargs cma=128M bootcause=${bootcause} ${videoargs} " \ "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ "networkboot=" \ @@ -74,7 +74,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ NETWORKBOOT \ - "bootcause=POR\0" \ "image=/boot/fitImage\0" \ "dev=mmc\0" \ "devnum=2\0" \ @@ -104,7 +103,6 @@ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ "run hasfirstboot || setenv partnum 0; " \ "if test ${partnum} != 0; then " \ - "setenv bootcause REVERT; " \ "run swappartitions loadimage doboot; " \ "fi; " \ "run failbootcmd\0" \ From ea51af2fdd87bb5da024507c9233a038e84e8737 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Wed, 4 Nov 2020 12:02:23 +0100 Subject: [PATCH 048/222] imx: imx8qm_rom7720_a1: add missing DTS to the MAINTAINERS add the dts file to the MAINTAINERS entry Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: uboot-imx --- board/advantech/imx8qm_rom7720_a1/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS index b142ee02e6..58a4d253c3 100644 --- a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS +++ b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS @@ -2,5 +2,6 @@ i.MX8QM ROM 7720 a1 BOARD M: Oliver Graute S: Maintained F: board/advantech/imx8qm_rom7720_a1/ +F: arch/arm/dts/imx8qm-rom7720-a1.dts F: include/configs/imx8qm_rom7720.h F: configs/imx8qm_rom7720_a1_4G_defconfig From 5d772196d93509306f9a4333e181a64f3e7e4249 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 3 Nov 2020 17:18:35 +0800 Subject: [PATCH 049/222] mmc: fsl_esdhc_imx: optimize the timing setting For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the card clock will be divied by 2 automatically by the host. So need to first config the DDR_EN correctly, then update the card clock. This will make sure the actual card clock is as our expected. IC also suggest config the DDR_EN firstly, then config the clock divider. For HS400/HS400ES mode, need to config the strobe dll, this need to based on the correct target clock rate, so need to do this after clock rate is update. Signed-off-by: Haibo Chen Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc_imx.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 29592d1f2c..e5409ade1b 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -760,7 +760,6 @@ static int esdhc_set_timing(struct mmc *mmc) case MMC_HS_400_ES: mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; esdhc_write32(®s->mixctrl, mixctrl); - esdhc_set_strobe_dll(mmc); break; case MMC_HS: case MMC_HS_52: @@ -933,6 +932,23 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) int ret __maybe_unused; u32 clock; +#ifdef MMC_SUPPORTS_TUNING + /* + * call esdhc_set_timing() before update the clock rate, + * This is because current we support DDR and SDR mode, + * Once the DDR_EN bit is set, the card clock will be + * divide by 2 automatically. So need to do this before + * setting clock rate. + */ + if (priv->mode != mmc->selected_mode) { + ret = esdhc_set_timing(mmc); + if (ret) { + printf("esdhc_set_timing error %d\n", ret); + return ret; + } + } +#endif + /* Set the clock speed */ clock = mmc->clock; if (clock < mmc->cfg->f_min) @@ -957,13 +973,13 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #endif } - if (priv->mode != mmc->selected_mode) { - ret = esdhc_set_timing(mmc); - if (ret) { - printf("esdhc_set_timing error %d\n", ret); - return ret; - } - } + /* + * For HS400/HS400ES mode, make sure set the strobe dll in the + * target clock rate. So call esdhc_set_strobe_dll() after the + * clock updated. + */ + if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) + esdhc_set_strobe_dll(mmc); if (priv->signal_voltage != mmc->signal_voltage) { ret = esdhc_set_voltage(mmc); From a5b5ad4d859bafc562b17861acf32d42d3cf7625 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 28 Oct 2020 11:58:08 +0200 Subject: [PATCH 050/222] toradex: tdx-cfg-clock: add new i.mx 8m mini/plus skus Add new i.MX 8M Mini/Plus SKUs to ConfigBlock handling: 0058: Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT 0059: Verdin iMX8M Mini Quad 2GB IT 0060: Verdin iMX8M Mini DualLite 1GB WB IT 0061: Verdin iMX8M Plus Quad 2GB Rename existing SKU (use correct one): Verdin iMX8M Nano SoloLite 1GB -> Verdin iMX8M Nano Quad 1GB Wi-Fi Signed-off-by: Igor Opaniuk Signed-off-by: Marcel Ziswiler --- board/toradex/common/tdx-cfg-block.c | 42 ++++++++++++++++++++-------- board/toradex/common/tdx-cfg-block.h | 8 ++++-- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index bf27b2fa66..475abf78a7 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -16,7 +16,8 @@ defined(CONFIG_TARGET_COLIBRI_IMX6) || \ defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ - defined(CONFIG_TARGET_VERDIN_IMX8MN) + defined(CONFIG_TARGET_VERDIN_IMX8MN) || \ + defined(CONFIG_TARGET_VERDIN_IMX8MP) #include #else #define is_cpu_type(cpu) (0) @@ -137,8 +138,12 @@ const char * const toradex_modules[] = { [53] = "Apalis iMX8 QuadXPlus 2GB ECC IT", [54] = "Apalis iMX8 DualXPlus 1GB", [55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT", - [56] = "Verdin iMX8M Nano SoloLite 1GB", /* not currently on sale */ + [56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on sale */ [57] = "Verdin iMX8M Mini DualLite 1GB", + [58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT", + [59] = "Verdin iMX8M Mini Quad 2GB IT", + [60] = "Verdin iMX8M Mini DualLite 1GB WB IT", + [61] = "Verdin iMX8M Plus Quad 2GB", }; const char * const toradex_carrier_boards[] = { @@ -361,21 +366,15 @@ static int get_cfgblock_interactive(void) if (cpu_is_pxa27x()) sprintf(message, "Is the module the 312 MHz version? [y/N] "); -#if !defined(CONFIG_TARGET_VERDIN_IMX8MM) || !defined(CONFIG_TARGET_VERDIN_IMX8MN) - else - sprintf(message, "Is the module an IT version? [y/N] "); - - len = cli_readline(message); - it = console_buffer[0]; -#else else it = 'y'; -#endif #if defined(CONFIG_TARGET_APALIS_IMX8) || \ defined(CONFIG_TARGET_APALIS_IMX8X) || \ defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \ - defined(CONFIG_TARGET_COLIBRI_IMX8X) + defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ + defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ + defined(CONFIG_TARGET_VERDIN_IMX8MP) sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] "); len = cli_readline(message); wb = console_buffer[0]; @@ -429,7 +428,7 @@ static int get_cfgblock_interactive(void) else if (is_cpu_type(MXC_CPU_IMX8MMDL)) tdx_hw_tag.prodid = VERDIN_IMX8MMDL; else if (is_cpu_type(MXC_CPU_IMX8MN)) - tdx_hw_tag.prodid = VERDIN_IMX8MNSL; + tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT; else if (is_cpu_type(MXC_CPU_IMX8QM)) { if (it == 'y' || it == 'Y') { if (wb == 'y' || wb == 'Y') @@ -465,6 +464,25 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX8DX; } #endif + } else if (is_cpu_type(MXC_CPU_IMX8MM)) { + if (is_cpu_type(MXC_CPU_IMX8MMDL)) { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MMDL; + } else { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT; + } + } else if (is_cpu_type(MXC_CPU_IMX8MN)) { + tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT; + } else if (is_cpu_type(MXC_CPU_IMX8MP)) { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MPQ; } else if (!strcmp("tegra20", soc)) { if (it == 'y' || it == 'Y') if (gd->ram_size == 0x10000000) diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 8f91d9aec6..9debd5f046 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -75,9 +75,13 @@ enum { COLIBRI_IMX8DX, APALIS_IMX8QXP, APALIS_IMX8DXP, - VERDIN_IMX8MMQ_WIFI_BT_IT, - VERDIN_IMX8MNSL, + VERDIN_IMX8MMQ_WIFI_BT_IT, /* 55 */ + VERDIN_IMX8MNQ_WIFI_BT, VERDIN_IMX8MMDL, + VERDIN_IMX8MPQ_WIFI_BT_IT, + VERDIN_IMX8MMQ_IT, + VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */ + VERDIN_IMX8MPQ, }; enum { From 5d89afe27f3872a526db7e6e5614ba3b9093e46b Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 28 Oct 2020 11:58:09 +0200 Subject: [PATCH 051/222] pca9450a: fix i2c address The I2C address is 0x25, not 0x35. This according to the datasheet and tests with a PCA9450A. Signed-off-by: Max Krummenacher Reviewed-by: Jaehoon Chung --- drivers/power/pmic/pca9450.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 0c9d9a366e..c7f8b80954 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -80,7 +80,7 @@ static struct dm_pmic_ops pca9450_ops = { }; static const struct udevice_id pca9450_ids[] = { - { .compatible = "nxp,pca9450a", .data = 0x35, }, + { .compatible = "nxp,pca9450a", .data = 0x25, }, { .compatible = "nxp,pca9450b", .data = 0x25, }, { } }; From 8f9abdf4d440baa87c41c15851e3f9ae8a30c07c Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Wed, 28 Oct 2020 11:58:10 +0200 Subject: [PATCH 052/222] power: pmic: add SPL_DM_PMIC_PCA9450 symbol to Kconfig Add SPL_DM_PMIC_PCA9450 symbol to Kconfig. Signed-off-by: Igor Opaniuk Reviewed-by: Jaehoon Chung --- drivers/power/pmic/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index a62aa38054..7d51510d1b 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -98,6 +98,13 @@ config DM_PMIC_PCA9450 This config enables implementation of driver-model pmic uclass features for PMIC PCA9450. The driver implements read/write operations. +config SPL_DM_PMIC_PCA9450 + bool "Enable Driver Model for PMIC PCA9450" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC PCA9450 in SPL. The driver implements read/write operations. + config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" depends on DM_PMIC From caafc6c497db9fba3007c537e92cf3b184f8c1e3 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 28 Oct 2020 11:58:11 +0200 Subject: [PATCH 053/222] ARM: dts: imx8mm-verdin: follow changed pmic The used PMIC has been changed from RHOM BD71837 to NXP PCA9450A. Adjust the device tree accordingly. Remove the old ADC node as the ADC has been changed and has no longer a separate power rail. Signed-off-by: Max Krummenacher Signed-off-by: Igor Opaniuk Acked-by: Marcel Ziswiler Reviewed-by: Oleksandr Suvorov --- arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 5 +- arch/arm/dts/imx8mm-verdin.dts | 168 +++++++++++++------------ 2 files changed, 87 insertions(+), 86 deletions(-) diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi index fe6bb9bf03..249b0f8f66 100644 --- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -2,7 +2,6 @@ /* * Copyright 2020 Toradex */ - / { wdt-reboot { compatible = "wdt-reboot"; @@ -90,11 +89,11 @@ u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { +&{/soc@0/bus@30800000/i2c@30a20000/pmic} { u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { +&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index 1c67c08c88..fb0756d6e1 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -203,115 +203,123 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic@4b { - compatible = "rohm,bd71840", "rohm,bd71837"; - bd71837,pmic-buck2-uses-i2c-dvs; - bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ - gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; - /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + /* Assembled on V1.1 HW and later */ + pmic { + reg = <0x25>; + u-boot,dm-spl; + compatible = "nxp,pca9450a"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; - reg = <0x4b>; - - gpo { - rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ - }; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { - buck1_reg: BUCK1 { - regulator-always-on; - regulator-boot-on; + u-boot,dm-spl; + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; regulator-compatible = "buck1"; - regulator-max-microvolt = <1300000>; - regulator-min-microvolt = <700000>; - regulator-ramp-delay = <1250>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; }; - buck2_reg: BUCK2 { - regulator-always-on; - regulator-boot-on; + buck2_reg: regulator@1 { + reg = <1>; regulator-compatible = "buck2"; - regulator-max-microvolt = <1300000>; - regulator-min-microvolt = <700000>; - regulator-ramp-delay = <1250>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; }; - buck5_reg: BUCK5 { - regulator-always-on; + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; regulator-compatible = "buck5"; - regulator-max-microvolt = <1350000>; - regulator-min-microvolt = <700000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; }; - buck6_reg: BUCK6 { - regulator-always-on; - regulator-boot-on; + buck6_reg: regulator@5 { + reg = <5>; regulator-compatible = "buck6"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; }; - buck7_reg: BUCK7 { - regulator-always-on; - regulator-boot-on; - regulator-compatible = "buck7"; - regulator-max-microvolt = <1995000>; - regulator-min-microvolt = <1605000>; - }; - - buck8_reg: BUCK8 { - regulator-always-on; - regulator-boot-on; - regulator-compatible = "buck8"; - regulator-max-microvolt = <1400000>; - regulator-min-microvolt = <800000>; - }; - - ldo1_reg: LDO1 { - regulator-always-on; - regulator-boot-on; + ldo1_reg: regulator@6 { + reg = <6>; regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; }; - ldo2_reg: LDO2 { - regulator-always-on; - regulator-boot-on; + ldo2_reg: regulator@7 { + reg = <7>; regulator-compatible = "ldo2"; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; }; - ldo3_reg: LDO3 { - regulator-always-on; - regulator-boot-on; + ldo3_reg: regulator@8 { + reg = <8>; regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-always-on; - regulator-boot-on; + ldo4_reg: regulator@9 { + reg = <9>; regulator-compatible = "ldo4"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <900000>; - }; - - ldo5_reg: LDO5 { - regulator-compatible = "ldo5"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; - ldo6_reg: LDO6 { - regulator-always-on; - regulator-boot-on; - regulator-compatible = "ldo6"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <900000>; + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; }; + }; }; @@ -321,12 +329,6 @@ reg = <0x32>; }; - adc@34 { - compatible = "maxim,max11607"; - reg = <0x34>; - vcc-supply = <&ldo5_reg>; - }; - eeprom_module: eeprom@50 { compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; From 7d43807d6c7a8bac56cbca27b9e302eda7db0f6f Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 28 Oct 2020 11:58:12 +0200 Subject: [PATCH 054/222] verdin-imx8mm: spl: switch to pca9450 pmic V1.1A HW switched the PMIC from BD71837 to PCA9450. - Disable combined DVS in PCA9450_BUCK123_DVS. - Increase DDR Voltage to 0.95V as we use a 1.5GHz RAM. - Configure WDOG_B behaviour. Signed-off-by: Max Krummenacher Signed-off-by: Igor Opaniuk Acked-by: Marcel Ziswiler Reviewed-by: Oleksandr Suvorov --- board/toradex/verdin-imx8mm/spl.c | 48 +++++++++++++++---------------- configs/verdin-imx8mm_defconfig | 2 +- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index cc78c5666b..9562cdeb35 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -21,12 +21,16 @@ #include #include #include +#include #include +#include #include #include DECLARE_GLOBAL_DATA_PTR; +#define I2C_PMIC_BUS_ID 1 + int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -101,33 +105,27 @@ int power_init_board(void) struct udevice *dev; int ret; - ret = pmic_get("pmic@4b", &dev); - if (ret == -ENODEV) { - puts("No pmic\n"); + if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) { + ret = pmic_get("pmic", &dev); + if (ret == -ENODEV) { + puts("No pmic found\n"); + return ret; + } + + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */ + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + return 0; } - if (ret != 0) - return ret; - - /* decrease RESET key long push time from the default 10s to 10ms */ - pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); - - /* unlock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); - - /* increase VDD_SOC to typical value 0.85v before first DRAM access */ - pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); - - /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ - pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); - -#ifndef CONFIG_IMX8M_LPDDR4 - /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ - pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); -#endif - - /* lock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); return 0; } diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 836c6f6c31..ea0b5978f1 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -90,7 +90,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y -CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y From 423ca964c3d8829d68676b367b773926d72cd24e Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 28 Oct 2020 11:58:13 +0200 Subject: [PATCH 055/222] verdin-imx8mm: implement hardware version detection And select the correct devicetree accordingly by setting the variant environment variable. Signed-off-by: Igor Opaniuk Signed-off-by: Max Krummenacher Acked-by: Marcel Ziswiler --- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 66950ed218..9c6f35e778 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -8,12 +8,22 @@ #include #include #include +#include #include #include #include +#include "../common/tdx-cfg-block.h" + DECLARE_GLOBAL_DATA_PTR; +#define I2C_PMIC 0 + +enum pcb_rev_t { + PCB_VERSION_1_0, + PCB_VERSION_1_1 +}; + #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { @@ -104,8 +114,69 @@ int board_mmc_get_env_dev(int devno) return devno; } +static enum pcb_rev_t get_pcb_revision(void) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + u8 is_bd71837 = 0; + + ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PMIC, &bus); + if (!ret) + ret = dm_i2c_probe(bus, 0x4b, 0, &i2c_dev); + if (!ret) + ret = dm_i2c_read(i2c_dev, 0x0, &is_bd71837, 1); + + /* BD71837_REV, High Nibble is major version, fix 1010 */ + is_bd71837 = !ret && ((is_bd71837 & 0xf0) == 0xa0); + return is_bd71837 ? PCB_VERSION_1_0 : PCB_VERSION_1_1; +} + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + int is_wifi = 0; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a + * module with Wi-Fi/Bluetooth make sure we use the -wifi + * device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT); + } + + switch (get_pcb_revision()) { + case PCB_VERSION_1_0: + printf("Detected a V1.0 module\n"); + if (is_wifi) + strncpy(&variant[0], "wifi", sizeof(variant)); + else + strncpy(&variant[0], "nonwifi", sizeof(variant)); + break; + default: + if (is_wifi) + strncpy(&variant[0], "wifi-v1.1", sizeof(variant)); + else + strncpy(&variant[0], "nonwifi-v1.1", sizeof(variant)); + break; + } + + if (strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + env_save(); + } +} + int board_late_init(void) { + select_dt_from_module_version(); + return 0; } From b8eecbac6a7ad339baf0446f333ce7cc43921b40 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 28 Oct 2020 11:58:14 +0200 Subject: [PATCH 056/222] verdin-imx8mm: spl: enable pca9450 i2c level translator Enable PCA9450 i2c level translator, as this is used for the on module ADC. Signed-off-by: Max Krummenacher Acked-by: Marcel Ziswiler Reviewed-by: Oleksandr Suvorov --- board/toradex/verdin-imx8mm/spl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 9562cdeb35..72e2e09e25 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -124,6 +124,8 @@ int power_init_board(void) /* set WDOG_B_CFG to cold reset */ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); + return 0; } From 2a1a2559fbc7f629fbf80a5478bcc252b9cd25b2 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 28 Oct 2020 11:58:15 +0200 Subject: [PATCH 057/222] toradex: tdx-cfg-clock: fix i.mx 8m mini interactive Now with them first Verdin iMX8M Mini DualLite modules in for bring-up we got clarity how is_cpu_type() actually behaves. Signed-off-by: Marcel Ziswiler Reviewed-by: Oleksandr Suvorov --- board/toradex/common/tdx-cfg-block.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 475abf78a7..adab0a0802 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -423,12 +423,6 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX7D; else if (!strcmp("imx7s", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7S; - else if (is_cpu_type(MXC_CPU_IMX8MM)) - tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT; - else if (is_cpu_type(MXC_CPU_IMX8MMDL)) - tdx_hw_tag.prodid = VERDIN_IMX8MMDL; - else if (is_cpu_type(MXC_CPU_IMX8MN)) - tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT; else if (is_cpu_type(MXC_CPU_IMX8QM)) { if (it == 'y' || it == 'Y') { if (wb == 'y' || wb == 'Y') @@ -464,18 +458,16 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX8DX; } #endif + } else if (is_cpu_type(MXC_CPU_IMX8MMDL)) { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MMDL; } else if (is_cpu_type(MXC_CPU_IMX8MM)) { - if (is_cpu_type(MXC_CPU_IMX8MMDL)) { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT; - else - tdx_hw_tag.prodid = VERDIN_IMX8MMDL; - } else { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT; - else - tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT; - } + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT; + else + tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT; } else if (is_cpu_type(MXC_CPU_IMX8MN)) { tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT; } else if (is_cpu_type(MXC_CPU_IMX8MP)) { From 72a1b9a977e8636b9c364f2cbf21371afe143c68 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 28 Oct 2020 11:58:16 +0200 Subject: [PATCH 058/222] verdin-imx8mm: automatic ram size detection Implement board_phys_sdram_size() to automatically detect Verdin iMX8M Mini DualLite 1GB vs. Verdin iMX8M Mini Quad 2GB. Note: This only works if we keep using similar RAM chips! Signed-off-by: Marcel Ziswiler Acked-by: Oleksandr Suvorov --- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 9c6f35e778..7cfae8767c 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -180,6 +180,16 @@ int board_late_init(void) return 0; } +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { From bc479b211876d60eca9a6f991971e5241ffa4037 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 25 Sep 2020 08:08:35 -0700 Subject: [PATCH 059/222] imx8m: fix cache setup for dynamic sdram size the mem_map structure containing the size of SDRAM is used in various cache functions in cache_v8.c thus we need to update it with the sdram size the board is configured with as well. Without this the cache functions do not get setup properly and can hang in the case where a board reports more SDRAM than defined in PHYS_SDRAM_SIZE. Signed-off-by: Tim Harvey --- arch/arm/mach-imx/imx8m/soc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 9bca5bf972..5df8e17510 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -210,6 +210,9 @@ int dram_init(void) else gd->ram_size = sdram_size; + /* also update the SDRAM size in the mem_map used externally */ + imx8m_mem_map[5].size = sdram_size; + #ifdef PHYS_SDRAM_2_SIZE gd->ram_size += PHYS_SDRAM_2_SIZE; #endif From 3d1103cefceccdc73c4fdda61910225e1fd002e0 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 22 Oct 2020 11:21:37 +0300 Subject: [PATCH 060/222] ARM: dts: fsl-imx8qxp-apalis: add initial device tree Introduce initial hierarchy of device trees for Apalis iMX8X System on Module. Signed-off-by: Igor Opaniuk Acked-by: Oleksandr Suvorov --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi | 139 ++++++++++ arch/arm/dts/fsl-imx8qxp-apalis.dts | 278 ++++++++++++++++++++ 3 files changed, 418 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-apalis.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 089dfb73a3..7cefce689f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ + fsl-imx8qxp-apalis.dtb \ fsl-imx8qxp-mek.dtb \ imx8-deneb.dtb \ imx8-giedi.dtb diff --git a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi new file mode 100644 index 0000000000..e41911a04a --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&{/imx8qx-pm} { + + u-boot,dm-pre-proper; +}; + +&mu { + u-boot,dm-pre-proper; +}; + +&clk { + u-boot,dm-pre-proper; +}; + +&iomuxc { + u-boot,dm-pre-proper; +}; + +&pd_lsio { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio0 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio1 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio2 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio3 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio4 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio5 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio6 { + u-boot,dm-pre-proper; +}; + +&pd_lsio_gpio7 { + u-boot,dm-pre-proper; +}; + +&pd_dma { + u-boot,dm-pre-proper; +}; + +&pd_dma_lpuart0 { + u-boot,dm-pre-proper; +}; + +&pd_dma_lpuart3 { + u-boot,dm-pre-proper; +}; + +&pd_conn { + u-boot,dm-pre-proper; +}; + +&pd_conn_sdch0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_sdch1 { + u-boot,dm-pre-proper; +}; + +&pd_conn_sdch2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_enet0 { + u-boot,dm-pre-proper; +}; + +&gpio0 { + u-boot,dm-pre-proper; +}; + +&gpio1 { + u-boot,dm-pre-proper; +}; + +&gpio2 { + u-boot,dm-pre-proper; +}; + +&gpio3 { + u-boot,dm-pre-proper; +}; + +&gpio4 { + u-boot,dm-pre-proper; +}; + +&gpio5 { + u-boot,dm-pre-proper; +}; + +&gpio6 { + u-boot,dm-pre-proper; +}; + +&gpio7 { + u-boot,dm-pre-proper; +}; + +&lpuart3 { + u-boot,dm-pre-proper; +}; + +&lpuart0 { + u-boot,dm-pre-proper; +}; + +&usdhc1 { + u-boot,dm-pre-proper; + /delete-property/ assigned-clock-parents; +}; + +&usdhc2 { + u-boot,dm-pre-proper; + /delete-property/ assigned-clock-parents; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts new file mode 100644 index 0000000000..6bd231b283 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-apalis.dts @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" +#include "fsl-imx8qxp-apalis-u-boot.dtsi" + +/ { + model = "Toradex Apalis iMX8X"; + compatible = "toradex,apalis-imx8x", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP1,115200"; + stdout-path = &lpuart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>; + + apalis-imx8x { + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* SODIMM 118 */ + SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* SODIMM 112 */ + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 + /* On-module ETH_RESET# */ + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x06000020 + /* On-module ETH_INT# */ + SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21 + >; + }; + + /* Apalis BKL_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 286 */ + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + /* Apalis USBO1_EN */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x41 /* SODIMM 274 */ + >; + }; + + /* Apalis RESET_MOCI# */ + pinctrl_reset_moci: gpioresetmocigrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_usdhc2_gpio: mmc1gpiogrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* SODIMM 164 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* SODIMM 164 */ + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x40 /* SODIMM 84 */ + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 154 */ + SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 150 */ + SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 160 */ + SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 162 */ + SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 144 */ + SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + }; +}; + +/* Apalis Gigabit LAN */ +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + disable-wp; + status = "okay"; +}; From a51fdba3fa1e18f5b3b294663949723f220576ba Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 22 Oct 2020 11:21:38 +0300 Subject: [PATCH 061/222] board: toradex: add apalis-imx8x 2gb wb it v1.1a module support This commit adds initial support for the Toradex Apalis iMX8X 2GB WB IT V1.1A System on Module support [1]. Boot log: U-Boot 2020.10-02940-g894aebb7e8-dirty (Oct 22 2020 - 09:43:57 +0300) CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 30C DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial@5a070000 Out: serial@5a070000 Err: serial@5a070000 Model: Toradex Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT V1.1A, Serial# 06617018 Net: eth0: ethernet@5b040000 [PRIME] Hit any key to stop autoboot: 0 Functionality wise the following is known to be working: - eMMC and MMC/SD card - Ethernet (*) - GPIOs - I2C Unfortunately, there is no USB functionality for the i.MX 8QXP as of yet. * With the SCU FW from the latest Toradex BSP 5.0.0 (SCU FW 1.5.1) ETH PHY encounters bring up problems after reset, this will be fixed soon on SCU FW side. [1] https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8x Signed-off-by: Igor Opaniuk Acked-by: Oleksandr Suvorov --- arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/apalis-imx8x/Kconfig | 30 ++++ board/toradex/apalis-imx8x/MAINTAINERS | 10 ++ board/toradex/apalis-imx8x/Makefile | 6 + .../apalis-imx8x/apalis-imx8x-imximage.cfg | 24 +++ board/toradex/apalis-imx8x/apalis-imx8x.c | 131 +++++++++++++++ configs/apalis-imx8x_defconfig | 77 +++++++++ include/configs/apalis-imx8x.h | 149 ++++++++++++++++++ 8 files changed, 433 insertions(+) create mode 100644 board/toradex/apalis-imx8x/Kconfig create mode 100644 board/toradex/apalis-imx8x/MAINTAINERS create mode 100644 board/toradex/apalis-imx8x/Makefile create mode 100644 board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg create mode 100644 board/toradex/apalis-imx8x/apalis-imx8x.c create mode 100644 configs/apalis-imx8x_defconfig create mode 100644 include/configs/apalis-imx8x.h diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9d1f73dfc7..04b9729109 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -65,6 +65,11 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP +config TARGET_APALIS_IMX8X + bool "Support Apalis iMX8X module" + select BOARD_LATE_INIT + select IMX8QXP + config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT @@ -98,6 +103,7 @@ source "board/freescale/imx8qxp_mek/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" +source "board/toradex/apalis-imx8x/Kconfig" source "board/siemens/capricorn/Kconfig" config IMX_SNVS_SEC_SC diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig new file mode 100644 index 0000000000..ee61e09736 --- /dev/null +++ b/board/toradex/apalis-imx8x/Kconfig @@ -0,0 +1,30 @@ +if TARGET_APALIS_IMX8X + +config SYS_BOARD + default "apalis-imx8x" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "apalis-imx8x" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS new file mode 100644 index 0000000000..fbf9379931 --- /dev/null +++ b/board/toradex/apalis-imx8x/MAINTAINERS @@ -0,0 +1,10 @@ +Apalis iMX8X +M: Igor Opaniuk +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: arch/arm/dts/fsl-imx8x-apalis.dts +F: arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi +F: board/toradex/apalis-imx8x/ +F: configs/apalis-imx8x_defconfig +F: doc/board/toradex/apalis-imx8x.rst +F: include/configs/apalis-imx8x.h diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile new file mode 100644 index 0000000000..9d6e85b742 --- /dev/null +++ b/board/toradex/apalis-imx8x/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 Toradex +# + +obj-y += apalis-imx8x.o diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg new file mode 100644 index 0000000000..58c62d0a65 --- /dev/null +++ b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + * + * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND mx8qx-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-apalis-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c new file mode 100644 index 0000000000..9f00f26cfe --- /dev/null +++ b/board/toradex/apalis-imx8x/apalis-imx8x.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Toradex + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart1_pads[] = { + SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate; + sc_err_t err = 0; + + /* + * This works around that having only UART3 up the baudrate is 1.2M + * instead of 115.2k. Set UART0 clock root to 80 MHz + */ + rate = 80000000; + err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); + if (err != SC_ERR_NONE) + return 0; + + /* Set UART3 clock root to 80 MHz and enable it */ + rate = SC_80MHZ; + err = sc_pm_setup_uart(SC_R_UART_1, rate); + if (err != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int checkboard(void) +{ + puts("Model: Toradex Apalis iMX8X\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */ + env_set("board_name", "Apalis iMX8X"); +#endif + + return 0; +} diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig new file mode 100644 index 0000000000..e6aa575380 --- /dev/null +++ b/configs/apalis-imx8x_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_TARGET_APALIS_IMX8X=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Apalis iMX8X # " +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h new file mode 100644 index 0000000000..db31c210f5 --- /dev/null +++ b/include/configs/apalis-imx8x.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + */ + +#ifndef __APALIS_IMX8X_H +#define __APALIS_IMX8X_H + +#include +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5b010000 +#define USDHC2_BASE_ADDR 0x5b020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define FEC_ENET_ENABLE_TXC_DELAY +#define FEC_ENET_ENABLE_RXC_DELAY + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r=0x80280000\0" \ + "fdt_addr_r=0x83100000\0" \ + "ramdisk_addr_r=0x8a000000\0" \ + "scriptaddr=0x83200000\0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define MFG_NAND_PARTITION "" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs ${consoleargs} " \ + "rdinit=/linuxrc g_mass_storage.stall=0 " \ + "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ + "g_mass_storage.idProduct=0x37FF " \ + "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ + "${vidargs} clk_ignore_unused\0" \ + "initrd_addr=0x83800000\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ + "${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + BOOTENV \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "boot_file=Image\0" \ + "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ + "fdt_file=imx8qxp-apalis-eval.dtb\0" \ + "fdtfile=imx8qxp-apalis-eval.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "mmcargs=setenv bootargs ${consoleargs} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs ${consoleargs} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "${vidargs}\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \ + "${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" \ + "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x89000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE 0x5b040000 +#define CONFIG_FEC_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME "eth0" +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define PHY_ANEG_TIMEOUT 20000 + +#endif /* __APALIS_IMX8X_H */ From 3730106cf0dcc0630ff37c138e9a0d46739e2e51 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 22 Oct 2020 11:21:39 +0300 Subject: [PATCH 062/222] doc: board: apalis-imx8x: add documentation This documents the u-boot build and deployment procedure. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- doc/board/toradex/apalix-imx8x.rst | 74 ++++++++++++++++++++++++++++++ doc/board/toradex/index.rst | 1 + 2 files changed, 75 insertions(+) create mode 100644 doc/board/toradex/apalix-imx8x.rst diff --git a/doc/board/toradex/apalix-imx8x.rst b/doc/board/toradex/apalix-imx8x.rst new file mode 100644 index 0000000000..ce7dde8d00 --- /dev/null +++ b/doc/board/toradex/apalix-imx8x.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Apalis iMX8X V1.1A Module +========================== + +Quick Start +----------- + +- Build the ARM trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Load U-Boot binary using uuu +- Flash U-Boot binary into the eMMC +- Boot + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone -b toradex_imx_5.4.24_2.1.0 http://git.toradex.com/cgit/imx-atf.git + $ cd imx-atf/ + $ make PLAT=imx8qx bl31 + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/blob/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.6.3.bin + $ chmod +x imx-seco-3.6.3.bin + $ ./imx-seco-3.6.3.bin + +Copy the following binaries to the U-Boot folder: + +.. code-block:: bash + + $ cp imx-atf/build/imx8qx/release/bl31.bin . + $ cp imx-seco-3.6.3/firmware/seco/mx8qxb0-ahab-container.img mx8qx-ahab-container.imx8_defconfig + +Build U-Boot +------------ +.. code-block:: bash + + $ make apalis-imx8x_defconfig + $ make u-boot-dtb.imx + +Load the U-Boot Binary Using UUU +-------------------------------- + +Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``: + +https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases + +Put the module into USB recovery aka serial downloader mode, connect USB device +to your host and execute uuu: + +.. code-block:: bash + + sudo ./uuu u-boot/u-boot-dtb.imx + +Flash the U-Boot Binary into the eMMC +------------------------------------- + +Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area +partition and boot: + +.. code-block:: bash + + load mmc 1:1 $loadaddr u-boot-dtb.imx + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + mmc dev 0 1 + mmc write ${loadaddr} 0x0 ${blkcnt} diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 16b5a0770d..abba648f86 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -7,6 +7,7 @@ Toradex :maxdepth: 2 apalix-imx8 + apalix-imx8x colibri_imx7 colibri-imx8x verdin-imx8mm From 2f36a693e34bd4bc6ab05d2c6e803aa9eb10d4df Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 22 Oct 2020 11:21:40 +0300 Subject: [PATCH 063/222] imx8: allow overriding memory layout Introduce weak function board_mem_get_layout() which allows overriding the memory layout from board code in runtime, useful for handling different SKU versions. Signed-off-by: Marcel Ziswiler Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- arch/arm/include/asm/mach-imx/sys_proto.h | 5 ++ arch/arm/mach-imx/imx8/cpu.c | 96 ++++++++++++++++------- 2 files changed, 72 insertions(+), 29 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 5f0c1ae218..43eae6d796 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -183,6 +183,11 @@ void init_src(void); void init_snvs(void); void imx_wdog_disable_powerdown(void); +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size); + int arch_auxiliary_core_check_up(u32 core_id); int board_mmc_get_env_dev(int devno); diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 38b2c0926f..911d6a51d1 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -260,14 +260,30 @@ static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, return -EINVAL; } +__weak void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + phys_size_t get_effective_memsize(void) { sc_rm_mr_t mr; sc_faddr_t start, end, end1, start_aligned; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; int err; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -277,29 +293,35 @@ phys_size_t get_effective_memsize(void) continue; /* Find the memory region runs the U-Boot */ - if (start >= PHYS_SDRAM_1 && start <= end1 && + if (start >= phys_sdram_1_start && start <= end1 && (start <= CONFIG_SYS_TEXT_BASE && end >= CONFIG_SYS_TEXT_BASE)) { - if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + - PHYS_SDRAM_1_SIZE)) - return (end - PHYS_SDRAM_1 + 1); + if ((end + 1) <= + ((sc_faddr_t)phys_sdram_1_start + + phys_sdram_1_size)) + return (end - phys_sdram_1_start + 1); else - return PHYS_SDRAM_1_SIZE; + return phys_sdram_1_size; } } } - return PHYS_SDRAM_1_SIZE; + return phys_sdram_1_size; } int dram_init(void) { sc_rm_mr_t mr; sc_faddr_t start, end, end1, end2; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; int err; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; - end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; + end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -308,12 +330,13 @@ int dram_init(void) if (start > end) continue; - if (start >= PHYS_SDRAM_1 && start <= end1) { + if (start >= phys_sdram_1_start && start <= end1) { if ((end + 1) <= end1) gd->ram_size += end - start + 1; else gd->ram_size += end1 - start; - } else if (start >= PHYS_SDRAM_2 && start <= end2) { + } else if (start >= phys_sdram_2_start && + start <= end2) { if ((end + 1) <= end2) gd->ram_size += end - start + 1; else @@ -324,8 +347,8 @@ int dram_init(void) /* If error, set to the default value */ if (!gd->ram_size) { - gd->ram_size = PHYS_SDRAM_1_SIZE; - gd->ram_size += PHYS_SDRAM_2_SIZE; + gd->ram_size = phys_sdram_1_size; + gd->ram_size += phys_sdram_2_size; } return 0; } @@ -358,11 +381,15 @@ int dram_init_banksize(void) sc_rm_mr_t mr; sc_faddr_t start, end, end1, end2; int i = 0; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; int err; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; - end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; + end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -370,7 +397,7 @@ int dram_init_banksize(void) if (start > end) /* Small memory region, no use it */ continue; - if (start >= PHYS_SDRAM_1 && start <= end1) { + if (start >= phys_sdram_1_start && start <= end1) { gd->bd->bi_dram[i].start = start; if ((end + 1) <= end1) @@ -381,7 +408,7 @@ int dram_init_banksize(void) dram_bank_sort(i); i++; - } else if (start >= PHYS_SDRAM_2 && start <= end2) { + } else if (start >= phys_sdram_2_start && start <= end2) { gd->bd->bi_dram[i].start = start; if ((end + 1) <= end2) @@ -398,10 +425,10 @@ int dram_init_banksize(void) /* If error, set to the default value */ if (!i) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[0].start = phys_sdram_1_start; + gd->bd->bi_dram[0].size = phys_sdram_1_size; + gd->bd->bi_dram[1].start = phys_sdram_2_start; + gd->bd->bi_dram[1].size = phys_sdram_2_size; } return 0; @@ -411,11 +438,16 @@ static u64 get_block_attrs(sc_faddr_t addr_start) { u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; - if ((addr_start >= PHYS_SDRAM_1 && - addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) || - (addr_start >= PHYS_SDRAM_2 && - addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); + + if ((addr_start >= phys_sdram_1_start && + addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) || + (addr_start >= phys_sdram_2_start && + addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size))) return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); return attr; @@ -424,14 +456,20 @@ static u64 get_block_attrs(sc_faddr_t addr_start) static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) { sc_faddr_t end1, end2; + u64 phys_sdram_1_start, phys_sdram_1_size; + u64 phys_sdram_2_start, phys_sdram_2_size; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; - end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, + &phys_sdram_2_start, &phys_sdram_2_size); - if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) { + + end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; + end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; + + if (addr_start >= phys_sdram_1_start && addr_start <= end1) { if ((addr_end + 1) > end1) return end1 - addr_start; - } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) { + } else if (addr_start >= phys_sdram_2_start && addr_start <= end2) { if ((addr_end + 1) > end2) return end2 - addr_start; } From 90311be09f653499a1f4bd8198955ae79e00b51c Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 22 Oct 2020 11:21:41 +0300 Subject: [PATCH 064/222] apalis-imx8: add implementation for board_mem_get_layout Add implementation of board_mem_get_layout for overriding the memory layout. Signed-off-by: Igor Opaniuk Acked-by: Oleksandr Suvorov --- board/toradex/apalis-imx8/apalis-imx8.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 9263b0f51f..2ed66261d2 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -37,6 +37,29 @@ static void setup_iomux_uart(void) imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + u32 is_quadplus = 0, val = 0; + sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + + if (scierr == SC_ERR_NONE) { + /* QP has one A72 core disabled */ + is_quadplus = ((val >> 4) & 0x3) != 0x0; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + if (is_quadplus) + /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + *phys_sdram_2_size = 0x0UL; + else + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + int board_early_init_f(void) { sc_pm_clock_rate_t rate = SC_80MHZ; From 5d39967dcfcea5ff5d07c32b92e224c873f63155 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 22 Oct 2020 11:21:42 +0300 Subject: [PATCH 065/222] apalis-imx8x: add implementation for board_mem_get_layout Add implementation of board_mem_get_layout for overriding the memory layout. Signed-off-by: Igor Opaniuk --- board/toradex/apalis-imx8x/apalis-imx8x.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c index 9f00f26cfe..739d2e5155 100644 --- a/board/toradex/apalis-imx8x/apalis-imx8x.c +++ b/board/toradex/apalis-imx8x/apalis-imx8x.c @@ -37,6 +37,29 @@ static void setup_iomux_uart(void) imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + u32 is_dualx = 0, val = 0; + sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + + if (scierr == SC_ERR_NONE) { + /* DX has two A35 cores disabled */ + is_dualx = (val & 0xf) != 0x0; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + if (is_dualx) + /* Our DX based SKUs only have 1 GB RAM */ + *phys_sdram_1_size = SZ_1G; + else + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + int board_early_init_f(void) { sc_pm_clock_rate_t rate; From 89f7d08b2af1e2d2d9aefe572623e149cbb44a1c Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 22 Oct 2020 11:21:43 +0300 Subject: [PATCH 066/222] colibri-imx8x: add implementation for board_mem_get_layout Add implementation of board_mem_get_layout for overriding the memory layout. Signed-off-by: Igor Opaniuk --- board/toradex/colibri-imx8x/colibri-imx8x.c | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index f981c11a37..da081e30be 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -39,6 +39,29 @@ static void setup_iomux_uart(void) imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); } +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + u32 is_dualx = 0, val = 0; + sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + + if (scierr == SC_ERR_NONE) { + /* DX has two A35 cores disabled */ + is_dualx = (val & 0xf) != 0x0; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + if (is_dualx) + /* Our DX based SKUs only have 1 GB RAM */ + *phys_sdram_1_size = SZ_1G; + else + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + int board_early_init_f(void) { sc_pm_clock_rate_t rate; From 5115de8d64c9bde382946dfd06eae3496a827239 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Thu, 29 Oct 2020 22:30:30 +0100 Subject: [PATCH 067/222] arm: mvebu: puzzle-m801: Add a maintainer Add Luka Perkov to Puzzle-M801 BOARD MAINTAINERS. Signed-off-by: Luka Kovacic Cc: Luka Perkov Reviewed-by: Stefan Roese --- board/Marvell/mvebu_armada-8k/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS index 15660cd17d..55e485faa9 100644 --- a/board/Marvell/mvebu_armada-8k/MAINTAINERS +++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS @@ -13,6 +13,7 @@ F: configs/mvebu_mcbin-88f8040_defconfig Puzzle-M801 BOARD M: Luka Kovacic +M: Luka Perkov S: Maintained F: configs/mvebu_puzzle-m801-88f8040_defconfig F: arch/arm/dts/armada-8040-puzzle-m801.dts From 28f0cbcdd28c03c44d867a6641d642e97d4704a8 Mon Sep 17 00:00:00 2001 From: Joshua Scott Date: Mon, 9 Nov 2020 10:14:08 +1300 Subject: [PATCH 068/222] arm: mvebu: a38x: Configurable USB2 high-speed impedance threshold Hardware testing of a board using the Armada 385 has shown that an impedance threshold setting of 0x7 performs better in an eye-diagram test than with Marvell's recommended value 0x6. As other boards may still perform better with Marvell's reccomended value, a configuration option is added with a default value of 0x6. Signed-off-by: Joshua Scott Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 6 ++++++ arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 6 +++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 0d8e0922a2..72aee8b3e5 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -30,6 +30,12 @@ config ARMADA_38X select ARMADA_32BIT select HAVE_MVEBU_EFUSE +config ARMADA_38X_HS_IMPEDANCE_THRESH + hex "Armada 38x USB 2.0 High-Speed Impedance Threshold (0x0 - 0x7)" + depends on ARMADA_38X + default 0x6 + range 0x0 0x7 + config ARMADA_XP bool select ARMADA_32BIT diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 2454730e6d..ae2a361104 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -677,9 +677,9 @@ struct op_params usb2_power_up_params[] = { {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, /* Change the High speed impedance threshold */ - {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, - {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, - {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc0008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, + {0xc2008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, + {0xc4008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */ {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, From 338c5ee26af1f047502e2df9d6934ceb8e83e8d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 25 Nov 2020 19:20:07 +0100 Subject: [PATCH 069/222] Revert "arm64: dts: armada-3720-espressobin: split common parts to .dtsi" This reverts commit 03bb6a9b1ed7085794c5f167307273d15c99d3f0. --- arch/arm/dts/armada-3720-espressobin.dts | 164 ++++++++++++++++++++- arch/arm/dts/armada-3720-espressobin.dtsi | 167 ---------------------- 2 files changed, 157 insertions(+), 174 deletions(-) delete mode 100644 arch/arm/dts/armada-3720-espressobin.dtsi diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index 1542d836c0..be67a45870 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -1,20 +1,170 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board + * Device Tree file for Marvell Armada 3720 community board + * (ESPRESSOBin) * Copyright (C) 2016 Marvell * - * Romain Perier + * Gregory CLEMENT + * Konstantin Porotchkin * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; -#include "armada-3720-espressobin.dtsi" +#include "armada-372x.dtsi" / { model = "Globalscale Marvell ESPRESSOBin Board"; compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð0; + i2c0 = &i2c0; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + vcc_sd_reg0: regulator@0 { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-type = "voltage"; + states = <1800000 0x1 + 3300000 0x0>; + gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&comphy { + max-lanes = <3>; + phy0 { + phy-type = ; + phy-speed = ; + }; + + phy1 { + phy-type = ; + phy-speed = ; + }; + + phy2 { + phy-type = ; + phy-speed = ; + }; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&smi_pins>; + phy-mode = "rgmii"; + phy_addr = <0x1>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +/* CON3 */ +&sata { + status = "okay"; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + bus-width = <4>; + cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vcc_sd_reg0>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_quad_pins>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +/* Exported on the micro USB connector CON32 through an FTDI */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +/* CON29 */ +&usb2 { + status = "okay"; +}; + +/* CON31 */ +&usb3 { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + status = "okay"; }; diff --git a/arch/arm/dts/armada-3720-espressobin.dtsi b/arch/arm/dts/armada-3720-espressobin.dtsi deleted file mode 100644 index 05dec89834..0000000000 --- a/arch/arm/dts/armada-3720-espressobin.dtsi +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Device Tree file for Marvell Armada 3720 community board - * (ESPRESSOBin) - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * Konstantin Porotchkin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "armada-372x.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - ethernet0 = ð0; - i2c0 = &i2c0; - spi0 = &spi0; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - vcc_sd_reg0: regulator@0 { - compatible = "regulator-gpio"; - regulator-name = "vcc_sd0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-type = "voltage"; - states = <1800000 0x1 - 3300000 0x0>; - gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; - }; -}; - -&comphy { - max-lanes = <3>; - phy0 { - phy-type = ; - phy-speed = ; - }; - - phy1 { - phy-type = ; - phy-speed = ; - }; - - phy2 { - phy-type = ; - phy-speed = ; - }; -}; - -ð0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&smi_pins>; - phy-mode = "rgmii"; - phy_addr = <0x1>; - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -/* CON3 */ -&sata { - status = "okay"; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - bus-width = <4>; - cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vcc_sd_reg0>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; -}; - -/* Exported on the micro USB connector CON32 through an FTDI */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* CON29 */ -&usb2 { - status = "okay"; -}; - -/* CON31 */ -&usb3 { - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - status = "okay"; -}; From c5c4b69857564bbd3ad64981e2beac458b6d0454 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 25 Nov 2020 19:20:08 +0100 Subject: [PATCH 070/222] Revert "arm64: dts: a3720: add support for espressobin with populated emmc" This reverts commit f1a43c84a960265309fa8365759de271a70c5a7e. --- arch/arm/dts/Makefile | 1 - arch/arm/dts/armada-3720-espressobin-emmc.dts | 44 ------------------- doc/README.marvell | 7 +-- 3 files changed, 2 insertions(+), 50 deletions(-) delete mode 100644 arch/arm/dts/armada-3720-espressobin-emmc.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e2e8a5fb7a..a669835ddb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -204,7 +204,6 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-db.dtb \ armada-3720-espressobin.dtb \ - armada-3720-espressobin-emmc.dtb \ armada-3720-turris-mox.dtb \ armada-3720-uDPU.dtb \ armada-375-db.dtb \ diff --git a/arch/arm/dts/armada-3720-espressobin-emmc.dts b/arch/arm/dts/armada-3720-espressobin-emmc.dts deleted file mode 100644 index 29ccb6a573..0000000000 --- a/arch/arm/dts/armada-3720-espressobin-emmc.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf - */ - -/dts-v1/; - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; - compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; -}; - -/* U11 */ -&sdhci1 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/doc/README.marvell b/doc/README.marvell index 6f05ad4cb1..6fc5ac8a40 100644 --- a/doc/README.marvell +++ b/doc/README.marvell @@ -43,11 +43,8 @@ Build Procedure In order to prevent this, the required device-tree MUST be set during compilation. All device-tree files are located in ./arch/arm/dts/ folder. - For the EspressoBin board with populated eMMC device use - # make DEVICE_TREE=armada-3720-espressobin-emmc - - For other DB boards (MacchiatoBin, EspressoBin without soldered eMMC and 3700 DB board) - compile u-boot with just default device-tree from defconfig using: + For other DB boards (MacchiatoBin, EspressoBin and 3700 DB board) compile u-boot with + just default device-tree from defconfig using: # make From 135973967b6c0fd08e5c0e75e55e3ccae83f5853 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 25 Nov 2020 19:20:09 +0100 Subject: [PATCH 071/222] arm: mvebu: Espressobin: Add support for emmc into dts file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To simplify setup, configuration and compilation of u-boot, define emmc node for all Espressobin boards. Espressobin boards without populated emmc works correctly, just detection and initialization of emmc obviously fails. Code for emmc is extracted from commit f1a43c84a960 ("arm64: dts: a3720: add support for espressobin with populated emmc"). Signed-off-by: Pali Rohár Tested-by: Gérald Kerma --- arch/arm/dts/armada-3720-espressobin.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index be67a45870..96a4b3d95b 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -130,6 +130,28 @@ status = "okay"; }; +/* U11 */ +&sdhci1 { + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,xenon-emmc; + marvell,xenon-tun-count = <9>; + marvell,pad-type = "fixed-1-8v"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + }; +}; + &spi0 { status = "okay"; pinctrl-names = "default"; From 061c6d1b238aa100728b3082fc943e8f679f8e7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 25 Nov 2020 19:20:10 +0100 Subject: [PATCH 072/222] arm: mvebu: Espressobin: Detect presence of emmc at runtime MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Try to initialize emmc in board_late_init() and if it fails then we know that emmc device is not connected. This allows to use in U-Boot just one DTS file for all Espressobin variants and also to correctly set fdtfile env variable for Linux kernel. Signed-off-by: Pali Rohár Tested-by: Gérald Kerma Reviewed-by: Andre Heider --- board/Marvell/mvebu_armada-37xx/board.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 73d69e0388..f67b04b78c 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -83,6 +84,7 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { + struct mmc *mmc_dev; bool ddr4, emmc; if (env_get("fdtfile")) @@ -95,7 +97,9 @@ int board_late_init(void) ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS) & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4; - emmc = of_machine_is_compatible("globalscale,espressobin-emmc"); + /* eMMC is mmc dev num 1 */ + mmc_dev = find_mmc_device(1); + emmc = (mmc_dev && mmc_init(mmc_dev) == 0); if (ddr4 && emmc) env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb"); From 8454cf0d236639f36f465b5b5cf4ef8b572698b6 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 2 Dec 2020 13:39:33 +0200 Subject: [PATCH 073/222] clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypass Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60 have no support for crystal oscillator bypass. Setting this bit might affect the device functionality. Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sam9x60.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index c3235f565d..9e9a643d62 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -382,7 +382,6 @@ static int sam9x60_clk_probe(struct udevice *dev) const char *p[10]; unsigned int cm[10], m[10], *tmpclkmux, *tmpmux; struct clk clk, *c; - bool main_osc_bypass; int ret, muxallocindex = 0, clkmuxallocindex = 0, i; static const struct clk_range r = { 0, 0 }; @@ -440,8 +439,6 @@ static int sam9x60_clk_probe(struct udevice *dev) if (ret) goto fail; - main_osc_bypass = dev_read_bool(dev, "atmel,main-osc-bypass"); - /* Register main rc oscillator. */ c = at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC], clk_names[ID_MAIN_RC]); @@ -453,7 +450,7 @@ static int sam9x60_clk_probe(struct udevice *dev) /* Register main oscillator. */ c = at91_clk_main_osc(base, clk_names[ID_MAIN_OSC], - clk_names[ID_MAIN_XTAL], main_osc_bypass); + clk_names[ID_MAIN_XTAL], false); if (IS_ERR(c)) { ret = PTR_ERR(c); goto fail; From eb381710345beb124be4fcf47c437299bd4991d0 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 20 Nov 2020 15:05:51 +0100 Subject: [PATCH 074/222] doc: board: imx8qm-rom7720-a1.rst: convert readme to reST Convert README to reStructuredText format. Signed-off-by: Oliver Graute --- board/advantech/imx8qm_rom7720_a1/README | 61 ------------------ doc/board/advantech/imx8qm-rom7720-a1.rst | 75 +++++++++++++++++++++++ doc/board/advantech/index.rst | 9 +++ doc/board/index.rst | 1 + 4 files changed, 85 insertions(+), 61 deletions(-) delete mode 100644 board/advantech/imx8qm_rom7720_a1/README create mode 100644 doc/board/advantech/imx8qm-rom7720-a1.rst create mode 100644 doc/board/advantech/index.rst diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README deleted file mode 100644 index 585fde440d..0000000000 --- a/board/advantech/imx8qm_rom7720_a1/README +++ /dev/null @@ -1,61 +0,0 @@ -U-Boot for the NXP i.MX8QM ROM 7720a1 board - -Quick Start -=========== - -- Build the ARM Trusted firmware binary -- Get scfw_tcm.bin and ahab-container.img -- Get imx-mkimage -- Build U-Boot -- Build imx-mkimage -- Flash the binary into the SD card -- Boot - -Get and Build the ARM Trusted firmware -====================================== - -$ git clone https://source.codeaurora.org/external/imx/imx-atf -$ cd imx-atf/ -$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga -$ make PLAT=imx8qm bl31 - -Get scfw_tcm.bin and ahab-container.img -============================== - -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin -$ chmod +x imx-sc-firmware-1.1.bin -$ ./imx-sc-firmware-1.1.bin -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin -$ chmod +x firmware-imx-8.0.bin -$ ./firmware-imx-8.0.bin - -Or use this to avoid running random scripts from the internet, -but note that you must agree to the license the script displays: - -$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 -$ tar -xf imx-sc-firmware-1.1.tar.bz2 -$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) - -$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 -$ tar -xf firmware-imx-8.0.tar.bz2 -$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) - -Build U-Boot -============ - -$ export ATF_LOAD_ADDR=0x80000000 -$ export BL33_LOAD_ADDR=0x80020000 -$ make imx8qm_rom7720_a1_4G_defconfig -$ make u-boot.bin -$ make flash.bin - -Flash the binary into the SD card -================================= - -Burn the flash.bin binary to SD card offset 32KB: - -$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync - -Boot -==== -Set Boot switch SW2: 1100. diff --git a/doc/board/advantech/imx8qm-rom7720-a1.rst b/doc/board/advantech/imx8qm-rom7720-a1.rst new file mode 100644 index 0000000000..bd4be1dbeb --- /dev/null +++ b/doc/board/advantech/imx8qm-rom7720-a1.rst @@ -0,0 +1,75 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the NXP i.MX8QM ROM 7720a1 board +=========================================== + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Build imx-mkimage +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ cd imx-atf/ + $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga + $ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin + $ chmod +x imx-sc-firmware-1.1.bin + $ ./imx-sc-firmware-1.1.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin + $ chmod +x firmware-imx-8.0.bin + $ ./firmware-imx-8.0.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +.. code-block:: bash + + $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 + $ tar -xf imx-sc-firmware-1.1.tar.bz2 + $ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) + + $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 + $ tar -xf firmware-imx-8.0.tar.bz2 + $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export ATF_LOAD_ADDR=0x80000000 + $ export BL33_LOAD_ADDR=0x80020000 + $ make imx8qm_rom7720_a1_4G_defconfig + $ make u-boot.bin + $ make flash.bin + +Flash the binary into the SD card +--------------------------------- + +Burn the flash.bin binary to SD card offset 32KB: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +---- + +Set Boot switch SW2: 1100. diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst new file mode 100644 index 0000000000..e9b198c5c3 --- /dev/null +++ b/doc/board/advantech/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Advantech +========= + +.. toctree:: + :maxdepth: 2 + + imx8qm-rom7720-a1.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index 4b6a996eb1..915f1be8a5 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -7,6 +7,7 @@ Board-specific doc :maxdepth: 2 actions/index + advantech/index AndesTech/index amlogic/index atmel/index From 6cb007a1c75ff8ba3fea8a48b66ad65192e53d78 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 28 Oct 2020 09:38:52 +0200 Subject: [PATCH 075/222] imx8mp_evk: README instruction fixes Use the full name of firmware self extracting file to make it run. Also, don't use sudo when not needed. Signed-off-by: Baruch Siach --- doc/board/freescale/imx8mp_evk.rst | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/board/freescale/imx8mp_evk.rst b/doc/board/freescale/imx8mp_evk.rst index b34742e33e..96df6d470f 100644 --- a/doc/board/freescale/imx8mp_evk.rst +++ b/doc/board/freescale/imx8mp_evk.rst @@ -23,7 +23,7 @@ branch: imx_5.4.3_2.0.0 .. code-block:: bash $ make PLAT=imx8mp bl31 - $ sudo cp build/imx8mp/release/bl31.bin $(srctree) + $ cp build/imx8mp/release/bl31.bin $(srctree) Get the ddr firmware -------------------- @@ -32,11 +32,11 @@ Get the ddr firmware $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin $ chmod +x firmware-imx-8.7.bin - $ ./firmware-imx-8.7 - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin - $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin + $ ./firmware-imx-8.7.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin + $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin Build U-Boot ------------ From 8c5ea5361c1728c162dd5ce796654c5aef77420e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 29 Oct 2020 21:22:03 -0400 Subject: [PATCH 076/222] configs: migrate CONFIG_IMX_THERMAL to defconfigs Done via moveconfig.py Signed-off-by: Tom Rini --- configs/cgtqmx6eval_defconfig | 1 + configs/colibri-imx6ull_defconfig | 1 + configs/colibri_imx7_defconfig | 1 + configs/colibri_imx7_emmc_defconfig | 1 + configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ configs/liteboard_defconfig | 1 + configs/marsboard_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_defconfig | 1 + configs/mx6slevk_spinor_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sllevk_defconfig | 1 + configs/mx6sllevk_plugin_defconfig | 1 + configs/mx6sxsabreauto_defconfig | 1 + configs/mx6sxsabresd_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/mx6ull_14x14_evk_defconfig | 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + configs/mx6ulz_14x14_evk_defconfig | 1 + configs/mx7dsabresd_defconfig | 1 + configs/mx7dsabresd_qspi_defconfig | 1 + configs/myir_mys_6ulx_defconfig | 1 + configs/ot1200_defconfig | 1 + configs/ot1200_spl_defconfig | 1 + configs/pfla02_defconfig | 1 + configs/phycore_pcl063_defconfig | 1 + configs/phycore_pcl063_ull_defconfig | 1 + configs/pico-dwarf-imx7d_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-nymph-imx7d_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + configs/riotboard_defconfig | 1 + configs/riotboard_spl_defconfig | 1 + configs/sksimx6_defconfig | 1 + configs/somlabs_visionsom_6ull_defconfig | 1 + configs/tbs2910_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/variscite_dart6ul_defconfig | 1 + configs/vining_2000_defconfig | 1 + configs/warp7_bl33_defconfig | 1 + configs/warp7_defconfig | 1 + configs/xpress_defconfig | 1 + configs/xpress_spl_defconfig | 1 + configs/zc5202_defconfig | 1 + configs/zc5601_defconfig | 1 + include/configs/cgtqmx6eval.h | 1 - include/configs/cl-som-imx7.h | 3 --- include/configs/colibri-imx6ull.h | 2 -- include/configs/colibri_imx7.h | 2 -- include/configs/dart_6ul.h | 2 -- include/configs/el6x_common.h | 2 -- include/configs/embestmx6boards.h | 2 -- include/configs/gw_ventana.h | 10 ---------- include/configs/liteboard.h | 2 -- include/configs/mx6cuboxi.h | 2 -- include/configs/mx6sabre_common.h | 2 -- include/configs/mx6slevk.h | 2 -- include/configs/mx6sllevk.h | 2 -- include/configs/mx6sxsabreauto.h | 2 -- include/configs/mx6sxsabresd.h | 2 -- include/configs/mx6ul_14x14_evk.h | 2 -- include/configs/mx6ullevk.h | 2 -- include/configs/mx7dsabresd.h | 2 -- include/configs/mys_6ulx.h | 2 -- include/configs/ot1200.h | 3 --- include/configs/pcl063.h | 2 -- include/configs/pcl063_ull.h | 2 -- include/configs/pfla02.h | 3 --- include/configs/pico-imx7d.h | 2 -- include/configs/sksimx6.h | 3 --- include/configs/somlabs_visionsom_6ull.h | 2 -- include/configs/tbs2910.h | 2 -- include/configs/udoo_neo.h | 4 ---- include/configs/vining_2000.h | 2 -- include/configs/warp7.h | 2 -- include/configs/xpress.h | 2 -- 83 files changed, 55 insertions(+), 75 deletions(-) diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index c3f608264d..26f74662f8 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -71,6 +71,7 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 273cb9d7a8..5e18f66d71 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -84,6 +84,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 42a9d63383..71e331ef71 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -82,6 +82,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 81d83c7296..c5a6c4433d 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -79,6 +79,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index fd47aad648..41e190bf1e 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -81,6 +81,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 2a87353ca9..66b0441978 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -85,6 +85,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index d2fa6d7022..9022f350d1 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -85,6 +85,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 40b5f276ed..b258880b94 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -56,6 +56,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 22578714b5..d2bd9c46d2 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -38,6 +38,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 4cabe9076a..a373d52c93 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 3241ef8e06..4faf49ef05 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -89,6 +89,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index baa304f744..0016fbac20 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -100,6 +100,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 171941a8f7..5fd78c3629 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 925886cb40..9777166727 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index b430955cb3..4e44bc2c79 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index d145874a7f..1e446a3e43 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 49d76a0805..3e0e1006b9 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index f645f751e2..0d8c07b57d 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -61,6 +61,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 0e672efb7b..af5acc178f 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -66,6 +66,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index f0a155aff3..878df78cce 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -80,6 +80,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 40bb371a69..9587ff808f 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -75,6 +75,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 4fdbb915d4..fdd4483817 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -58,3 +58,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index f8f863411e..a6c30b3fb6 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -57,3 +57,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index fac63f3859..71801208ad 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -49,3 +49,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index e9e1f1ea47..3687a65283 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -70,6 +70,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 6004128de9..c216b8c5be 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -77,6 +77,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index ef90f5f66f..e929216c83 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index a4fb70b5bf..4f8a524c1d 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -53,6 +53,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index 81feb2ff2f..ec3bf90306 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -64,6 +64,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index dc7151b610..fa8ed31e5b 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -71,4 +71,5 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index ab92e3f7e7..65239a049d 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 9cc0892dab..c57ca29f3b 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 085913ef82..dbfa2e0a8c 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 6b3b100d20..f33a72571c 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 5bd56c6535..947dfcbf9e 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -62,6 +62,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_CONS_INDEX=4 CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index e2e3a56437..cc49e6f80a 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 085913ef82..dbfa2e0a8c 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 4005f8d1af..ab630cace7 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1c632770b3..b652057d74 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -39,6 +39,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig index 42d737771c..95549ff5b7 100644 --- a/configs/riotboard_spl_defconfig +++ b/configs/riotboard_spl_defconfig @@ -49,6 +49,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig index 927f46f5db..9b3706124f 100644 --- a/configs/sksimx6_defconfig +++ b/configs/sksimx6_defconfig @@ -49,4 +49,5 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index 739d4c9bab..52e34e3b3f 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index e43fab208d..239e9ed04e 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -84,6 +84,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 89e9363dc5..ba1e6d31f8 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -38,4 +38,5 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 37d9687c06..5f94cea5dd 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index b0a9c652a9..31e6cfb425 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -78,6 +78,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 761fcd7821..4b45fcd50a 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -52,6 +52,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_OPTEE=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 3fd21dd853..3d11196080 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -58,6 +58,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_OPTEE=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig index dd0b61c18f..b77bf9a470 100644 --- a/configs/xpress_defconfig +++ b/configs/xpress_defconfig @@ -40,6 +40,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig index 935450efe0..aee059dea0 100644 --- a/configs/xpress_spl_defconfig +++ b/configs/xpress_spl_defconfig @@ -51,6 +51,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index 07cd0542a0..321a9351d2 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -58,4 +58,5 @@ CONFIG_PCI=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index 90736ec6ec..ed6978e32c 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -56,4 +56,5 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 2ef6bfdba8..bdd5973cb7 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -35,7 +35,6 @@ #define CONFIG_SPI_FLASH_SST /* Thermal support */ -#define CONFIG_IMX_THERMAL /* I2C Configs */ #define CONFIG_SYS_I2C diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 07f1893d11..0ef55b7713 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -141,9 +141,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -/* Uncomment to enable iMX thermal driver support */ -/*#define CONFIG_IMX_THERMAL*/ - /* SPL */ #include "imx7_spl.h" diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index d373fda016..2827c171c9 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -140,8 +140,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS /* USB Device Firmware Update support */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index b3601abe2c..85dd891055 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -208,8 +208,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS #if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b27f715798..4eb50f841e 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -84,8 +84,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bd61f20a7a..9ee7fee2d7 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -14,8 +14,6 @@ #include "mx6_common.h" -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index b18db76d2f..ff3a849a14 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -17,8 +17,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a92157d52c..7c8abda1d2 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -32,16 +32,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -/* Init Functions */ - -/* Driver Model */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_THERMAL -#endif - -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART2_BASE diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index db5e6fc133..5adbe1ca39 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -141,6 +141,4 @@ #define CONFIG_ETHPRIME "FEC" #endif -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index cfab9a7fc0..55717c77ab 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -13,8 +13,6 @@ #include "imx6_spl.h" -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) /* MMC Configs */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c4e34e9cbc..93d00a4dc3 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 44dadd681c..ab32f4e151 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -132,6 +132,4 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IMX_THERMAL - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 9533d30742..a38ce4d097 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -123,8 +123,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IMX_THERMAL - #define CONFIG_IOMUX_LPSR /* USB Configs */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 9ad29341c1..58cc3f0ee2 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -138,8 +138,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 42feb14019..036881f6ea 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -170,8 +170,6 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#define CONFIG_IMX_THERMAL - #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_MXS diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index fa6b303dd4..7d36c1e4d9 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -177,8 +177,6 @@ #endif #endif -#define CONFIG_IMX_THERMAL - #ifndef CONFIG_SPL_BUILD #if defined(CONFIG_DM_VIDEO) #define CONFIG_VIDEO_MXS diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index ca2f2bd975..23f6de9050 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -150,8 +150,6 @@ /* environment organization */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_IMX_THERMAL - #define CONFIG_IOMUX_LPSR #define CONFIG_SOFT_SPI diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 51a7a5f4a0..5801da0cfa 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -134,8 +134,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS #ifdef CONFIG_VIDEO diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 208779958f..5ef16fb278 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -50,8 +50,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index bf8f7b1e1b..ea61f92bdb 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -74,9 +74,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #endif -/* Thermal support */ -#define CONFIG_IMX_THERMAL - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 2156da671b..4f4d50131f 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -62,8 +62,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index d7c6f8808e..6009521c9f 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -69,8 +69,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index 3227c4276e..e96429083e 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -13,9 +13,6 @@ #include "mx6_common.h" -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 51b7359cad..80de1158ad 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -168,6 +168,4 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h index 511b1a440e..7052d8049e 100644 --- a/include/configs/sksimx6.h +++ b/include/configs/sksimx6.h @@ -10,9 +10,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 204818b8eb..945d0ecc73 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -104,6 +104,4 @@ #define CONFIG_ETHPRIME "eth0" #endif -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 01c1143e43..a2e59ce618 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_IMX_THERMAL - /* Physical Memory Map */ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 34a95a0283..4935a2b363 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -70,10 +70,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Environment organization */ - -#define CONFIG_IMX_THERMAL - /* I2C configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a851fb41a8..f97431f135 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -73,8 +73,6 @@ #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif -#define CONFIG_IMX_THERMAL - #define CONFIG_IMX6_PWM_PER_CLK 66000000 #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 2d1ede3bc8..8eb1060274 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -146,8 +146,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS /* USB Device Firmware Update support */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 399925a75b..e7a26589d6 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -63,8 +63,6 @@ #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "FEC" -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_UBOOT_SECTOR_START 0x2 From 81d4c4e45c015794f1fa96cc7f308bb27b11009a Mon Sep 17 00:00:00 2001 From: Manuel Reis Date: Wed, 25 Nov 2020 10:16:20 +0000 Subject: [PATCH 077/222] add check for ignored CONFIG_ENV_EXT4_DEVICE_AND_PART definition Check whether user has explicitly defined device and partition where environment file will be located before using 'auto' i.e. bootable partition Voids the need to set such partition as bootable to work with the 'dev:auto' tuple Signed-off-by: Manuel Reis Cc: Patrick Delaunay Cc: Patrice Chotard Tested-by: Michael Opdenacker Reviewed-by: Patrick Delaunay --- board/st/stm32mp1/stm32mp1.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 8a3ce0a6f5..d3cffdd770 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -827,11 +827,22 @@ const char *env_ext4_get_intf(void) const char *env_ext4_get_dev_part(void) { + static char *const env_dev_part = +#ifdef CONFIG_ENV_EXT4_DEVICE_AND_PART + CONFIG_ENV_EXT4_DEVICE_AND_PART; +#else + ""; +#endif static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"}; + + if (strlen(env_dev_part) > 0) + return env_dev_part; + u32 bootmode = get_bootmode(); return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1]; } + int mmc_get_env_dev(void) { u32 bootmode = get_bootmode(); From 5905e0880a8dbae8cc0249c3fd3428cb24f8d230 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 2 Dec 2020 18:47:29 +0100 Subject: [PATCH 078/222] MAINTAINERS: Update ARM STI and ARM STM STM32MP Arch maintainers emails Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2625fc629c..127e30c0a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -385,7 +385,7 @@ F: drivers/smem/msm_smem.c F: drivers/usb/host/ehci-msm.c ARM STI -M: Patrice Chotard +M: Patrice Chotard S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git F: arch/arm/mach-sti/ @@ -411,8 +411,8 @@ F: arch/arm/cpu/arm926ejs/spear/ F: arch/arm/include/asm/arch-spear/ ARM STM STM32MP -M: Patrick Delaunay -M: Patrice Chotard +M: Patrick Delaunay +M: Patrice Chotard L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git S: Maintained From 0f8106f8e0c03839b371eaee1d7459b810d569ec Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 2 Dec 2020 18:47:30 +0100 Subject: [PATCH 079/222] treewide: Update email address Patrick Delaunay and Patrice Chotard Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/include/asm/arch-stih410/sdhci.h | 2 +- arch/arm/include/asm/arch-stih410/sys_proto.h | 2 +- arch/arm/include/asm/arch-stm32/stm32f.h | 2 +- arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 2 +- arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 2 +- arch/arm/include/asm/arch-stm32h7/gpio.h | 2 +- arch/arm/include/asm/arch-stm32h7/stm32.h | 2 +- arch/arm/mach-stm32/soc.c | 2 +- board/st/stih410-b2260/board.c | 2 +- board/st/stm32f429-evaluation/stm32f429-evaluation.c | 2 +- board/st/stm32f469-discovery/stm32f469-discovery.c | 2 +- board/st/stm32h743-disco/stm32h743-disco.c | 2 +- board/st/stm32h743-eval/stm32h743-eval.c | 2 +- drivers/clk/clk_stm32h7.c | 2 +- drivers/misc/stm32_rcc.c | 2 +- drivers/mmc/sti_sdhci.c | 2 +- drivers/mmc/stm32_sdmmc2.c | 2 +- drivers/phy/sti_usb_phy.c | 2 +- drivers/pinctrl/pinctrl-sti.c | 2 +- drivers/reset/sti-reset.c | 2 +- drivers/reset/stm32-reset.c | 2 +- drivers/serial/serial_sti_asc.c | 2 +- drivers/sysreset/sysreset_sti.c | 2 +- drivers/timer/sti-timer.c | 2 +- drivers/timer/stm32_timer.c | 2 +- drivers/usb/host/dwc3-sti-glue.c | 2 +- drivers/video/backlight_gpio.c | 2 +- include/configs/stih410-b2260.h | 2 +- include/configs/stm32f429-evaluation.h | 2 +- include/configs/stm32f469-discovery.h | 2 +- include/configs/stm32h743-disco.h | 2 +- include/configs/stm32h743-eval.h | 2 +- include/dwc3-sti-glue.h | 2 +- include/stm32_rcc.h | 2 +- 34 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h b/arch/arm/include/asm/arch-stih410/sdhci.h index d5557b89fc..1735c0e391 100644 --- a/arch/arm/include/asm/arch-stih410/sdhci.h +++ b/arch/arm/include/asm/arch-stih410/sdhci.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STI_SDHCI_H__ diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h b/arch/arm/include/asm/arch-stih410/sys_proto.h index f9e8d3704a..30e7f398eb 100644 --- a/arch/arm/include/asm/arch-stih410/sys_proto.h +++ b/arch/arm/include/asm/arch-stih410/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_SYS_PROTO_H diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h index bd3f4fd30a..a1ce81ecad 100644 --- a/arch/arm/include/asm/arch-stm32/stm32f.h +++ b/arch/arm/include/asm/arch-stm32/stm32f.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_STM32F_H diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h index 8af6de220d..fe6ca03d2d 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h index 02faaeb663..5cd6553d04 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h index 2dad52a400..4f57f175ff 100644 --- a/arch/arm/include/asm/arch-stm32h7/gpio.h +++ b/arch/arm/include/asm/arch-stm32h7/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _STM32_GPIO_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/stm32.h b/arch/arm/include/asm/arch-stm32h7/stm32.h index 458baca458..2b0a670008 100644 --- a/arch/arm/include/asm/arch-stm32h7/stm32.h +++ b/arch/arm/include/asm/arch-stm32h7/stm32.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_HARDWARE_H diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 1f12da401c..0bd8d7b22c 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index b1147f2e1a..e06f05bfa4 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 92e3d40a1b..22a193d8fc 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 85988acb24..4ad4ee69c7 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #include diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 0484c3c250..0b5afa05ac 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 0484c3c250..0b5afa05ac 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index 5e6abca56f..edf90ee00f 100644 --- a/drivers/clk/clk_stm32h7.c +++ b/drivers/clk/clk_stm32h7.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index b82fe54c60..86275454be 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c index 5578feebef..c3a1b34442 100644 --- a/drivers/mmc/sti_sdhci.c +++ b/drivers/mmc/sti_sdhci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 77871d5afc..1f1b6cf4fb 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/phy/sti_usb_phy.c b/drivers/phy/sti_usb_phy.c index 2a20f7601c..51468b4573 100644 --- a/drivers/phy/sti_usb_phy.c +++ b/drivers/phy/sti_usb_phy.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/pinctrl/pinctrl-sti.c b/drivers/pinctrl/pinctrl-sti.c index 8e942a8280..2f3ee00453 100644 --- a/drivers/pinctrl/pinctrl-sti.c +++ b/drivers/pinctrl/pinctrl-sti.c @@ -3,7 +3,7 @@ * Pinctrl driver for STMicroelectronics STi SoCs * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index ac3a99f9bf..2cca67dc52 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index 20c36a99eb..d8902e9d9c 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c index 33ff396bff..91e1574638 100644 --- a/drivers/serial/serial_sti_asc.c +++ b/drivers/serial/serial_sti_asc.c @@ -3,7 +3,7 @@ * Support for Serial I/O using STMicroelectronics' on-chip ASC. * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/sysreset/sysreset_sti.c b/drivers/sysreset/sysreset_sti.c index 3482d2a078..43e161c65d 100644 --- a/drivers/sysreset/sysreset_sti.c +++ b/drivers/sysreset/sysreset_sti.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/timer/sti-timer.c b/drivers/timer/sti-timer.c index e6843ebb33..9d95f562fa 100644 --- a/drivers/timer/sti-timer.c +++ b/drivers/timer/sti-timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index f517d5e61f..2f5f8f43b9 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c index 3e6c1429d6..9dec087738 100644 --- a/drivers/usb/host/dwc3-sti-glue.c +++ b/drivers/usb/host/dwc3-sti-glue.c @@ -3,7 +3,7 @@ * STiH407 family DWC3 specific Glue layer * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/video/backlight_gpio.c b/drivers/video/backlight_gpio.c index 67fed7f224..433d0979e8 100644 --- a/drivers/video/backlight_gpio.c +++ b/drivers/video/backlight_gpio.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author: Patrick Delaunay + * Author: Patrick Delaunay */ #include diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 169b9efeec..33b34ee0cd 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 8390535af0..fefdb2dd15 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 57fb6b25af..ba9f05a61b 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index afc98ae791..6e10dbdfe9 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 66af8f50d9..268d39c7ad 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h index 3989a9bb53..546ffbaf7b 100644 --- a/include/dwc3-sti-glue.h +++ b/include/dwc3-sti-glue.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __DWC3_STI_UBOOT_H_ diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index a09a09ff95..b559ea7728 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #ifndef __STM32_RCC_H_ From b52b9330c66f1f6671d361d336a99907692cde06 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 2 Dec 2020 18:47:31 +0100 Subject: [PATCH 080/222] .mailmap: map Patrick Delaunay and my email address Add our new email address dedicated for upstream activities. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- .mailmap | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.mailmap b/.mailmap index 8250015453..33001f1e01 100644 --- a/.mailmap +++ b/.mailmap @@ -31,6 +31,8 @@ Jagan Teki Jagan Teki Igor Opaniuk Markus Klotzbuecher +Patrice Chotard +Patrick Delaunay Paul Burton Prabhakar Kushwaha Rajeshwari Shinde From 845c6720eca92be09127f7d306349ab31dbf372d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:17 +0100 Subject: [PATCH 081/222] ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM The default state of SD bus and clock line is logical HI. SD card IO is open-drain and pulls the bus lines LO. Always enable the SD bus pull ups to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus voltage level shifter, the pull ups are built into the level shifter, however that has no negative impact. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index f022d8395c..9049245c5b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -339,6 +339,20 @@ status = "okay"; }; +&sdmmc1_b4_pins_a { + /* + * SD bus pull-up resistors: + * - optional on SoMs with SD voltage translator + * - mandatory on SoMs without SD voltage translator + */ + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + &sdmmc2 { pinctrl-names = "default"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; From 75df748b87f86e87a4393d8ebc274e5806f2079a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:18 +0100 Subject: [PATCH 082/222] ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter or without one on the SDMMC1 interface. Because the SDMMC1 interface is limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback clock to permit operation of the same U-Boot image on both SoM with and without voltage level shifter. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index 9049245c5b..dafcce4323 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -333,7 +333,6 @@ disable-wp; st,sig-dir; st,neg-edge; - st,use-ckin; bus-width = <4>; vmmc-supply = <&vdd_sd>; status = "okay"; From 1399be91cb57a480d5ff7bb084b40b4787be9f22 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:19 +0100 Subject: [PATCH 083/222] ARM: dts: stm32: Enable SDMMC3 on DH DRC02 The DH DRC02 board has an on-board microSD slot, add DT properties to enable the slot. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts index 5a237a3b7b..e8508aa4d5 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -105,9 +105,18 @@ * On DRC02, the SoM does not have SDIO WiFi. The pins * are used for on-board microSD slot instead. */ - /delete-property/broken-cd; - cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; }; &spi1 { From 9b36b7dc96baedc0ed506246a9822c745cc65b45 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:20 +0100 Subject: [PATCH 084/222] ARM: dts: stm32: Add USB OTG ID pin on DH AV96 Add USB OTG ID pin mux and switch the USB OTG port from peripheral to OTG mode. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts index 88f25d89b2..9b5dda318e 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -192,7 +192,8 @@ }; &usbotg_hs { - dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; From 07f29f0217d29637971c04dc032c9040398c99c9 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:03 +0530 Subject: [PATCH 085/222] configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 LX2160A-Rev1 uses PCIe layerscape Gen4 controller. Enable CONFIG_PCIE_LAYERSCAPE_GEN4 for lx2160a. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index a6a3feba93..9d60fe8a96 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -69,6 +69,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index d96c3b129d..391ea174fd 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -76,6 +76,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index b2912e418b..22db7fbdd5 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 5a9e2e776e..a82f14ec1c 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -70,6 +70,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 2d7b4af4b2..d3c76832c8 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -70,6 +70,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y From b6c6a245bfe0c7d76fa5bb6d079ef5b85e14e835 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:04 +0530 Subject: [PATCH 086/222] pci: layerscape: Update print of pcie controller Print pcie controller number starting from 1 Signed-off-by: Wasim Khan [Trimmed subject] Signed-off-by: Priyanka Jain --- drivers/pci/pcie_layerscape_ep.c | 4 +++- drivers/pci/pcie_layerscape_rc.c | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index eba230e3a5..26c04a9fc2 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -294,7 +295,8 @@ static int ls_pcie_ep_probe(struct udevice *dev) pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "num-ob-windows", 8); - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Endpoint"); ls_pcie_setup_ep(pcie_ep); if (!ls_pcie_link_up(pcie)) { diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index 25c6ddebce..f9e308925b 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev) pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); if (!pcie_rc->enabled) { - printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx), + dev->name); return 0; } @@ -342,7 +343,8 @@ static int ls_pcie_probe(struct udevice *dev) (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0, pcie->big_endian); - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Root Complex"); ls_pcie_setup_ctrl(pcie_rc); if (!ls_pcie_link_up(pcie)) { From eac364416c62ea1f49934f762e184616a04adede Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:05 +0530 Subject: [PATCH 087/222] pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan --- drivers/pci/pcie_layerscape_gen4.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 428bfcab09..0226bde678 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * * PCIe Gen4 driver for NXP Layerscape SoCs * Author: Hou Zhiqiang @@ -472,7 +472,8 @@ static int ls_pcie_g4_probe(struct udevice *dev) pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); if (!pcie->enabled) { - printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx), + dev->name); return 0; } @@ -522,10 +523,12 @@ static int ls_pcie_g4_probe(struct udevice *dev) pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f; if (pcie->mode == PCI_HEADER_TYPE_NORMAL) { - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Endpoint"); ls_pcie_g4_setup_ep(pcie); } else { - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Root Complex"); ls_pcie_g4_setup_ctrl(pcie); } From 6519ccd28229b03e335e4af5dac6ddf209a777e5 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 4 Dec 2020 20:11:53 +0530 Subject: [PATCH 088/222] arm: dts: lx2160a: add label to pcie nodes in dts Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/dts/fsl-lx2160a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index bfdf178738..a6f0e9bc56 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -325,7 +325,7 @@ }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */ 0x00 0x03480000 0x0 0x40000 /* LUT registers */ @@ -340,7 +340,7 @@ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */ 0x00 0x03580000 0x0 0x40000 /* LUT registers */ @@ -356,7 +356,7 @@ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */ 0x00 0x03680000 0x0 0x40000 /* LUT registers */ @@ -371,7 +371,7 @@ 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3700000 { + pcie4: pcie@3700000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */ 0x00 0x03780000 0x0 0x40000 /* LUT registers */ @@ -386,7 +386,7 @@ 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3800000 { + pcie5: pcie@3800000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */ 0x00 0x03880000 0x0 0x40000 /* LUT registers */ @@ -401,7 +401,7 @@ 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3900000 { + pcie6: pcie@3900000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */ 0x00 0x03980000 0x0 0x40000 /* LUT registers */ From 2adb7970cbc4a74511dd44fc968e96947033407f Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:07 +0530 Subject: [PATCH 089/222] arm: dts: ls1046a: add label to pcie nodes in dts Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1046a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 3f11d6cd18..155455d591 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -241,7 +241,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x40000 /* lut registers */ @@ -257,7 +257,7 @@ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie_ep@3400000 { + pcie_ep1: pcie_ep@3400000 { compatible = "fsl,ls-pcie-ep"; reg = <0x00 0x03400000 0x0 0x80000 0x00 0x034c0000 0x0 0x40000 @@ -268,7 +268,7 @@ big-endian; }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x40000 /* lut registers */ @@ -285,7 +285,7 @@ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie_ep@3500000 { + pcie_ep2: pcie_ep@3500000 { compatible = "fsl,ls-pcie-ep"; reg = <0x00 0x03500000 0x0 0x80000 0x00 0x035c0000 0x0 0x40000 @@ -296,7 +296,7 @@ big-endian; }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x40000 /* lut registers */ @@ -312,7 +312,7 @@ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie_ep@3600000 { + pcie_ep3: pcie_ep@3600000 { compatible = "fsl,ls-pcie-ep"; reg = <0x00 0x03600000 0x0 0x80000 0x00 0x036c0000 0x0 0x40000 From ba45dd21f3bcaeec1fb90c9f52428252ea2ba911 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:08 +0530 Subject: [PATCH 090/222] arm: dts: ls2080a: add label to pcie nodes in dts Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls2080a.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 6b7bf8eb16..f0f4a82c14 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a SOC common device tree source + * NXP ls2080a SOC common device tree source * + * Copyright 2020 NXP * Copyright 2013-2015 Freescale Semiconductor, Inc. */ @@ -133,7 +134,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x80000 /* lut registers */ @@ -148,7 +149,7 @@ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x80000 /* lut registers */ @@ -163,7 +164,7 @@ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x80000 /* lut registers */ @@ -178,7 +179,7 @@ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3700000 { + pcie4: pcie@3700000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */ 0x00 0x03780000 0x0 0x80000 /* lut registers */ From 7dfc20ab1dc996ec89d564fb2fb031da499a0920 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:09 +0530 Subject: [PATCH 091/222] arm: dts: ls1088a: add label to pcie nodes in dts Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1088a.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 6653794d1c..7b4ac6d3de 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -2,7 +2,7 @@ /* * NXP ls1088a SOC common device tree source * - * Copyright 2017 NXP + * Copyright 2017, 2020 NXP */ / { @@ -135,7 +135,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x80000 /* lut registers */ @@ -151,7 +151,7 @@ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 0x00 0x03580000 0x0 0x80000 /* lut registers */ @@ -167,7 +167,7 @@ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 0x00 0x03680000 0x0 0x80000 /* lut registers */ From 6ba8b6a8f8d284bea437d51ab86b8d7b8ad80f9c Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:10 +0530 Subject: [PATCH 092/222] arm: dts: ls1012a: add label to pcie nodes in dts Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1012a.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 2d70c82a72..c401ba33ac 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* + * Copyright 2020 NXP * Copyright 2016 Freescale Semiconductor */ @@ -116,7 +117,7 @@ status = "disabled"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 0x00 0x03480000 0x0 0x40000 /* lut registers */ From 04c2d93d3693bb9a9f4002ab37336cb87d81af53 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:11 +0530 Subject: [PATCH 093/222] arm: dts: ls1043a: add label to pcie nodes in dts Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1043a.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index f7db44c0fa..8ca57ea7b9 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * Device Tree Include file for NXP Layerscape-1043A family SoC. * + * Copyright 2020 NXP * Copyright (C) 2014-2015, Freescale Semiconductor * * Mingkai Hu @@ -240,7 +241,7 @@ dr_mode = "host"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */ 0x00 0x03410000 0x0 0x10000 /* lut registers */ @@ -255,7 +256,7 @@ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */ 0x00 0x03510000 0x0 0x10000 /* lut registers */ @@ -271,7 +272,7 @@ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3600000 { + pcie3: pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */ 0x00 0x03610000 0x0 0x10000 /* lut registers */ From 4c72d2d53bfcbf8003ba715ab3a3bac8cbf50b21 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:12 +0530 Subject: [PATCH 094/222] arm: dts: ls1028a: add label to pcie nodes in dts Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index bf6373d5ec..d0850237c7 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -2,7 +2,7 @@ /* * NXP ls1028a SOC common device tree source * - * Copyright 2019 NXP + * Copyright 2019-2020 NXP * */ @@ -91,7 +91,7 @@ status = "disabled"; }; - pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 0x00 0x03480000 0x0 0x40000 /* lut registers */ @@ -107,7 +107,7 @@ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; - pcie@3500000 { + pcie2: pcie@3500000 { compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 0x00 0x03580000 0x0 0x40000 /* lut registers */ From 49df7c90867c0a991222f6a4eac8e42879880c23 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:13 +0530 Subject: [PATCH 095/222] pci: layerscape: Add size check for config resource resource "config" is required to have minimum 8KB space as per hardware documentation. Signed-off-by: Hou Zhiqiang Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- drivers/pci/pcie_layerscape_rc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index f9e308925b..cdfcad6b0b 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev) return ret; } + cfg_size = fdt_resource_size(&pcie_rc->cfg_res); + if (cfg_size < SZ_8K) { + printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n", + PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K); + return 0; + } + /* * Fix the pcie memory map address and PF control registers address * for LS2088A series SoCs @@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev) if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || svr == SVR_LS2081A || svr == SVR_LS2041A) { - cfg_size = fdt_resource_size(&pcie_rc->cfg_res); pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size; From 1255f8bc36101400fd16fc4898f9dd9fdccbbc2e Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 28 Sep 2020 16:26:14 +0530 Subject: [PATCH 096/222] pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- drivers/pci/pcie_layerscape_gen4.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 0226bde678..6e71173621 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev) u32 link_ctrl_sta; u32 val; int ret; + fdt_size_t cfg_size; pcie->bus = dev; @@ -488,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev) return ret; } + cfg_size = fdt_resource_size(&pcie->cfg_res); + if (cfg_size < SZ_4K) { + printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n", + PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K); + return 0; + } + pcie->cfg = map_physmem(pcie->cfg_res.start, fdt_resource_size(&pcie->cfg_res), MAP_NOCACHE); From 2a29a9a1b41200b228651a4dc13f88ff00301b62 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Thu, 29 Oct 2020 19:16:15 +0530 Subject: [PATCH 097/222] drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can be controlled via defconfig files. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + drivers/net/phy/Kconfig | 9 +++++++++ drivers/net/phy/cortina.c | 8 ++++---- include/configs/lx2160aqds.h | 1 - include/configs/lx2160ardb.h | 1 - 9 files changed, 18 insertions(+), 6 deletions(-) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 9d60fe8a96..cf4bf8a19a 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 391ea174fd..f0e8dca8f9 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 22db7fbdd5..0551ef0793 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -52,6 +52,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index a82f14ec1c..52ac1264ae 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -61,6 +61,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index d3c76832c8..d9c1674026 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -61,6 +61,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 4e1a93be22..51733dd123 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -100,6 +100,15 @@ config PHY_BROADCOM config PHY_CORTINA bool "Cortina Ethernet PHYs support" +config SYS_CORTINA_NO_FW_UPLOAD + bool "Cortina firmware loading support" + default n + depends on PHY_CORTINA + help + Cortina phy has provision to store phy firmware in attached dedicated + EEPROM. And boards designed with such EEPROM does not require firmware + upload. + choice prompt "Location of the Cortina firmware" default SYS_CORTINA_FW_IN_NOR diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index dbc20b1405..b381a431fd 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -3,7 +3,7 @@ * Cortina CS4315/CS4340 10G PHY drivers * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */ @@ -29,7 +29,7 @@ #error The Cortina PHY needs 10G support #endif -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD struct cortina_reg_config cortina_reg_cfg[] = { /* CS4315_enable_sr_mode */ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, @@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) int cs4340_phy_init(struct phy_device *phydev) { -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD int timeout = 100; /* 100ms */ #endif int reg_value; @@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev) * Boards designed with EEPROM attached to Cortina * does not require FW upload. */ -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD /* step1: BIST test */ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 1cc015c1c7..12884bcf2b 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -93,7 +93,6 @@ u8 qixis_esdhc_detect_quirk(void); #define AQ_PHY_ADDR3 0x02 #define AQ_PHY_ADDR4 0x03 -#define CORTINA_NO_FW_UPLOAD #define CORTINA_PHY_ADDR1 0x0 #define INPHI_PHY_ADDR1 0x0 diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index a51987e6b0..59c2305a34 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -64,7 +64,6 @@ #define AQR107_PHY_ADDR2 0x05 #define AQR107_IRQ_MASK 0x0C -#define CORTINA_NO_FW_UPLOAD #define CORTINA_PHY_ADDR1 0x0 #define INPHI_PHY_ADDR1 0x0 From 3a187cff7ac95887917bcf25f3f575bb677a361e Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Thu, 29 Oct 2020 19:16:16 +0530 Subject: [PATCH 098/222] armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal [Fixed whitespace errors] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++++++++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 ++- .../cpu/armv8/fsl-layerscape/doc/README.soc | 56 +++++++++++++++++++ .../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 8 +-- .../armv8/fsl-layerscape/fsl_lsch3_speed.c | 4 +- .../cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 ++++++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 10 ++-- .../include/asm/arch-fsl-layerscape/config.h | 6 +- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++-- .../arm/include/asm/arch-fsl-layerscape/soc.h | 7 ++- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 ++-- board/freescale/common/vid.c | 3 +- drivers/ddr/fsl/Kconfig | 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/pci/Kconfig | 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 ++- 21 files changed, 171 insertions(+), 42 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3655990772..f2474413cc 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -115,7 +115,7 @@ config PSCI_RESET !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ - !TARGET_LX2160AQDS && \ + !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index be51b7d856..4d46587214 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -208,6 +208,35 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2162A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config ARCH_LX2160A bool select ARMV8_SET_SMPEN @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106 help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar - to erratum A-009007, but this one is for LX2160A, + to erratum A-009007, but this one is for LX2160A and LX2162A, and the register value is different. config SYS_FSL_ERRATUM_A010315 @@ -362,6 +391,7 @@ config MAX_CPUS default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A default 16 if ARCH_LX2160A + default 16 if ARCH_LX2162A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A default 4 if ARCH_LX2160A + default 4 if ARCH_LX2162A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -560,14 +593,14 @@ config SYS_FSL_EC1 bool help Ethernet controller 1, this is connected to - MAC17 for LX2160A or to MAC3 for other SoCs + MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help Ethernet controller 2, this is connected to - MAC18 for LX2160A or to MAC4 for other SoCs + MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 9ecb372b4e..598c36ee66 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o obj-y += icid.o lx2160_ids.o endif +ifneq ($(CONFIG_ARCH_LX2162A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +obj-y += icid.o lx2160_ids.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o obj-y += icid.o ls2088_ids.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 596b88d3e2..1a5d26b537 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), + CPU_TYPE_ENTRY(LX2162A, LX2162A, 16), + CPU_TYPE_ENTRY(LX2122A, LX2122A, 12), + CPU_TYPE_ENTRY(LX2082A, LX2082A, 8), }; #define EARLY_PGTABLE_SIZE 0x5000 @@ -403,7 +406,7 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) if (IS_C_PROCESSOR(svr)) strcat(name, "C"); #endif @@ -1229,7 +1232,7 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; void __efi_runtime reset_cpu(ulong addr) { -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) /* clear the RST_REQ_MSK and SW_RST_REQ */ out_le32(rstcr, 0x0); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index ad55573c85..f33d05d053 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -9,6 +9,7 @@ SoC overview 7. LS2081A 8. LX2160A 9. LS1028A + 10. LX2162A LS1043A --------- @@ -379,3 +380,58 @@ The LS1028A SoC includes the following function and features: - Layerscape Trust Architecture - Service Processor (SP) provides pre-boot initialization and secure-boot capabilities + +LX2162A +-------- +The QorIQ LX2162A processor is built on the Layerscape architecture +combining sixteen ARM A72 processor cores with advanced, high-performance +datapath acceleration and network, peripheral interfaces required for +networking, wireless infrastructure, storage, and general-purpose embedded +applications. + +LX2162A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2162A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508) + One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 12 Serdes lanes at up to 25 GHz + Ethernet interfaces + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + One PCIe Gen 3.0 8-lane controllers supporting SR-IOV, + Two PCIe Gen 3.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + One USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2162A SoC has 2 more similar SoC personalities +1)LX2122A, few difference w.r.t. LX2162A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2082A, few difference w.r.t. LX2162A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index aa6fd6b28c..fad7a93566 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2016-2018 NXP + * Copyright 2016-2018, 2020 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -26,7 +26,7 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) int xfi_dpmac[XFI14 + 1]; int sgmii_dpmac[SGMII18 + 1]; int a25gaui_dpmac[_25GE10 + 1]; @@ -159,7 +159,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], (int)lane_prtcl); @@ -552,7 +552,7 @@ void fsl_serdes_init(void) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int i , j; -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) for (i = XFI1, j = 1; i <= XFI14; i++, j++) xfi_dpmac[i] = j; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 7f8178f72e..bf153c720e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015, Freescale Semiconductor, Inc. - * Copyright 2019 NXP Semiconductors + * Copyright 2019-2020 NXP * * Derived from arch/power/cpu/mpc85xx/speed.c */ @@ -180,7 +180,7 @@ int get_clocks(void) #ifdef CONFIG_FSL_ESDHC #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) clock = sys_info.freq_cga_m2; -#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A) clock = sys_info.freq_systembus; #endif gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c index a04a370268..5941d90e03 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP */ #include @@ -11,6 +11,22 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; +#if defined(CONFIG_ARCH_LX2162A) +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } }, + {0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {_25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } }, + {} +}; +#else static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, @@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, {} }; +#endif static struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 96b2775f3f..ad209bde33 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #include @@ -186,7 +186,8 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ - defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) + defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -222,7 +223,7 @@ static void erratum_a009007(void) #if defined(CONFIG_FSL_LSCH3) static void erratum_a050106(void) { -#if defined(CONFIG_ARCH_LX2160A) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); @@ -392,7 +393,8 @@ void fsl_lsch3_early_init_f(void) #endif #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ - defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) set_icids(); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index e13f4d83e6..a9bd8b24fd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2016-2018 NXP + * Copyright 2016-2018, 2020 NXP * Copyright 2015, Freescale Semiconductor */ @@ -179,8 +179,8 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ -/* LX2160A Soc Support */ -#elif defined(CONFIG_ARCH_LX2160A) +/* LX2160A/LX2162A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define TZPC_BASE 0x02200000 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) #if !defined(CONFIG_DM_I2C) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 7759acdb8f..4335aa0ec2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018, 2020 NXP * Copyright 2014-2015, Freescale Semiconductor */ @@ -53,7 +53,7 @@ #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 -#ifndef CONFIG_ARCH_LX2160A +#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162) #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #else #define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 24a64b7575..b61666ed4b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -15,7 +15,7 @@ #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) #else #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) @@ -198,12 +198,12 @@ #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) #endif -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL @@ -267,7 +267,7 @@ defined(CONFIG_ARCH_LS1028A) #define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_4 0x0b80 -#elif defined(CONFIG_ARCH_LX2160A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define USB_PHY_RX_EQ_VAL_3 0x0080 #define USB_PHY_RX_EQ_VAL_4 0x0880 #endif @@ -391,7 +391,7 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 -#elif defined(CONFIG_ARCH_LX2160A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define FSL_CHASSIS3_EC1_REGSR 27 #define FSL_CHASSIS3_EC2_REGSR 27 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 020548ac6c..b24f38cac9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * Copyright 2015 Freescale Semiconductor */ @@ -106,13 +106,16 @@ enum boot_src get_boot_src(void); #define SVR_LX2160A 0x873600 #define SVR_LX2120A 0x873620 #define SVR_LX2080A 0x873602 +#define SVR_LX2162A 0x873608 +#define SVR_LX2122A 0x873628 +#define SVR_LX2082A 0x87360A #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) #endif #ifdef CONFIG_ARCH_LS1028A diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 4c54e3d3d5..36f36699a7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015-2019 NXP + * Copyright 2015-2020 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -74,11 +74,13 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ + defined(CONFIG_ARCH_LX2162A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) #define FSL_DMA_STREAM_ID 5 @@ -91,7 +93,7 @@ #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_PEX_STREAM_ID_END 18 -#elif defined(CONFIG_ARCH_LX2160A) +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define FSL_PEX_STREAM_ID_END (0x100) #endif diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 9c51f50260..77a3be68ef 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -487,7 +488,7 @@ int adjust_vdd(ulong vdd_override) int ret, i2caddress; unsigned long vdd_string_override; char *vdd_string; -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) static const u16 vdd[32] = { 8250, 7875, diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index f75d97b15c..5f62489a90 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -47,6 +47,7 @@ config SYS_NUM_DDR_CTLRS ARCH_P5020 || \ ARCH_P5040 || \ ARCH_LX2160A || \ + ARCH_LX2162A || \ ARCH_T4160 default 1 diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig index 2cf651d3b3..ae4c35799b 100644 --- a/drivers/net/fsl-mc/Kconfig +++ b/drivers/net/fsl-mc/Kconfig @@ -4,7 +4,7 @@ menuconfig FSL_MC_ENET bool "NXP Management Complex" - depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A default y select RESV_RAM help @@ -17,7 +17,7 @@ if FSL_MC_ENET config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 1d85b2cfa8..52ab828f0b 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -7,3 +7,4 @@ obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o +obj-$(CONFIG_ARCH_LX2162A) += lx2160a.o diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index af92784950..65498bce1d 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -219,7 +219,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A default "fsl,ls1021a-pcie" if ARCH_LS1021A help This compatible is used to find pci controller node in Kernel DT @@ -228,7 +228,7 @@ config FSL_PCIE_COMPAT config FSL_PCIE_EP_COMPAT string "PCIe EP compatible of Kernel DT" depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 - default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A + default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A default "fsl,ls-pcie-ep" help This compatible is used to find pci controller ep node in Kernel DT diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 26c04a9fc2..d7d4a44b22 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -273,7 +273,9 @@ static int ls_pcie_ep_probe(struct udevice *dev) svr = SVR_SOC_VER(get_svr()); - if (svr == SVR_LX2160A) + if (svr == SVR_LX2160A || svr == SVR_LX2162A || + svr == SVR_LX2120A || svr == SVR_LX2080A || + svr == SVR_LX2122A || svr == SVR_LX2082A) pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET; else pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET; diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index 0a42997696..77d1573ea5 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -121,13 +121,16 @@ int pcie_board_fix_fdt(void *fdt) svr = SVR_SOC_VER(get_svr()); - if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0)) + if ((svr == SVR_LX2160A || svr == SVR_LX2162A || + svr == SVR_LX2120A || svr == SVR_LX2080A || + svr == SVR_LX2122A || svr == SVR_LX2082A) && + IS_SVR_REV(get_svr(), 2, 0)) return lx2_board_fix_fdt(fdt); return 0; } -#ifdef CONFIG_ARCH_LX2160A +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) /* returns the next available streamid for pcie, -errno if failed */ int pcie_next_streamid(int currentid, int idx) { From 9ed303dfa97b773c4f4743238ea32b68e340afa9 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Fri, 4 Dec 2020 20:17:28 +0530 Subject: [PATCH 099/222] armv8: lx2162aqds: Add support for LX2162AQDS platform This patch add base support for LX2162AQDS board. LX2162AQDS board supports LX2162A family SoCs. This patch add basic support of platform. Signed-off-by: Ioana Ciornei Signed-off-by: Zhao Qiang Signed-off-by: hui.song Signed-off-by: Manish Tomar Signed-off-by: Vikas Singh Signed-off-by: Meenakshi Aggarwal [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/Kconfig | 12 + arch/arm/dts/Makefile | 6 +- arch/arm/dts/fsl-lx2160a-qds.dts | 3 - arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + arch/arm/dts/fsl-lx2162a-qds.dts | 34 + board/freescale/common/qixis.h | 25 + board/freescale/common/vid.h | 30 + board/freescale/lx2160a/Kconfig | 16 + board/freescale/lx2160a/MAINTAINERS | 26 + board/freescale/lx2160a/Makefile | 1 + board/freescale/lx2160a/README | 132 +++ board/freescale/lx2160a/eth_lx2160ardb.c | 3 +- board/freescale/lx2160a/eth_lx2162aqds.c | 974 ++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 43 +- board/freescale/lx2160a/lx2160a.h | 61 ++ configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 98 ++ configs/lx2162aqds_tfa_defconfig | 96 ++ .../lx2162aqds_tfa_verified_boot_defconfig | 103 ++ include/configs/lx2160a_common.h | 2 + include/configs/lx2160aqds.h | 75 -- include/configs/lx2160ardb.h | 49 - include/configs/lx2162aqds.h | 78 ++ 28 files changed, 1935 insertions(+), 150 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c create mode 100644 board/freescale/lx2160a/lx2160a.h create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/lx2162aqds_tfa_defconfig create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig create mode 100644 include/configs/lx2162aqds.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5903c09370..fbe90875ae 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS is a high-performance development platform that supports the QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. +config TARGET_LX2162AQDS + bool "Support lx2162aqds" + select ARCH_LX2162A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT + help + Support for NXP LX2162AQDS platform. + The lx2162aqds support is based on LX2160A Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 02d04f5a8c..fd47e408f8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -414,7 +414,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-lx2160a-qds-19-x-x.dtb \ fsl-lx2160a-qds-19-11-x.dtb \ fsl-lx2160a-qds-20-x-x.dtb \ - fsl-lx2160a-qds-20-11-x.dtb + fsl-lx2160a-qds-20-11-x.dtb \ + fsl-lx2162a-qds.dtb\ + fsl-lx2162a-qds-17-x.dtb\ + fsl-lx2162a-qds-18-x.dtb\ + fsl-lx2162a-qds-20-x.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index e0f5d5e2d3..332c778d3a 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -13,7 +13,4 @@ / { model = "NXP Layerscape LX2160AQDS Board"; compatible = "fsl,lx2160aqds", "fsl,lx2160a"; - aliases { - spi0 = &fspi; - }; }; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 96c980004b..288607c034 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -2,12 +2,18 @@ /* * NXP LX2160AQDS common device tree source * - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */ #include "fsl-lx2160a.dtsi" +/ { + aliases { + spi0 = &fspi; + }; +}; + &dpmac17 { status = "okay"; phy-handle = <&rgmii_phy1>; @@ -251,6 +257,20 @@ }; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2162a-qds-17-x.dts b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts new file mode 100644 index 0000000000..8a8895f023 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 17.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-17.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 17.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-18-x.dts b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts new file mode 100644 index 0000000000..c28e5e2497 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 18.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-18.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 18.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-20-x.dts b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts new file mode 100644 index 0000000000..7882c767e2 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 20.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-20.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi new file mode 100644 index 0000000000..60f5a4ee43 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17 + * + * Some assumptions are made: + * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy2>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy3>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; + + inphi_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x2>; + }; + + inphi_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x3>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi new file mode 100644 index 0000000000..8e11b0680a --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) + * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; +}; + +&emdio1_slot6 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi new file mode 100644 index 0000000000..faf4285eab --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20 + * + * Some assumptions are made: + * * Mezzanine card M8 is connected to IO SLOT1 + * (xlaui4 for DPMAC 1) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-handle = <&cortina_phy1_0>; + phy-connection-type = "xlaui4"; +}; + +&emdio1_slot1 { + cortina_phy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts new file mode 100644 index 0000000000..b16526503d --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds.dtsi" + +/ { + model = "NXP Layerscape LX2162AQDS Board"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + + aliases { + pcie@3500000 { + status = "disabled"; + }; + + pcie@3800000 { + status = "disabled"; + }; + + pcie@3900000 { + status = "disabled"; + }; + }; +}; + +&usb1 { + status = "disabled"; +}; diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 93638d2452..0860bd2312 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -141,4 +141,29 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_EVDD_BY_SDHC_VS 0x0c +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +#define QIXIS_XMAP_MASK 0x07 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC +#define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 +#define NON_EXTENDED_DUTCFG +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 +#endif + #endif diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index 65b348ee42..5bbaecace4 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __VID_H_ @@ -37,6 +38,35 @@ */ #define EN_WRITE_ALL_CMD (0) +#ifdef CONFIG_TARGET_LX2160ARDB +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 855 +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 925 +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +/* PM Bus commands code for LTC3882*/ +#define PWM_CHANNEL0 0x0 +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_VOUT_COMMAND 0x21 +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_MUX_CH_VOL_MONITOR 0xA +#endif + int adjust_vdd(ulong vdd_override); #endif /* __VID_H_ */ diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig index 122a385100..7556f7dd21 100644 --- a/board/freescale/lx2160a/Kconfig +++ b/board/freescale/lx2160a/Kconfig @@ -32,3 +32,19 @@ config SYS_CONFIG_NAME source "board/freescale/common/Kconfig" endif +if TARGET_LX2162AQDS + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2162aqds" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index 9fe79c0ef7..c627417cf7 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -1,4 +1,5 @@ LX2160ARDB BOARD +M: Meenakshi Aggarwal M: Priyanka Jain S: Maintained F: board/freescale/lx2160a/ @@ -14,6 +15,7 @@ S: Maintained F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig LX2160AQDS BOARD +M: Meenakshi Aggarwal M: Pankaj Bansal S: Maintained F: board/freescale/lx2160a/eth_lx2160aqds.h @@ -25,3 +27,27 @@ LX2160AQDS_SECURE_BOOT BOARD M: Udit Agarwal S: Maintained F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS BOARD +M: Meenakshi Aggarwal +S: Maintained +F: board/freescale/lx2160a/eth_lx2162aqds.h +F: include/configs/lx2162aqds.h +F: configs/lx2162aqds_tfa_defconfig +F: arch/arm/dts/fsl-lx2162a-qds.dts +F: arch/arm/dts/fsl-lx2162a-qds-17-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-18-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-20-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi + +LX2162AQDS_SECURE_BOOT BOARD +M: Manish Tomar +S: Maintained +F: configs/lx2162aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS_VERIFIED_BOOT BOARD +M: Manish Tomar +S: Maintained +F: configs/lx2162aqds_tfa_verified_boot_defconfig diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile index d1a621b682..c9561bfade 100644 --- a/board/freescale/lx2160a/Makefile +++ b/board/freescale/lx2160a/Makefile @@ -8,3 +8,4 @@ obj-y += lx2160a.o obj-y += ddr.o obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o +obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README index 62fb9eab15..7bca98dd3d 100644 --- a/board/freescale/lx2160a/README +++ b/board/freescale/lx2160a/README @@ -195,3 +195,135 @@ SERDES3 |CARDS |Connect I/O cable to IO_SLOT6(J125) ------------------------------------------------------------------------- +LX2162A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2162AQDS board Overview +---------------------- +DDR Memory + One ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 2.9 GT/s. + +SERDES ports + Two serdes controllers (12 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector, + four SATA 3.0 connectors + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + One high speed USB 3.0 ports. First USB 3.0 port configured as Host + with Type-A connector, second USB 3.0 port configured as OTG with + micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot +c) eMMC boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd/eMMC card +---------------------------- +Image SD/eMMC card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 + +Various Mezzanine cards and their connection for different SERDES protocols is +as below: + +SERDES1 |CARDS +----------------------------------------------------------------------- +1 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +3 |Mezzanine:X-M11-USXGMII (29828) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +15 |Mezzanine:X-M8-50G (29734) + |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +17 |Mezzanine:X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +18 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) +------------------------------------------------------------------------ +20 |Mezzanine:X-M7-40G (29738) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J108) +------------------------------------------------------------------------ + + +SERDES2 |CARDS +----------------------------------------------------------------------- +2 |Mezzanine:X-M6-PCIE-X8 (29737) * + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT3(J116) +------------------------------------------------------------------------ +3 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +5 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M5-SATA (29687) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +11 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT7(J127) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT8(J131) +------------------------------------------------------------------------ diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index b448883ee1..b3125b7748 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */ @@ -19,6 +19,7 @@ #include #include #include +#include "lx2160a.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c new file mode 100644 index 0000000000..4683f674f0 --- /dev/null +++ b/board/freescale/lx2160a/eth_lx2162aqds.c @@ -0,0 +1,974 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_ETH +#define EMI_NONE 0 +#define EMI1 1 /* Mdio Bus 1 */ +#define EMI2 2 /* Mdio Bus 2 */ + +#if defined(CONFIG_FSL_MC_ENET) +enum io_slot { + IO_SLOT_NONE = 0, + IO_SLOT_1, + IO_SLOT_2, + IO_SLOT_3, + IO_SLOT_4, + IO_SLOT_5, + IO_SLOT_6, + IO_SLOT_7, + IO_SLOT_8, + EMI1_RGMII1, + EMI1_RGMII2, + IO_SLOT_MAX +}; + +struct lx2162a_qds_mdio { + enum io_slot ioslot : 4; + u8 realbusnum : 4; + struct mii_dev *realbus; +}; + +/* structure explaining the phy configuration on 8 lanes of a serdes*/ +struct serdes_phy_config { + u8 serdes; /* serdes protocol */ + struct phy_config { + u8 dpmacid; + /* -1 terminated array */ + int phy_address[WRIOP_MAX_PHY_NUM + 1]; + u8 mdio_bus; + enum io_slot ioslot; + } phy_config[SRDS_MAX_LANES]; +}; + +/* Table defining the phy configuration on 8 lanes of a serdes. + * Various assumptions have been made while defining this table. + * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII + * card is being used for dpmac 3-4. (X-M12-XFI could also have been used) + * And also that this card is connected to IO Slot 1 (could have been connected + * to any of the 8 IO slots (IO slot 1 - IO slot 8)). + * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card + * used in serdes1 protocol 19 (could have selected MDIO 2) + * To override these settings "dpmac" environment variable can be used after + * defining "dpmac_override" in hwconfig environment variable. + * This table has limited serdes protocol entries. It can be expanded as per + * requirement. + */ +/***************************************************************** + *| SERDES_1 PROTOCOL | IO_SLOT | CARD | + ****************************************************************** + *| 2 | IO_SLOT_1 | M4-PCIE-SGMII | + *| 3 | IO_SLOT_1 | M11-USXGMII | + *| 15 | IO_SLOT_1 | M13-25G | + *| 17 | IO_SLOT_1 | M13-25G | + *| 18 | IO_SLOT_1 | M11-USXGMII | + *| | IO_SLOT_6 | M13-25G | + *| 20 | IO_SLOT_1 | M7-40G | + ***************************************************************** + */ +static const struct serdes_phy_config serdes1_phy_config[] = { + {1, {} }, + {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_1} } }, + {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1}, + EMI1, IO_SLOT_1} } }, + {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1} } }, + {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1} } }, + {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_6}, + {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_6} } }, + {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1} } } +}; + +/***************************************************************** + *| SERDES_2 PROTOCOL | IO_SLOT | CARD | + ****************************************************************** + *| 2 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 3 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 5 | IO_SLOT_7 | M4-PCIE-SGMII | + *| 10 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 11 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 12 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + ****************************************************************** + */ +static const struct serdes_phy_config serdes2_phy_config[] = { + {2, {} }, + {3, {} }, + {5, {} }, + {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } }, + {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_8}, + {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_8}, + {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_8} } }, + {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } } +}; + +static inline +const struct phy_config *get_phy_config(u8 serdes, + const struct serdes_phy_config *table, + u8 table_size) +{ + int i; + + for (i = 0; i < table_size; i++) { + if (table[i].serdes == serdes) + return table[i].phy_config; + } + + return NULL; +} + +/* BRDCFG4 controls EMI routing for the board. + * Bits Function + * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V): + * EMI1 00= On-board PHY #1 + * 01= On-board PHY #2 + * 10= (reserved) + * 11= Slots 1..8 multiplexer and translator. + * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V): + * EMI1X 000= Slot #1 + * 001= Slot #2 + * 010= Slot #3 + * 011= Slot #4 + * 100= Slot #5 + * 101= Slot #6 + * 110= Slot #7 + * 111= Slot #8 + * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2): + * EMI2 000= Slot #1 (secondary EMI) + * 001= Slot #2 (secondary EMI) + * 010= Slot #3 (secondary EMI) + * 011= Slot #4 (secondary EMI) + * 100= Slot #5 (secondary EMI) + * 101= Slot #6 (secondary EMI) + * 110= Slot #7 (secondary EMI) + * 111= Slot #8 (secondary EMI) + */ +static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot) +{ + switch (realbusnum) { + case EMI1: + switch (ioslot) { + case EMI1_RGMII1: + return 0; + case EMI1_RGMII2: + return 0x40; + default: + return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0); + } + break; + case EMI2: + return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT); + default: + return -1; + } +} + +static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv) +{ + u8 brdcfg4, mux_val, reg; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + reg = brdcfg4; + mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + + switch (priv->realbusnum) { + case EMI1: + brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK; + brdcfg4 |= mux_val; + break; + case EMI2: + brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK; + brdcfg4 |= mux_val; + break; + } + + if (brdcfg4 ^ reg) + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr, + int devad, int regnum) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + lx2162a_qds_mux_mdio(priv); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + lx2162a_qds_mux_mdio(priv); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int lx2162a_qds_mdio_reset(struct mii_dev *bus) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot) +{ + struct lx2162a_qds_mdio *pmdio; + struct mii_dev *bus; + /*should be within MDIO_NAME_LEN*/ + char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1"; + + if (realbusnum == EMI2) { + if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) { + printf("invalid ioslot %d\n", ioslot); + return NULL; + } + } else if (realbusnum == EMI1) { + if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) { + printf("invalid ioslot %d\n", ioslot); + return NULL; + } + } else { + printf("not supported real mdio bus %d\n", realbusnum); + return NULL; + } + + if (ioslot == EMI1_RGMII1) + strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1"); + else if (ioslot == EMI1_RGMII2) + strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2"); + else + sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d", + realbusnum, ioslot); + bus = miiphy_get_dev_by_name(dummy_mdio_name); + + if (bus) + return bus; + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate %s bus\n", dummy_mdio_name); + return NULL; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate %s private data\n", dummy_mdio_name); + free(bus); + return NULL; + } + + switch (realbusnum) { + case EMI1: + pmdio->realbus = + miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + break; + case EMI2: + pmdio->realbus = + miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + break; + } + + if (!pmdio->realbus) { + printf("No real mdio bus num %d found\n", realbusnum); + free(bus); + free(pmdio); + return NULL; + } + + pmdio->realbusnum = realbusnum; + pmdio->ioslot = ioslot; + bus->read = lx2162a_qds_mdio_read; + bus->write = lx2162a_qds_mdio_write; + bus->reset = lx2162a_qds_mdio_reset; + strcpy(bus->name, dummy_mdio_name); + bus->priv = pmdio; + + if (!mdio_register(bus)) + return bus; + + printf("No bus with name %s\n", dummy_mdio_name); + free(bus); + free(pmdio); + return NULL; +} + +static inline void do_phy_config(const struct phy_config *phy_config) +{ + struct mii_dev *bus; + int i, phy_num, phy_address; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (!phy_config[i].dpmacid) + continue; + + for (phy_num = 0; + phy_num < ARRAY_SIZE(phy_config[i].phy_address); + phy_num++) { + phy_address = phy_config[i].phy_address[phy_num]; + if (phy_address == -1) + break; + wriop_set_phy_address(phy_config[i].dpmacid, + phy_num, phy_address); + } + /*Register the muxing front-ends to the MDIO buses*/ + bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus, + phy_config[i].ioslot); + if (!bus) + printf("could not get bus for mdio %d ioslot %d\n", + phy_config[i].mdio_bus, + phy_config[i].ioslot); + else + wriop_set_mdio(phy_config[i].dpmacid, bus); + } +} + +static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid, + char *env_dpmac) +{ + const char *ret; + size_t len; + u8 realbusnum, ioslot; + struct mii_dev *bus; + int phy_num; + char *phystr = "phy00"; + + /*search phy in dpmac arg*/ + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) { + sprintf(phystr, "phy%d", phy_num + 1); + ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac); + if (!ret) { + /*look for phy instead of phy1*/ + if (!phy_num) + ret = hwconfig_subarg_f(arg_dpmacid, "phy", + &len, env_dpmac); + if (!ret) + continue; + } + + if (len != 4 || strncmp(ret, "0x", 2)) + printf("invalid phy format in %s variable.\n" + "specify phy%d for %s in hex format e.g. 0x12\n", + env_dpmac, phy_num + 1, arg_dpmacid); + else + wriop_set_phy_address(dpmac, phy_num, + simple_strtoul(ret, NULL, 16)); + } + + /*search mdio in dpmac arg*/ + ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac); + if (ret) + realbusnum = *ret - '0'; + else + realbusnum = EMI_NONE; + + if (realbusnum) { + /*search io in dpmac arg*/ + ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac); + if (ret) + ioslot = *ret - '0'; + else + ioslot = IO_SLOT_NONE; + /*Register the muxing front-ends to the MDIO buses*/ + bus = lx2162a_qds_mdio_init(realbusnum, ioslot); + if (!bus) + printf("could not get bus for mdio %d ioslot %d\n", + realbusnum, ioslot); + else + wriop_set_mdio(dpmac, bus); + } +} + +#endif +#endif /* !CONFIG_DM_ETH */ + +int board_eth_init(struct bd_info *bis) +{ +#ifndef CONFIG_DM_ETH +#if defined(CONFIG_FSL_MC_ENET) + struct memac_mdio_info mdio_info; + struct memac_mdio_controller *regs; + int i; + const char *ret; + char *env_dpmac; + char dpmacid[] = "dpmac00", srds[] = "00_00_00"; + size_t len; + struct mii_dev *bus; + const struct phy_config *phy_config; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1, srds_s2; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + sprintf(srds, "%d_%d", srds_s1, srds_s2); + + regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = regs; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /*Register the EMI 1*/ + fm_memac_mdio_init(bis, &mdio_info); + + regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = regs; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /*Register the EMI 2*/ + fm_memac_mdio_init(bis, &mdio_info); + + /* "dpmac" environment variable can be used after + * defining "dpmac_override" in hwconfig environment variable. + */ + if (hwconfig("dpmac_override")) { + env_dpmac = env_get("dpmac"); + if (env_dpmac) { + ret = hwconfig_arg_f("srds", &len, env_dpmac); + if (ret) { + if (strncmp(ret, srds, strlen(srds))) { + printf("SERDES configuration changed.\n" + "previous: %.*s, current: %s.\n" + "update dpmac variable.\n", + (int)len, ret, srds); + } + } else { + printf("SERDES configuration not found.\n" + "Please add srds:%s in dpmac variable\n", + srds); + } + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + /* Look for dpmac1 to dpmac24(current max) arg + * in dpmac environment variable + */ + sprintf(dpmacid, "dpmac%d", i); + ret = hwconfig_arg_f(dpmacid, &len, env_dpmac); + if (ret) + do_dpmac_config(i, dpmacid, env_dpmac); + } + } else { + printf("Warning: environment dpmac not found.\n" + "DPAA network interfaces may not work\n"); + } + } else { + /*Look for phy config for serdes1 in phy config table*/ + phy_config = get_phy_config(srds_s1, serdes1_phy_config, + ARRAY_SIZE(serdes1_phy_config)); + if (!phy_config) { + printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n", + __func__, srds_s1); + } else { + do_phy_config(phy_config); + } + phy_config = get_phy_config(srds_s2, serdes2_phy_config, + ARRAY_SIZE(serdes2_phy_config)); + if (!phy_config) { + printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n", + __func__, srds_s2); + } else { + do_phy_config(phy_config); + } + } + + if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) { + wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1); + bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1); + if (!bus) + printf("could not get bus for RGMII1\n"); + else + wriop_set_mdio(WRIOP1_DPMAC17, bus); + } + + if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) { + wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2); + bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2); + if (!bus) + printf("could not get bus for RGMII2\n"); + else + wriop_set_mdio(WRIOP1_DPMAC18, bus); + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + +#ifdef CONFIG_DM_ETH + return 0; +#else + return pci_eth_init(bis); +#endif +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +#ifndef CONFIG_DM_ETH +#if defined(CONFIG_FSL_MC_ENET) +int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) +{ + int offset; + int ret; + char dpmac_str[] = "dpmacs@00"; + const char *phy_string; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); + + if (offset < 0) { + printf("dpmacs node not found in device tree\n"); + return offset; + } + + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + debug("dpmac_str = %s\n", dpmac_str); + + offset = fdt_subnode_offset(fdt, offset, dpmac_str); + if (offset < 0) { + printf("%s node not found in device tree\n", dpmac_str); + return offset; + } + + phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL); + if (is_backplane_mode(phy_string)) { + /* Backplane KR mode: skip fixups */ + printf("Interface %d in backplane KR mode\n", dpmac_id); + return 0; + } + + ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle); + if (ret) + printf("%d@%s %d\n", __LINE__, __func__, ret); + + phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id)); + ret = fdt_setprop_string(fdt, offset, "phy-connection-type", + phy_string); + if (ret) + printf("%d@%s %d\n", __LINE__, __func__, ret); + + return ret; +} + +int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) +{ + char mdio_ioslot_str[] = "mdio@00"; + struct lx2162a_qds_mdio *priv; + u64 reg; + u32 phandle; + int offset, mux_val; + + /*Test if the MDIO bus is real mdio bus or muxing front end ?*/ + if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO", + strlen("LX2162A_QDS_MDIO"))) + return -1; + + /*Get the real MDIO bus num and ioslot info from bus's priv data*/ + priv = mii_dev->priv; + + debug("real_bus_num = %d, ioslot = %d\n", + priv->realbusnum, priv->ioslot); + + if (priv->realbusnum == EMI1) + reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; + else + reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; + + offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); + if (offset < 0) { + printf("mdio@%llx node not found in device tree\n", reg); + return offset; + } + + phandle = fdt_get_phandle(fdt, offset); + phandle = cpu_to_fdt32(phandle); + offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus", + &phandle, 4); + if (offset < 0) { + printf("mdio-mux-%d node not found in device tree\n", + priv->realbusnum == EMI1 ? 1 : 2); + return offset; + } + + mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + if (priv->realbusnum == EMI1) + mux_val >>= BRDCFG4_EMI1SEL_SHIFT; + else + mux_val >>= BRDCFG4_EMI2SEL_SHIFT; + sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val); + + offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str); + if (offset < 0) { + printf("%s node not found in device tree\n", mdio_ioslot_str); + return offset; + } + + return offset; +} + +int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset, + struct phy_device *phy_dev, int phandle) +{ + char phy_node_name[] = "ethernet-phy@00"; + char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,"; + int ret; + + sprintf(phy_node_name, "ethernet-phy@%x", phyaddr); + debug("phy_node_name = %s\n", phy_node_name); + + *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name); + if (*subnodeoffset <= 0) { + printf("Could not add subnode %s inside node %s err = %s\n", + phy_node_name, fdt_get_name(fdt, offset, NULL), + fdt_strerror(*subnodeoffset)); + return *subnodeoffset; + } + + sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,", + phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF); + debug("phy_id_compatible_str %s\n", phy_id_compatible_str); + + ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible", + phy_id_compatible_str); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + + if (phy_dev->is_c45) { + ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", + "ethernet-phy-ieee802.3-c45"); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + } else { + ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", + "ethernet-phy-ieee802.3-c22"); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + } + + ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + + ret = fdt_set_phandle(fdt, *subnodeoffset, phandle); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + +out: + if (ret) + fdt_del_node(fdt, *subnodeoffset); + + return ret; +} + +#define is_rgmii(dpmac_id) \ + wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID + +int fdt_fixup_board_phy(void *fdt) +{ + int fpga_offset, offset, subnodeoffset; + struct mii_dev *mii_dev; + struct list_head *mii_devs, *entry; + int ret, dpmac_id, phandle, i; + struct phy_device *phy_dev; + char ethname[ETH_NAME_LEN]; + phy_interface_t phy_iface; + + ret = 0; + /* we know FPGA is connected to i2c0, therefore search path directly, + * instead of compatible property, as it saves time + */ + fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga"); + + if (fpga_offset < 0) + fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga"); + + if (fpga_offset < 0) { + printf("i2c@2000000/fpga node not found in device tree\n"); + return fpga_offset; + } + + phandle = fdt_alloc_phandle(fdt); + mii_devs = mdio_get_list_head(); + + list_for_each(entry, mii_devs) { + mii_dev = list_entry(entry, struct mii_dev, link); + debug("mii_dev name : %s\n", mii_dev->name); + offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset); + if (offset < 0) + continue; + + // Look for phy devices attached to MDIO bus muxing front end + // and create their entries with compatible being the device id + for (i = 0; i < PHY_MAX_ADDR; i++) { + phy_dev = mii_dev->phymap[i]; + if (!phy_dev) + continue; + + // TODO: use sscanf instead of loop + dpmac_id = WRIOP1_DPMAC1; + while (dpmac_id < NUM_WRIOP_PORTS) { + phy_iface = wriop_get_enet_if(dpmac_id); + snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", + dpmac_id, + phy_string_for_interface(phy_iface)); + if (strcmp(ethname, phy_dev->dev->name) == 0) + break; + dpmac_id++; + } + if (dpmac_id == NUM_WRIOP_PORTS) + continue; + + if ((dpmac_id == 17 || dpmac_id == 18) && + is_rgmii(dpmac_id)) + continue; + + ret = fdt_create_phy_node(fdt, offset, i, + &subnodeoffset, + phy_dev, phandle); + if (ret) + break; + + ret = fdt_fixup_dpmac_phy_handle(fdt, + dpmac_id, phandle); + if (ret) { + fdt_del_node(fdt, subnodeoffset); + break; + } + /* calculate offset again as new node addition may have + * changed offset; + */ + offset = fdt_get_ioslot_offset(fdt, mii_dev, + fpga_offset); + phandle++; + } + + if (ret) + break; + } + + return ret; +} +#endif // CONFIG_FSL_MC_ENET +#endif + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 2, true}, + {1, 3, true}, + {1, 15, true}, + {1, 17, true}, + {1, 18, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 10, false}, + {2, 11, true}, + {2, 12, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 0ff987eeb4..222906fdff 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -32,12 +32,13 @@ #include "../common/vid.h" #include #include +#include "lx2160a.h" #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" #endif -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) @@ -47,7 +48,7 @@ #define SDHC1_BASE_PMUX_DSPI 2 #define SDHC2_BASE_PMUX_DSPI 2 #define IIC5_PMUX_SPI3 3 -#endif /* CONFIG_TARGET_LX2160AQDS */ +#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ DECLARE_GLOBAL_DATA_PTR; @@ -191,7 +192,7 @@ int board_fix_fdt(void *fdt) } #endif -#if defined(CONFIG_TARGET_LX2160AQDS) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; @@ -259,7 +260,7 @@ void esdhc_dspi_status_fixup(void *blob) int esdhc_status_fixup(void *blob, const char *compat) { -#if defined(CONFIG_TARGET_LX2160AQDS) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) /* Enable esdhc and dspi DT nodes based on RCW fields */ esdhc_dspi_status_fixup(blob); #else @@ -297,7 +298,7 @@ int checkboard(void) enum boot_src src = get_boot_src(); char buf[64]; u8 sw; -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; static const char *const freq[] = {"100", "125", "156.25", "161.13", "322.26", "", "", "", @@ -306,7 +307,7 @@ int checkboard(void) #endif cpu_name(buf); -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else printf("Board: %s-RDB, ", buf); @@ -339,7 +340,13 @@ int checkboard(void) break; } } -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160ARDB) + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); + + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); + puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +#else printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); @@ -350,31 +357,27 @@ int checkboard(void) sw = QIXIS_READ(brdcfg[2]); clock = sw >> 4; printf("Clock1 = %sMHz ", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) clock = sw & 0x0f; printf("Clock2 = %sMHz", freq[clock]); - +#endif sw = QIXIS_READ(brdcfg[3]); puts("\nSERDES2 Reference : "); clock = sw >> 4; printf("Clock1 = %sMHz ", freq[clock]); clock = sw & 0x0f; - printf("Clock2 = %sMHz", freq[clock]); - + printf("Clock2 = %sMHz\n", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) sw = QIXIS_READ(brdcfg[12]); - puts("\nSERDES3 Reference : "); + puts("SERDES3 Reference : "); clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); -#else - printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - - puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); - puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); - puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +#endif #endif return 0; } -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) /* * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. */ @@ -562,7 +565,7 @@ int config_board_mux(void) unsigned long get_board_sys_clk(void) { -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x03) { @@ -581,7 +584,7 @@ unsigned long get_board_sys_clk(void) unsigned long get_board_ddr_clk(void) { -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); switch ((ddrclk_conf & 0x30) >> 4) { diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h new file mode 100644 index 0000000000..52b020765d --- /dev/null +++ b/board/freescale/lx2160a/lx2160a.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2160_H +#define __LX2160_H + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* SYSCLK */ +#define QIXIS_SYSCLK_100 0x0 +#define QIXIS_SYSCLK_125 0x1 +#define QIXIS_SYSCLK_133 0x2 + +/* DDRCLK */ +#define QIXIS_DDRCLK_100 0x0 +#define QIXIS_DDRCLK_125 0x1 +#define QIXIS_DDRCLK_133 0x2 + +#define BRDCFG4_EMI1SEL_MASK 0xF8 +#define BRDCFG4_EMI1SEL_SHIFT 3 +#define BRDCFG4_EMI2SEL_MASK 0x07 +#define BRDCFG4_EMI2SEL_SHIFT 0 +#endif + +#define QIXIS_XMAP_SHIFT 5 + +/* RTC */ +#define I2C_MUX_CH_RTC 0xB + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define AQ_PHY_ADDR1 0x00 +#define AQ_PHY_ADDR2 0x01 +#define AQ_PHY_ADDR3 0x02 +#define AQ_PHY_ADDR4 0x03 +#endif + +#ifdef CONFIG_TARGET_LX2160ARDB +#define AQR107_PHY_ADDR1 0x04 +#define AQR107_PHY_ADDR2 0x05 +#define AQR107_IRQ_MASK 0x0C +#endif + +#define CORTINA_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR1 0x0 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define INPHI_PHY_ADDR2 0x1 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif +#endif + +#endif /* __LX2160_H */ diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..11fe33b0fa --- /dev/null +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_TFABOOT=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_NXP_ESBC=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig new file mode 100644 index 0000000000..ca7479793d --- /dev/null +++ b/configs/lx2162aqds_tfa_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig new file mode 100644 index 0000000000..1199b6c63d --- /dev/null +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_RSA=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_OPTEE_TA_AVB=y +CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 0017ac5773..837760fe46 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -149,8 +149,10 @@ /* USB */ #ifdef CONFIG_USB #define CONFIG_HAS_FSL_XHCI_USB +#ifndef CONFIG_TARGET_LX2162AQDS #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#endif /* FlexSPI */ #ifdef CONFIG_NXP_FSPI diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 12884bcf2b..ea1b1635fe 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -8,70 +8,14 @@ #include "lx2160a_common.h" -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_LBMAP_EMMC -#define QIXIS_RCW_SRC_SD 0x08 -#define QIXIS_RCW_SRC_EMMC 0x09 -#define NON_EXTENDED_DUTCFG -#define QIXIS_SDID_MASK 0x07 -#define QIXIS_ESDHC_NO_ADAPTER 0x7 - -/* SYSCLK */ -#define QIXIS_SYSCLK_100 0x0 -#define QIXIS_SYSCLK_125 0x1 -#define QIXIS_SYSCLK_133 0x2 - -/* DDRCLK */ -#define QIXIS_DDRCLK_100 0x0 -#define QIXIS_DDRCLK_125 0x1 -#define QIXIS_DDRCLK_133 0x2 - -#define BRDCFG4_EMI1SEL_MASK 0xF8 -#define BRDCFG4_EMI1SEL_SHIFT 3 -#define BRDCFG4_EMI2SEL_MASK 0x07 -#define BRDCFG4_EMI2SEL_SHIFT 0 - /* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 #define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv" #define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 925 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -#define I2C_MUX_CH_RTC 0xB /* * MMC @@ -87,25 +31,6 @@ u8 qixis_esdhc_detect_quirk(void); #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC17@rgmii-id" - -#define AQ_PHY_ADDR1 0x00 -#define AQ_PHY_ADDR2 0x01 -#define AQ_PHY_ADDR3 0x02 -#define AQ_PHY_ADDR4 0x03 - -#define CORTINA_PHY_ADDR1 0x0 - -#define INPHI_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR2 0x1 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - #endif /* EEPROM */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 59c2305a34..097f1224c9 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -8,47 +8,9 @@ #include "lx2160a_common.h" -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_LBMAP_EMMC -#define QIXIS_RCW_SRC_SD 0x08 -#define QIXIS_RCW_SRC_EMMC 0x09 -#define NON_EXTENDED_DUTCFG - /* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 #define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" #define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 855 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ @@ -59,17 +21,6 @@ #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC1@xgmii" - -#define AQR107_PHY_ADDR1 0x04 -#define AQR107_PHY_ADDR2 0x05 -#define AQR107_IRQ_MASK 0x0C - -#define CORTINA_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR1 0x0 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - #endif /* EMC2305 */ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h new file mode 100644 index 0000000000..847534c550 --- /dev/null +++ b/include/configs/lx2162aqds.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2162_QDS_H +#define __LX2162_QDS_H + +#include "lx2160a_common.h" + +/* USB */ +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +/* Voltage monitor on channel 2*/ +#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv" +#define CONFIG_VID +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * MMC + */ +#ifdef CONFIG_MMC +#ifndef __ASSEMBLY__ +u8 qixis_esdhc_detect_quirk(void); +#endif +#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() +#endif + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS \ + "boot_scripts=lx2162aqds_boot.scr\0" \ + "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \ + "BOARD=lx2162aqds\0" \ + "xspi_bootcmd=echo Trying load from flexspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "emmc_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" + +#include + +#endif /* __LX2162_QDS_H */ From fd1f8c691d2bd09c18a12883596742939840839a Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Mon, 28 Sep 2020 18:21:54 +0530 Subject: [PATCH 100/222] configs: lx2162a: Enable OPTEE support Enable support to compile OPTEE driver, access AVB TA and RPMB API's access via RPC from OPTEE for lx2162 Signed-off-by: Ruchika Gupta Signed-off-by: Gaurav Jain Reviewed-by: Priyanka Jain --- configs/lx2162aqds_tfa_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index ca7479793d..b88e73a551 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -94,3 +94,8 @@ CONFIG_CMD_DATE=y CONFIG_RTC_PCF2127=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_OPTEE_TA_AVB=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_CMD_OPTEE_RPMB=y From 9ff0fc8f7739e6c58766f050b29ddf60e5bc10fb Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 4 Dec 2020 20:31:26 +0530 Subject: [PATCH 101/222] configs: lx2162aqds: enable CONFIG_BOARD_EARLY_INIT_R Enable CONFIG_BOARD_EARLY_INIT_R for SDHC adapter card identification and configuration. Signed-off-by: Yangbo Lu [Rebased] Signed-off-by: Priyanka Jain --- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 11fe33b0fa..16a53775f7 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -18,6 +18,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CMD_GREPENV=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index b88e73a551..81108ef1bb 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CMD_GREPENV=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 1199b6c63d..7c19cdc884 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CMD_GREPENV=y From 8114791aeb220b81e706fef60ea899d3ea1f086b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 13 Oct 2020 14:17:35 +0800 Subject: [PATCH 102/222] configs: lx2162aqds: enable eMMC HS400 mode support Enable eMMC HS400 mode support on LX2162AQDS. Signed-off-by: Yangbo Lu Reviewed-by: Priyanka Jain --- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 16a53775f7..ea2c8db8c0 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 81108ef1bb..2eedc4842d 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 7c19cdc884..bbad895b1b 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -50,6 +50,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y From ee7c1225e3d8b3871833f4cbd80e122cb5fa52d2 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 26 Oct 2020 11:57:42 +0800 Subject: [PATCH 103/222] pci: layerscape: fix a dead loop issue Fixes: commit 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2") This added the PCIe EP nodes fixup of LX2160A, but it didn't update the condition value when there isn't a property 'apio-wins'. Signed-off-by: Hou Zhiqiang [Fixed checkpatch error] Signed-off-by: Priyanka Jain --- drivers/pci/pcie_layerscape_fixup_common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index 77d1573ea5..40f0ef10ac 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -99,6 +99,8 @@ int lx2_board_fix_fdt(void *fdt) if (!prop) { printf("%s: Failed to fixup PCIe EP node @0x%x\n", __func__, off); + off = fdt_node_offset_by_compatible(fdt, off, + "fsl,lx2160a-pcie-ep"); continue; } From e343ae7c967f5386f97fc9087383b54ed1967786 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 26 Oct 2020 15:14:05 +0800 Subject: [PATCH 104/222] board/freescale/common: fix a bug that failed to read/write eeprom on ls1021atsn Fix a bug that failed to read/write eeprom on ls1021atsn Signed-off-by: Biwen Li Tested-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- board/freescale/common/sys_eeprom.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 728245d81c..33ae4c15ba 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -175,9 +175,11 @@ static int read_eeprom(void) struct udevice *dev; #ifdef CONFIG_SYS_EEPROM_BUS_NUM ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); #else - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); #endif if (!ret) ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); From fc9a3d1b295cb15da06788fbb2f32d06b3888c57 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 26 Oct 2020 16:52:36 +0800 Subject: [PATCH 105/222] include/configs: ls1012aqds: add default environment variable This adds default environment variable for ls1012aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1012aqds.h | 62 ++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index df2a613eaf..c4c9b7f501 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -102,5 +102,67 @@ #define CONFIG_PCI_SCAN_SHOW +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#endif + #include #endif /* __LS1012AQDS_H__ */ From f6cb837721425000fc666ef350b77d400a08f584 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Tue, 27 Oct 2020 15:50:14 +0530 Subject: [PATCH 106/222] board: freescale: vid.c: Initialize variable 'i2caddress' Initialize variable 'i2caddress' in adjust_vdd() to zero Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- board/freescale/common/vid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 77a3be68ef..2617f61520 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -485,7 +485,7 @@ int adjust_vdd(ulong vdd_override) u8 vid; #endif int vdd_target, vdd_current, vdd_last; - int ret, i2caddress; + int ret, i2caddress = 0; unsigned long vdd_string_override; char *vdd_string; #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) From ccedd4ff8e359acfbf1877af14937a9e5045b25f Mon Sep 17 00:00:00 2001 From: Madalin Bucur Date: Wed, 4 Nov 2020 15:09:16 +0200 Subject: [PATCH 107/222] armv8: ls1043/ls1046aqds: add support for all RGMII modes Make sure all RGMII internal delay modes are covered. Signed-off-by: Madalin Bucur Reviewed-by: Priyanka Jain --- board/freescale/ls1043aqds/eth.c | 2 ++ board/freescale/ls1046aqds/eth.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 95412df1d7..c3efe8a0be 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -479,6 +479,8 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4) diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 8f5f95e396..33db552adb 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -409,6 +409,8 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4) From 848a2efd142ab6d879b1afed0cdbfada30522fa7 Mon Sep 17 00:00:00 2001 From: Madalin Bucur Date: Wed, 4 Nov 2020 15:09:17 +0200 Subject: [PATCH 108/222] board: freescale: powerpc: add support for all RGMII modes Make sure all RGMII internal delay modes are covered. Signed-off-by: Madalin Bucur Reviewed-by: Priyanka Jain --- board/freescale/corenet_ds/eth_hydra.c | 6 +++++ board/freescale/corenet_ds/eth_p4080.c | 6 +++++ board/freescale/corenet_ds/eth_superhydra.c | 12 +++++++++ board/freescale/p2041rdb/eth.c | 29 ++++++++++++++------- board/freescale/t102xrdb/eth_t102xrdb.c | 3 +++ board/freescale/t104xrdb/eth.c | 3 +++ board/freescale/t208xqds/eth_t208xqds.c | 3 +++ board/freescale/t208xrdb/eth_t208xrdb.c | 3 +++ 8 files changed, 55 insertions(+), 10 deletions(-) diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 8112c12568..6500c2fcf6 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "emi1_rgmii"); break; default: @@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * If DTSEC4 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC5 is RGMII, diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 650013bb6f..df5a69bcba 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -367,6 +367,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, @@ -434,6 +437,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index 35daa1e80f..de7b692f3f 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -317,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -353,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -557,6 +563,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the @@ -704,6 +713,9 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 396981605d..23fd619cee 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -81,17 +81,21 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, { phy_interface_t intf = fm_info_get_enet_if(port); char phy[16]; + int lane; + u8 slot; + switch (intf) { /* The RGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_RGMII) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); fdt_set_phy_handle(fdt, compat, addr, phy); - } - + break; /* The SGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_SGMII) { - int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - u8 slot; + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); if (lane < 0) return; slot = lane_to_slot[lane]; @@ -106,16 +110,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } - } - - if (intf == PHY_INTERFACE_MODE_XGMII) { + break; + case PHY_INTERFACE_MODE_XGMII: /* XAUI */ - int lane = serdes_get_first_lane(XAUI_FM1); + lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { /* The XAUI PHY is identified by the slot */ sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); fdt_set_phy_handle(fdt, compat, addr, phy); } + break; + default: + break; } } #endif /* #ifdef CONFIG_FMAN_ENET */ @@ -169,6 +175,9 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(i, riser_phy_addr[i]); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ fm_info_set_phy_address(i, i == FM1_DTSEC5 ? CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index b64590f9d7..56e6109288 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -89,6 +89,9 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 8e2f035874..b034f11d68 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -77,6 +77,9 @@ int board_eth_init(struct bd_info *bis) break; #endif case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 5044b5695b..aaa3490aaa 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -765,6 +765,9 @@ int board_eth_init(struct bd_info *bis) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4 || FM1_DTSEC10) diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index c16538850c..e77f3f7146 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -76,6 +76,9 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; From 03d095e87d4b6865deae74527c9655161a891777 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Mon, 2 Nov 2020 11:38:41 +0530 Subject: [PATCH 109/222] layerscape: fdt.c: Check for NULL return value from fdt_getprop() Check for NULL return value from fdt_getprop() in fdt_fixup_remove_jr() Signed-off-by: Priyanka Singh [Fixed checkpatch errors/warnings] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 6d3391db3b..3a04dce56f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -400,10 +400,12 @@ void fdt_fixup_remove_jr(void *blob) while (jr_node != -FDT_ERR_NOTFOUND) { reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len); - jr_offset = fdt_read_number(reg, addr_cells); - if (jr_offset == used_jr) { - fdt_del_node(blob, jr_node); - break; + if (reg) { + jr_offset = fdt_read_number(reg, addr_cells); + if (jr_offset == used_jr) { + fdt_del_node(blob, jr_node); + break; + } } jr_node = fdt_node_offset_by_compatible(blob, jr_node, "fsl,sec-v4.0-job-ring"); From 507103f8a93b51ece694a7662409408380bc828f Mon Sep 17 00:00:00 2001 From: Manish Tomar Date: Thu, 5 Nov 2020 14:08:55 +0530 Subject: [PATCH 110/222] ls1043a: Fix address for secure boot headers Update kernelheader_addr and kernelheader_addr variables with correct values for ls1043a. Signed-off-by: Manish Tomar Reviewed-by: Priyanka Jain --- include/configs/ls1043a_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 96fdd6417e..6584e39199 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -247,12 +247,12 @@ "kernelheader_start=0x800000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x60800000\0" \ + "kernelheader_addr=0x60600000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ From 4ed00656a99aa3df82397e98c4a7b04d360f2e6b Mon Sep 17 00:00:00 2001 From: Manish Tomar Date: Thu, 5 Nov 2020 14:08:56 +0530 Subject: [PATCH 111/222] lx2160a: Fix address for secure boot headers Update kernel_size_sd variable with correct value for lx2160a. Signed-off-by: Manish Tomar Reviewed-by: Priyanka Jain --- include/configs/lx2160a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 837760fe46..4bd0ddbdad 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -232,7 +232,7 @@ unsigned long get_board_ddr_clk(void); "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ - "kernel_size_sd=0x1d000\0" \ + "kernel_size_sd=0x14000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyAMA0,38400n8\0" \ BOOTENV \ From 164941c2c444830dfee6d1575207a590dcba8ae4 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Thu, 5 Nov 2020 19:28:12 +0800 Subject: [PATCH 112/222] net: pfe_eth: read PFE ESBC header flash with spi_flash_read API Read PFE ESBC header flash with spi_flash_read API - logs as follows, Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB "Synchronous Abort" handler, esr 0x96000210 elr: 000000008206db44 lr : 0000000082004ea0 (reloc) elr: 00000000b7ba6b44 lr : 00000000b7b3dea0 x0 : 00000000b79407e8 x1 : 0000000040640000 x2 : 0000000000000050 x3 : 0000000000000000 x4 : 000000000000000a x5 : 0000000000000050 x6 : 0000000000000366 x7 : 00000000b7942308 x8 : 00000000b76407c0 x9 : 0000000000000008 x10: 0000000000000044 x11: 00000000b7634d1c x12: 000000000000004f x13: 0000000000000044 x14: 00000000b7634d98 x15: 00000000b76407c0 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000b7636dd8 x19: 0000000000000000 x20: 00000000b79407d0 x21: 00000000b79407e8 x22: 0000000040640000 x23: 00000000b7634e58 x24: 0000000000000000 x25: 0000000003800000 x26: 00000000b7bdd000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000b7634d10 Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826) Resetting CPU ... Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/ls1012afrdm/Kconfig | 11 +++++++ board/freescale/ls1012aqds/Kconfig | 14 +++++++-- board/freescale/ls1012ardb/Kconfig | 18 +++++++++-- drivers/net/pfe_eth/pfe_firmware.c | 48 ++++++++++++++++++++++++++--- 4 files changed, 81 insertions(+), 10 deletions(-) diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig index 55b414e168..4ac69d7117 100644 --- a/board/freescale/ls1012afrdm/Kconfig +++ b/board/freescale/ls1012afrdm/Kconfig @@ -16,6 +16,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40400000 @@ -65,6 +69,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40020000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40060000 @@ -77,6 +85,9 @@ config SYS_LS_PFE_ESBC_ADDR hex "PFE Firmware HDR Addr" default 0x401f8000 +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index 8844557aae..59b1a87665 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -20,6 +20,14 @@ if CHAIN_OF_TRUST config SYS_LS_PPA_ESBC_ADDR hex "PPA Firmware HDR Addr" default 0x40680000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if FSL_PFE @@ -39,9 +47,9 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40700000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 5a2fa91f6b..c4acea3ae2 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -20,6 +20,14 @@ if CHAIN_OF_TRUST config SYS_LS_PPA_ESBC_ADDR hex "PPA Firmware HDR Addr" default 0x40680000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40640000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if FSL_PFE @@ -33,9 +41,9 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40640000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" @@ -89,6 +97,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x03800000 diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index d414c750d4..41999e176d 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -10,6 +10,8 @@ * files. */ +#include +#include #include #include #include @@ -24,6 +26,9 @@ #define PFE_FIRMWARE_FIT_CNF_NAME "config@1" static const void *pfe_fit_addr; +#ifdef CONFIG_CHAIN_OF_TRUST +static const void *pfe_esbc_hdr_addr; +#endif /* * PFE elf firmware loader. @@ -169,7 +174,7 @@ int pfe_spi_flash_init(void) struct spi_flash *pfe_flash; struct udevice *new; int ret = 0; - void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH); if (!addr) return -ENOMEM; @@ -179,21 +184,56 @@ int pfe_spi_flash_init(void) CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE, &new); + if (ret) { + printf("SF: failed to probe spi\n"); + free(addr); + device_remove(new, DM_REMOVE_NORMAL); + return ret; + } + pfe_flash = dev_get_uclass_priv(new); if (!pfe_flash) { printf("SF: probe for pfe failed\n"); free(addr); + device_remove(new, DM_REMOVE_NORMAL); return -ENODEV; } ret = spi_flash_read(pfe_flash, CONFIG_SYS_LS_PFE_FW_ADDR, - CONFIG_SYS_QE_FMAN_FW_LENGTH, + CONFIG_SYS_LS_PFE_FW_LENGTH, addr); - if (ret) + if (ret) { printf("SF: read for pfe failed\n"); + free(addr); + spi_flash_free(pfe_flash); + return ret; + } +#ifdef CONFIG_CHAIN_OF_TRUST + void *hdr_addr = malloc(CONFIG_SYS_LS_PFE_ESBC_LENGTH); + + if (!hdr_addr) { + free(addr); + spi_flash_free(pfe_flash); + return -ENOMEM; + } + + ret = spi_flash_read(pfe_flash, + CONFIG_SYS_LS_PFE_ESBC_ADDR, + CONFIG_SYS_LS_PFE_ESBC_LENGTH, + hdr_addr); + if (ret) { + printf("SF: failed to read pfe esbc header\n"); + free(addr); + free(hdr_addr); + spi_flash_free(pfe_flash); + return ret; + } + + pfe_esbc_hdr_addr = hdr_addr; +#endif pfe_fit_addr = addr; spi_flash_free(pfe_flash); @@ -233,7 +273,7 @@ int pfe_firmware_init(void) goto err; #ifdef CONFIG_CHAIN_OF_TRUST - pfe_esbc_hdr = CONFIG_SYS_LS_PFE_ESBC_ADDR; + pfe_esbc_hdr = (uintptr_t)pfe_esbc_hdr_addr; pfe_img_addr = (uintptr_t)pfe_fit_addr; if (fsl_check_boot_mode_secure() != 0) { /* From cbf77d201870f2d12227e2d95718a416b16ec98b Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Tue, 17 Nov 2020 16:20:04 +0100 Subject: [PATCH 113/222] armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A When booting from TF-A there is a logic that attempt to detect if the default environment is used, if this is the case it then set the `bootcmd` and `mcinitcmd` depending of the device we booted from. This detection logic is dubious as it access internals of the env implementation and it doesn't always work correctly. First of all it detect any valid environment as not being the default, so after running `env default -a && saveenv` the board doesn't boot anymore as `bootcmd` is then empty. But it also fails in some other ways, for example it always detect a default environment when redundant env is enabled on MMC, so in that case `bootcmd` is overwritten on every boot. Instead of increasing the complexity of the detection just check if `bootcmd` and `mcinitcmd` are set in the environment and set them if they are not. Signed-off-by: Alban Bedel Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27 ++++--------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ad209bde33..7553b5bce2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -33,13 +33,10 @@ #include #endif #include -#ifdef CONFIG_TFABOOT -#include -#endif #include #include #include -#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS) +#ifdef CONFIG_GIC_V3_ITS DECLARE_GLOBAL_DATA_PTR; #endif @@ -956,28 +953,12 @@ int board_late_init(void) #endif #ifdef CONFIG_TFABOOT /* - * check if gd->env_addr is default_environment; then setenv bootcmd - * and mcinitcmd. + * Set bootcmd and mcinitcmd if they don't exist in the environment. */ -#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR - if (gd->env_addr == (ulong)&default_environment[0]) { -#else - if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { -#endif + if (!env_get("bootcmd")) fsl_setenv_bootcmd(); + if (!env_get("mcinitcmd")) fsl_setenv_mcinitcmd(); - } - - /* - * If the boot mode is secure, default environment is not present then - * setenv command needs to be run by default - */ -#ifdef CONFIG_CHAIN_OF_TRUST - if ((fsl_check_boot_mode_secure() == 1)) { - fsl_setenv_bootcmd(); - fsl_setenv_mcinitcmd(); - } -#endif #endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); From 0606bf2b7c0d941f84e76f1e8dd577313c72b587 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 3 Dec 2020 16:24:29 +1300 Subject: [PATCH 114/222] powerpc: mpc85xx: Allow boards to override CONFIG_USB_MAX_CONTROLLER_COUNT If the board isn't strapped to enable USB1 then attempting to access it will result in a hang. Avoid this by allowing boards to define CONFIG_USB_MAX_CONTROLLER_COUNT. Signed-off-by: Chris Packham Reviewed-by: Priyanka Jain --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4ca1e2b325..f25ba1af09 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -116,7 +116,9 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" From bb1828f34537962cabe2f2e49f1e92d5cfee24aa Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Thu, 26 Nov 2020 10:45:16 +0000 Subject: [PATCH 115/222] drivers: ifc: add define for IFC_CSPRn TE bit To drive TE pin high is supported IFC configuration that can be used on some designs. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- include/fsl_ifc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index fd915335b2..e1e6214b0f 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -52,6 +52,8 @@ /* Machine Select */ #define CSPR_MSEL 0x00000006 #define CSPR_MSEL_SHIFT 1 +/* External Transceiver Enable */ +#define CSPR_TE 0x00000010 /* NOR */ #define CSPR_MSEL_NOR 0x00000000 /* NAND */ From 2ef53647d10ac0ec6938b37e5d9cc457ff585cdf Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Thu, 26 Nov 2020 10:52:41 +0000 Subject: [PATCH 116/222] arm: ls102xa: select USB PHY erratum's only if USB is enabled The USB support is not by default enabled on all designs, so it does not make seance to have USB specific erratum's enabled on such a designs. On our internal Hitachi-Powergrids design not using the USB controller there is a crash when accessing those specific memory locations selected by the erratum flags. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 937989b278..747059b56a 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,11 +5,11 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 select SYS_FSL_ERRATUM_A008850 - select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 - select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A008997 if USB + select SYS_FSL_ERRATUM_A009007 if USB + select SYS_FSL_ERRATUM_A009008 if USB select SYS_FSL_ERRATUM_A009663 - select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A009798 if USB select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_HAS_CCI400 From ca0c7a5e4a07337e6c2d1c53a182e436daa734c3 Mon Sep 17 00:00:00 2001 From: Hui Song Date: Fri, 4 Dec 2020 21:26:19 +0530 Subject: [PATCH 117/222] configs: lx2162aqds: Enable gpio driver in defconfig make lx2162aqds platform to enable gpio driver. Signed-off-by: Hui Song Signed-off-by: Ran Wang [Rebased] Signed-off-by: Priyanka Jain --- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index ea2c8db8c0..610e09d726 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -98,3 +98,4 @@ CONFIG_CMD_DATE=y CONFIG_RTC_PCF2127=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_MPC8XXX_GPIO=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 2eedc4842d..af7a63f6af 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -96,6 +96,7 @@ CONFIG_CMD_DATE=y CONFIG_RTC_PCF2127=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_MPC8XXX_GPIO=y CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_OPTEE_TA_AVB=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index bbad895b1b..32c583cf82 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -103,3 +103,4 @@ CONFIG_OPTEE=y CONFIG_CMD_OPTEE_RPMB=y CONFIG_OPTEE_TA_AVB=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MPC8XXX_GPIO=y From bb5eedbc7fbddc7849bb10a239facac29b615c1c Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 7 Dec 2020 09:30:59 +0200 Subject: [PATCH 118/222] ARM: dts: at91: sama5d2_icp: fix i2c eeprom compatible The correct compatible for this eeproms is microchip,24aa02e48 The previous compatible string was working up to U-boot 2020.04. Signed-off-by: Eugen Hristev Tested-by: Codrin Ciubotariu --- arch/arm/dts/at91-sama5d2_icp.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index cae8748268..f81fa60171 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -53,19 +53,19 @@ status = "okay"; eeprom@50 { - compatible = "atmel,24c32"; + compatible = "microchip,24aa02e48"; reg = <0x50>; pagesize = <16>; }; eeprom@52 { - compatible = "atmel,24c32"; + compatible = "microchip,24aa02e48"; reg = <0x52>; pagesize = <16>; }; eeprom@53 { - compatible = "atmel,24c32"; + compatible = "microchip,24aa02e48"; reg = <0x53>; pagesize = <16>; }; From fb33eaa3a26cdc37826390b6db223509230ae8e2 Mon Sep 17 00:00:00 2001 From: Brad Kim Date: Fri, 13 Nov 2020 20:47:51 +0900 Subject: [PATCH 119/222] riscv: fix the wrong swap value register Not s2 register, t1 register is correct Fortunately, it works because t1 register has a garbage value Signed-off-by: Brad Kim Reviewed-by: Lukas Auer Reviewed-by: Leo Liang --- arch/riscv/cpu/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bbc737ed9a..8589509e01 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -123,7 +123,7 @@ call_board_init_f_0: * wait for initialization to complete. */ la t0, hart_lottery - li s2, 1 + li t1, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init #else From c353f2b845bbbb7b39ecb3f0aafac889cc25a328 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 2 Dec 2020 14:36:26 +0100 Subject: [PATCH 120/222] riscv: reset after crash If an exception occurs on ARM or x86, we call panic() which will try to reset the board. Do the same on RISC-V. To avoid -Werror=format-zero-length move a '\n' to the string passed to panic. We don't need a message here as depending on CONFIG_PANIC_HANG we will either see ### ERROR ### Please RESET the board ### or resetting ... as next message. Reviewed-by: Rick Chen Signed-off-by: Heinrich Schuchardt --- arch/riscv/lib/interrupts.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 35de98e8ce..fb3ce118c1 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -27,7 +27,7 @@ static void show_efi_loaded_images(uintptr_t epc) static void show_regs(struct pt_regs *regs) { #ifdef CONFIG_SHOW_REGS - printf("SP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n", + printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n", regs->sp, regs->gp, regs->tp); printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n", regs->t0, regs->t1, regs->t2); @@ -45,7 +45,7 @@ static void show_regs(struct pt_regs *regs) regs->s7, regs->s8, regs->s9); printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n", regs->s10, regs->s11, regs->t3); - printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n\n", + printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n", regs->t4, regs->t5, regs->t6); #endif } @@ -80,12 +80,12 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc, regs->ra, tval); /* Print relocation adjustments, but only if gd is initialized */ if (gd && gd->flags & GD_FLG_RELOC) - printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n", + printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n", epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); show_efi_loaded_images(epc); - hang(); + panic("\n"); } int interrupt_init(void) From b620363feb50ad9ec0623581567beb317e0d52d7 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 1 Dec 2020 17:30:26 +0100 Subject: [PATCH 121/222] riscv: qemu: enable distro boot from scsi Booting via distro boot fails for: qemu-system-riscv64 -drive if=none,file=sct-riscv64.img,format=raw,id=mydisk \ -device ich9-ahci,id=ahci -device ide-hd,drive=mydisk,bus=ahci.0 Enable distro booting from an attached SCSI disk. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- include/configs/qemu-riscv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index aed9a4ae99..a2f33587c2 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -35,6 +35,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ + func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include From 84c3db2ea3b0e1eedb7557e4721b8880a14dcb69 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Tue, 13 Oct 2020 12:23:31 -0700 Subject: [PATCH 122/222] riscv: Fix efi header for RV32 RV32 should use PE32 format instead of PE32+ as the efi header format. This requires following changes 1. A different header magic value 2. An additional parameter known as BaseOfData. Currently, it is set to zero in absence of any usage. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/crt0_riscv_efi.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 87fe1e56f9..4aaa49ad07 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -15,11 +15,13 @@ #define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV64 +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC #else #define SIZE_LONG 4 #define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV32 +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR32_MAGIC #endif @@ -48,7 +50,7 @@ coff_header: IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ IMAGE_FILE_DEBUG_STRIPPED) optional_header: - .short IMAGE_NT_OPTIONAL_HDR64_MAGIC /* PE32+ format */ + .short PE_MAGIC /* PE32+ format */ .byte 0x02 /* MajorLinkerVersion */ .byte 0x14 /* MinorLinkerVersion */ .long _edata - _start /* SizeOfCode */ @@ -56,6 +58,9 @@ optional_header: .long 0 /* SizeOfUninitializedData */ .long _start - ImageBase /* AddressOfEntryPoint */ .long _start - ImageBase /* BaseOfCode */ +#if __riscv_xlen == 32 + .long 0 /* BaseOfData */ +#endif extra_header_fields: .quad 0 /* ImageBase */ From 9ea6952a9ab75d09d8d8958ef7e425d3879b85e3 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Thu, 12 Nov 2020 10:09:52 +0800 Subject: [PATCH 123/222] riscv: Fix efi header size for RV32 This patch depends on Atish's patch. (https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/) Modify the size of the Optional Header "Windows-Specific Fields" to fit with the specification. (https://docs.microsoft.com/en-us/windows/win32/debug/pe-format) Signed-off-by: Leo Yu-Chi Liang Cc: rick@andestech.com Cc: alankao@andestech.com Cc: atish.patra@wdc.com Cc: xypron.glpk@gmx.de Cc: bmeng.cn@gmail.com --- arch/riscv/lib/crt0_riscv_efi.S | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 4aaa49ad07..48ff89553b 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -15,13 +15,13 @@ #define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV64 -#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC #else #define SIZE_LONG 4 #define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV32 -#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR32_MAGIC +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR32_MAGIC #endif @@ -50,7 +50,7 @@ coff_header: IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ IMAGE_FILE_DEBUG_STRIPPED) optional_header: - .short PE_MAGIC /* PE32+ format */ + .short PE_MAGIC /* PE32(+) format */ .byte 0x02 /* MajorLinkerVersion */ .byte 0x14 /* MinorLinkerVersion */ .long _edata - _start /* SizeOfCode */ @@ -63,7 +63,11 @@ optional_header: #endif extra_header_fields: +#if __riscv_xlen == 32 + .long 0 /* ImageBase */ +#else .quad 0 /* ImageBase */ +#endif .long 0x20 /* SectionAlignment */ .long 0x8 /* FileAlignment */ .short 0 /* MajorOperatingSystemVersion */ @@ -83,10 +87,17 @@ extra_header_fields: .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ .short 0 /* DllCharacteristics */ +#if __riscv_xlen == 32 + .long 0 /* SizeOfStackReserve */ + .long 0 /* SizeOfStackCommit */ + .long 0 /* SizeOfHeapReserve */ + .long 0 /* SizeOfHeapCommit */ +#else .quad 0 /* SizeOfStackReserve */ .quad 0 /* SizeOfStackCommit */ .quad 0 /* SizeOfHeapReserve */ .quad 0 /* SizeOfHeapCommit */ +#endif .long 0 /* LoaderFlags */ .long 0x6 /* NumberOfRvaAndSizes */ From 9afaeec6ef8bbc6cf936d2a9c3d28caffca5bf7e Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Mon, 16 Nov 2020 17:07:41 +0800 Subject: [PATCH 124/222] riscv: Complete efi header for RV32/64 This patch depends on Atish's patch. (https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/) Add fields to complete Optional Header "Data Directories" specified in the document. (https://docs.microsoft.com/en-us/windows/win32/debug/pe-format) Signed-off-by: Leo Yu-Chi Liang Cc: rick@andestech.com Cc: alankao@andestech.com Cc: atish.patra@wdc.com Cc: xypron.glpk@gmx.de Cc: bmeng.cn@gmail.com Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/lib/crt0_riscv_efi.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 48ff89553b..e7c4d99c21 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -107,6 +107,16 @@ extra_header_fields: .quad 0 /* ExceptionTable */ .quad 0 /* CertificationTable */ .quad 0 /* BaseRelocationTable */ + .quad 0 /* Debug */ + .quad 0 /* Architecture */ + .quad 0 /* Global Ptr */ + .quad 0 /* TLS Table */ + .quad 0 /* Load Config Table */ + .quad 0 /* Bound Import */ + .quad 0 /* IAT */ + .quad 0 /* Delay Import Descriptor */ + .quad 0 /* CLR Runtime Header */ + .quad 0 /* Reserved */ /* Section table */ section_table: From 5c88b6ad400c42cabd347ad58098b149ede34281 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 14 Dec 2020 12:34:19 +0100 Subject: [PATCH 125/222] usb: dwc3-meson-g12a: always configure dr-mode dwc3_meson_g12a_force_mode() sets the dr-mode of the USB PHY. However it skips setting the mode if it matches the one done during driver probe (stored in private structure). This fails if the mode has been changed to other value and then back to initial one. Fix this by configuring the dr-mode always, regadless of the one set at the driver probe). This fixes operation of USB gadget based drivers when they are initialized for the second time. Signed-off-by: Marek Szyprowski Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 6567502cdd..6f0bac2a00 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -269,9 +269,6 @@ int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode) if (!priv->phys[USB2_OTG_PHY].dev) return -EINVAL; - if (mode == priv->otg_mode) - return 0; - if (mode == USB_DR_MODE_HOST) debug("%s: switching to Host Mode\n", __func__); else From 5ccd5d2cc98224108ae9fb09593a862c9caa5e80 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 14 Dec 2020 19:39:07 +0100 Subject: [PATCH 126/222] pinctrl: meson: fix bit manipulation of pin bias configuration This fixes the wrong usage of clrsetbits_le32(), badly setting the set argument. Fixes: c4c726c26b ("pinctrl: meson: add pinconf support") Reported-by: Anton Arapov Reported-by: Otto Meier Signed-off-by: Neil Armstrong --- drivers/pinctrl/meson/pinctrl-meson.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index d4539b02d8..5065b62436 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -216,13 +216,13 @@ static int meson_pinconf_bias_set(struct udevice *dev, unsigned int pin, } /* othewise, enable the bias and select level */ - clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 1); + clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), BIT(bit)); ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULL, ®, &bit); if (ret) return ret; clrsetbits_le32(priv->reg_pull + reg, BIT(bit), - param == PIN_CONFIG_BIAS_PULL_UP); + (param == PIN_CONFIG_BIAS_PULL_UP ? BIT(bit) : 0)); return 0; } From c2067021556a623a56b931cf3975f0fe1e195cb7 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 20 Sep 2020 12:01:30 +0200 Subject: [PATCH 127/222] doc/build/gcc.rst: required packages for SUSE Describe the packages required to build U-Boot on SUSE. Signed-off-by: Heinrich Schuchardt --- doc/build/gcc.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst index 1ceba0b699..c51b3e73b8 100644 --- a/doc/build/gcc.rst +++ b/doc/build/gcc.rst @@ -29,6 +29,26 @@ Depending on the build targets further packages maybe needed lzma-alone openssl python3 python3-coverage python3-pyelftools \ python3-pytest python3-sphinxcontrib.apidoc python3-sphinx-rtd-theme swig +SUSE based +~~~~~~~~~~ + +On suse based systems the cross compiler packages are named +cross--gcc. + +You could install GCC and the GCC 10 cross compiler for the ARMv8 architecture +with + +.. code-block:: bash + + sudo zypper install gcc cross-aarch64-gcc10 + +Depending on the build targets further packages maybe needed. + +.. code-block:: bash + + zypper install bc bison flex gcc libopenssl-devel libSDL2-devel make \ + ncurses-devel python3-devel python3-pytest swig + Prerequisites ------------- From b2107a4b77458424d60dda05e778319eadcde0ed Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 15 Oct 2020 07:40:57 +0200 Subject: [PATCH 128/222] doc: global data pointer on x86, x86_64 On x86 the global data pointer is stored in register fs. On x86_64 no register is used for the global data pointer. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- doc/develop/global_data.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/develop/global_data.rst b/doc/develop/global_data.rst index 9e7c8a24da..230ebcd860 100644 --- a/doc/develop/global_data.rst +++ b/doc/develop/global_data.rst @@ -33,8 +33,10 @@ On most architectures the global data pointer is stored in a register. +------------+----------+ | SuperH | r13 | +------------+----------+ +| x86 32bit | fs | ++------------+----------+ -The sandbox, x86, and Xtensa are notable exceptions. +The sandbox, x86_64, and Xtensa are notable exceptions. Clang for ARM does not support assigning a global register. When using Clang gd is defined as an inline function using assembly code. This adds a few bytes From ae2b48e84a6b954b56f3e68f5fd2cde3484422cd Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 30 Nov 2020 09:52:57 +0100 Subject: [PATCH 129/222] doc: allow building htmldoc with Sphinx 3+ Due to removed function c_funcptr_sig_re building with Sphinx 3 fails. With the patch building succeeds with a lot of warnings if the '-W' flag is removed from doc/Makefile. Most of the documentation is correct This follows the approach taken by the Linux kernel. Signed-off-by: Heinrich Schuchardt --- doc/conf.py | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/doc/conf.py b/doc/conf.py index 93250a6aee..ee7f201724 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -36,7 +36,34 @@ latex_engine = 'xelatex' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. -extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'cdomain', 'kfigure'] +extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'kfigure'] + +# +# cdomain is badly broken in Sphinx 3+. Leaving it out generates *most* +# of the docs correctly, but not all. +# +if major >= 3: + if (major > 3) or (minor > 0 or patch >= 2): + sys.stderr.write('''The build process with Sphinx 3+ is broken. +You will have to remove -W in doc/Makefile. +''') + # Sphinx c function parser is more pedantic with regards to type + # checking. Due to that, having macros at c:function cause problems. + # Those needed to be escaped by using c_id_attributes[] array + c_id_attributes = [ + + # include/linux/compiler.h + "__maybe_unused", + + # include/efi.h + "EFIAPI", + + # include/efi_loader.h + "__efi_runtime", + ] + +else: + extensions.append('cdomain') # The name of the math extension changed on Sphinx 1.4 if (major == 1 and minor > 3) or (major > 1): From 380c6b94dae83463d8f0d737ec548ba90dabfc8a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 12 Dec 2020 08:33:28 +0100 Subject: [PATCH 130/222] doc: move README.commands to HTML doc Reformat README.commands as reStructured text and add it to the HTML documentation as develop/commands.rst. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- doc/README.commands | 186 -------------------------------- doc/develop/commands.rst | 226 +++++++++++++++++++++++++++++++++++++++ doc/develop/index.rst | 1 + 3 files changed, 227 insertions(+), 186 deletions(-) delete mode 100644 doc/README.commands create mode 100644 doc/develop/commands.rst diff --git a/doc/README.commands b/doc/README.commands deleted file mode 100644 index 22ab063fdc..0000000000 --- a/doc/README.commands +++ /dev/null @@ -1,186 +0,0 @@ -Command definition ------------------- - -Commands are added to U-Boot by creating a new command structure. -This is done by first including command.h, then using the U_BOOT_CMD() or the -U_BOOT_CMD_COMPLETE macro to fill in a struct cmd_tbl struct. - -U_BOOT_CMD(name, maxargs, repeatable, command, "usage", "help") -U_BOOT_CMD_COMPLETE(name, maxargs, repeatable, command, "usage, "help", comp) - -name: The name of the command. THIS IS NOT a string. - -maxargs: The maximum number of arguments this function takes including - the command itself. - -repeatable: Either 0 or 1 to indicate if autorepeat is allowed. - -command: Pointer to the command function. This is the function that is - called when the command is issued. - -usage: Short description. This is a string. - -help: Long description. This is a string. The long description is - only available if CONFIG_SYS_LONGHELP is defined. - -comp: Pointer to the completion function. May be NULL. - This function is called if the user hits the TAB key while - entering the command arguments to complete the entry. Command - completion is only available if CONFIG_AUTO_COMPLETE is defined. - -Sub-command definition ----------------------- - -Likewise an array of struct cmd_tbl holding sub-commands can be created using either -of the following macros: - -* U_BOOT_CMD_MKENT(name, maxargs, repeatable, command, "usage", "help") -* U_BOOT_CMD_MKENTCOMPLETE(name, maxargs, repeatable, command, "usage, "help", - comp) - -This table has to be evaluated in the command function of the main command, e.g. - - static struct cmd_tbl cmd_sub[] = { - U_BOOT_CMD_MKENT(foo, CONFIG_SYS_MAXARGS, 1, do_foo, "", ""), - U_BOOT_CMD_MKENT(bar, CONFIG_SYS_MAXARGS, 1, do_bar, "", ""), - }; - - static int do_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) - { - struct cmd_tbl *cp; - - if (argc < 2) - return CMD_RET_USAGE; - - /* drop sub-command argument */ - argc--; - argv++; - - cp = find_cmd_tbl(argv[0], cmd_ut_sub, ARRAY_SIZE(cmd_sub)); - - if (cp) - return cp->cmd(cmdtp, flag, argc, argv); - - return CMD_RET_USAGE; - } - -Command function ----------------- - -The command function pointer has to be of type -int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]); - -cmdtp: Table entry describing the command (see above). - -flag: A bitmap which may contain the following bit: - CMD_FLAG_REPEAT - The last command is repeated. - CMD_FLAG_BOOTD - The command is called by the bootd command. - CMD_FLAG_ENV - The command is called by the run command. - -argc: Number of arguments including the command. - -argv: Arguments. - -Allowable return value are: - -CMD_RET_SUCCESS The command was successfully executed. - -CMD_RET_FAILURE The command failed. - -CMD_RET_USAGE The command was called with invalid parameters. This value - leads to the display of the usage string. - -Completion function -------------------- - -The completion function pointer has to be of type -int (*complete)(int argc, char *const argv[], char last_char, - int maxv, char *cmdv[]); - -argc: Number of arguments including the command. - -argv: Arguments. - -last_char: The last character in the command line buffer. - -maxv: Maximum number of possible completions that may be returned by - the function. - -cmdv: Used to return possible values for the last argument. The last - possible completion must be followed by NULL. - -The function returns the number of possible completions (without the terminating -NULL value). - -Behind the scene ----------------- - -The structure created is named with a special prefix and placed by -the linker in a special section using the linker lists mechanism -(see include/linker_lists.h) - -This makes it possible for the final link to extract all commands -compiled into any object code and construct a static array so the -command array can be iterated over using the linker lists macros. - -The linker lists feature ensures that the linker does not discard -these symbols when linking full U-Boot even though they are not -referenced in the source code as such. - -If a new board is defined do not forget to define the command section -by writing in u-boot.lds ($(srctree)/board/boardname/u-boot.lds) these -3 lines: - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - -Writing tests -------------- - -All new commands should have tests. Tests for existing commands are very -welcome. - -It is fairly easy to write a test for a command. Enable it in sandbox, and -then add code that runs the command and checks the output. - -Here is an example: - -/* Test 'acpi items' command */ -static int dm_test_acpi_cmd_items(struct unit_test_state *uts) -{ - struct acpi_ctx ctx; - void *buf; - - buf = malloc(BUF_SIZE); - ut_assertnonnull(buf); - - ctx.current = buf; - ut_assertok(acpi_fill_ssdt(&ctx)); - console_record_reset(); - run_command("acpi items", 0); - ut_assert_nextline("dev 'acpi-test', type 1, size 2"); - ut_assert_nextline("dev 'acpi-test2', type 1, size 2"); - ut_assert_console_end(); - - ctx.current = buf; - ut_assertok(acpi_inject_dsdt(&ctx)); - console_record_reset(); - run_command("acpi items", 0); - ut_assert_nextline("dev 'acpi-test', type 2, size 2"); - ut_assert_nextline("dev 'acpi-test2', type 2, size 2"); - ut_assert_console_end(); - - console_record_reset(); - run_command("acpi items -d", 0); - ut_assert_nextline("dev 'acpi-test', type 2, size 2"); - ut_assert_nextlines_are_dump(2); - ut_assert_nextline("%s", ""); - ut_assert_nextline("dev 'acpi-test2', type 2, size 2"); - ut_assert_nextlines_are_dump(2); - ut_assert_nextline("%s", ""); - ut_assert_console_end(); - - return 0; -} -DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst new file mode 100644 index 0000000000..c72d1b0aaa --- /dev/null +++ b/doc/develop/commands.rst @@ -0,0 +1,226 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Implementing shell commands +=========================== + +Command definition +------------------ + +Commands are added to U-Boot by creating a new command structure. +This is done by first including command.h, then using the U_BOOT_CMD() or the +U_BOOT_CMD_COMPLETE macro to fill in a struct cmd_tbl structure. + +.. code-block:: c + + U_BOOT_CMD(name, maxargs, repeatable, command, "usage", "help") + U_BOOT_CMD_COMPLETE(name, maxargs, repeatable, command, "usage, "help", comp) + +name + The name of the command. This is **not** a string. + +maxargs + The maximum number of arguments this function takes including + the command itself. + +repeatable + Either 0 or 1 to indicate if autorepeat is allowed. + +command + Pointer to the command function. This is the function that is + called when the command is issued. + +usage + Short description. This is a string. + +help + Long description. This is a string. The long description is + only available if CONFIG_SYS_LONGHELP is defined. + +comp + Pointer to the completion function. May be NULL. + This function is called if the user hits the TAB key while + entering the command arguments to complete the entry. Command + completion is only available if CONFIG_AUTO_COMPLETE is defined. + +Sub-command definition +---------------------- + +Likewise an array of struct cmd_tbl holding sub-commands can be created using +either of the following macros: + +.. code-block:: c + + U_BOOT_CMD_MKENT(name, maxargs, repeatable, command, "usage", "help") + U_BOOT_CMD_MKENTCOMPLETE(name, maxargs, repeatable, command, "usage, "help", comp) + +This table has to be evaluated in the command function of the main command, e.g. + +.. code-block:: c + + static struct cmd_tbl cmd_sub[] = { + U_BOOT_CMD_MKENT(foo, CONFIG_SYS_MAXARGS, 1, do_foo, "", ""), + U_BOOT_CMD_MKENT(bar, CONFIG_SYS_MAXARGS, 1, do_bar, "", ""), + }; + + static int do_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + struct cmd_tbl *cp; + + if (argc < 2) + return CMD_RET_USAGE; + + /* drop sub-command argument */ + argc--; + argv++; + + cp = find_cmd_tbl(argv[0], cmd_ut_sub, ARRAY_SIZE(cmd_sub)); + + if (cp) + return cp->cmd(cmdtp, flag, argc, argv); + + return CMD_RET_USAGE; + } + +Command function +---------------- + +The command function pointer has to be of type + +.. code-block:: c + + int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]); + +cmdtp + Table entry describing the command (see above). + +flag + A bitmap which may contain the following bits + + * CMD_FLAG_REPEAT - The last command is repeated. + * CMD_FLAG_BOOTD - The command is called by the bootd command. + * CMD_FLAG_ENV - The command is called by the run command. + +argc + Number of arguments including the command. + +argv + Arguments. + +Allowable return value are: + +CMD_RET_SUCCESS + The command was successfully executed. + +CMD_RET_FAILURE + The command failed. + +CMD_RET_USAGE + The command was called with invalid parameters. This value + leads to the display of the usage string. + +Completion function +------------------- + +The completion function pointer has to be of type + +.. code-block:: c + + int (*complete)(int argc, char *const argv[], char last_char, + int maxv, char *cmdv[]); + +argc + Number of arguments including the command. + +argv + Arguments. + +last_char + The last character in the command line buffer. + +maxv + Maximum number of possible completions that may be returned by + the function. + +cmdv + Used to return possible values for the last argument. The last + possible completion must be followed by NULL. + +The function returns the number of possible completions (without the terminating +NULL value). + +Behind the scene +---------------- + +The structure created is named with a special prefix and placed by +the linker in a special section using the linker lists mechanism +(see include/linker_lists.h) + +This makes it possible for the final link to extract all commands +compiled into any object code and construct a static array so the +command array can be iterated over using the linker lists macros. + +The linker lists feature ensures that the linker does not discard +these symbols when linking full U-Boot even though they are not +referenced in the source code as such. + +If a new board is defined do not forget to define the command section +by writing in u-boot.lds ($(srctree)/board/boardname/u-boot.lds) these +3 lines: + +.. code-block:: c + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + +Writing tests +------------- + +All new commands should have tests. Tests for existing commands are very +welcome. + +It is fairly easy to write a test for a command. Enable it in sandbox, and +then add code that runs the command and checks the output. + +Here is an example: + +.. code-block:: c + + /* Test 'acpi items' command */ + static int dm_test_acpi_cmd_items(struct unit_test_state *uts) + { + struct acpi_ctx ctx; + void *buf; + + buf = malloc(BUF_SIZE); + ut_assertnonnull(buf); + + ctx.current = buf; + ut_assertok(acpi_fill_ssdt(&ctx)); + console_record_reset(); + run_command("acpi items", 0); + ut_assert_nextline("dev 'acpi-test', type 1, size 2"); + ut_assert_nextline("dev 'acpi-test2', type 1, size 2"); + ut_assert_console_end(); + + ctx.current = buf; + ut_assertok(acpi_inject_dsdt(&ctx)); + console_record_reset(); + run_command("acpi items", 0); + ut_assert_nextline("dev 'acpi-test', type 2, size 2"); + ut_assert_nextline("dev 'acpi-test2', type 2, size 2"); + ut_assert_console_end(); + + console_record_reset(); + run_command("acpi items -d", 0); + ut_assert_nextline("dev 'acpi-test', type 2, size 2"); + ut_assert_nextlines_are_dump(2); + ut_assert_nextline("%s", ""); + ut_assert_nextline("dev 'acpi-test2', type 2, size 2"); + ut_assert_nextlines_are_dump(2); + ut_assert_nextline("%s", ""); + ut_assert_console_end(); + + return 0; + } + DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 89e80eab94..c95a8d6b12 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -8,6 +8,7 @@ Develop U-Boot :maxdepth: 2 coccinelle + commands crash_dumps global_data logging From d2472dedbd1682dfb618204ae289deee253506ad Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 12 Dec 2020 08:50:37 +0100 Subject: [PATCH 131/222] doc: move pstore.rst to usage/pstore.rst Let's have a separate chapter dedicated to using U-Boot. Signed-off-by: Heinrich Schuchardt --- doc/index.rst | 8 +------- doc/usage/index.rst | 12 ++++++++++++ doc/{ => usage}/pstore.rst | 0 3 files changed, 13 insertions(+), 7 deletions(-) create mode 100644 doc/usage/index.rst rename doc/{ => usage}/pstore.rst (100%) diff --git a/doc/index.rst b/doc/index.rst index 68a083b16b..4c44955d67 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -25,6 +25,7 @@ trying to get it to work optimally on a given system. :maxdepth: 2 build/index + usage/index Developer-oriented documentation -------------------------------- @@ -109,13 +110,6 @@ Android-specific features available in U-Boot. android/index -Command line ------------- -.. toctree:: - :maxdepth: 2 - - pstore.rst - Indices and tables ================== diff --git a/doc/usage/index.rst b/doc/usage/index.rst new file mode 100644 index 0000000000..af7d50650d --- /dev/null +++ b/doc/usage/index.rst @@ -0,0 +1,12 @@ +Use U-Boot +========== + +.. toctree:: + +Shell commands +-------------- + +.. toctree:: + :maxdepth: 1 + + pstore diff --git a/doc/pstore.rst b/doc/usage/pstore.rst similarity index 100% rename from doc/pstore.rst rename to doc/usage/pstore.rst From 9ebb71f70d8367b7f5030d507a43acb34252a984 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 12 Dec 2020 09:00:12 +0100 Subject: [PATCH 132/222] doc: use code-block in pstore.rst Use syntax highlighting for a Linux console session. Signed-off-by: Heinrich Schuchardt --- doc/usage/pstore.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/usage/pstore.rst b/doc/usage/pstore.rst index 8427d8fd97..8c4e5274aa 100644 --- a/doc/usage/pstore.rst +++ b/doc/usage/pstore.rst @@ -57,7 +57,9 @@ Generate kernel crash ~~~~~~~~~~~~~~~~~~~~~ For test purpose, you can generate a kernel crash by setting reboot timeout to -10 seconds and trigger a panic:: +10 seconds and trigger a panic + +.. code-block:: console $ sudo sh -c "echo 1 > /proc/sys/kernel/sysrq" $ sudo sh -c "echo 10 > /proc/sys/kernel/panic" From d0253f7e5ca1e1d79a6c42aea330cb9e2355211a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 12 Dec 2020 09:37:47 +0100 Subject: [PATCH 133/222] doc: move README.NetConsole to HTML documentation Convert README.NetConsole to reStructured text and move it to doc/usage/netconsole.rst. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- doc/usage/index.rst | 2 + .../netconsole.rst} | 54 +++++++++++-------- 2 files changed, 35 insertions(+), 21 deletions(-) rename doc/{README.NetConsole => usage/netconsole.rst} (79%) diff --git a/doc/usage/index.rst b/doc/usage/index.rst index af7d50650d..063e970981 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -3,6 +3,8 @@ Use U-Boot .. toctree:: + netconsole + Shell commands -------------- diff --git a/doc/README.NetConsole b/doc/usage/netconsole.rst similarity index 79% rename from doc/README.NetConsole rename to doc/usage/netconsole.rst index af7fc6043a..0156f0212d 100644 --- a/doc/README.NetConsole +++ b/doc/usage/netconsole.rst @@ -1,3 +1,5 @@ +Network console +=============== In U-Boot, we implemented the networked console via the standard "devices" mechanism, which means that you can switch between the @@ -6,7 +8,8 @@ serial and network input/output devices by adjusting the 'stdin' and set either of these variables to "nc". Input and output can be switched independently. -CONFIG_NETCONSOLE_BUFFER_SIZE - Override the default buffer size +The default buffer size can be overridden by setting +CONFIG_NETCONSOLE_BUFFER_SIZE. We use an environment variable 'ncip' to set the IP address and the port of the destination. The format is :. If is @@ -17,15 +20,16 @@ The source / listening port can be configured separately by setting the 'ncinport' environment variable and the destination port can be configured by setting the 'ncoutport' environment variable. -For example, if your server IP is 192.168.1.1, you could use: +For example, if your server IP is 192.168.1.1, you could use:: => setenv nc 'setenv stdout nc;setenv stdin nc' => setenv ncip 192.168.1.1 => saveenv => run nc +On the host side, please use this script to access the console -On the host side, please use this script to access the console: +.. code-block:: bash tools/netconsole [port] @@ -54,31 +58,37 @@ file for the original Ingo Molnar's documentation on how to pass parameters to the loadable module. The format of the kernel command line parameter (for the static -configuration) is as follows: +configuration) is as follows - netconsole=[src-port]@[src-ip]/[],[tgt-port]@/[tgt-macaddr] +.. code-block:: bash + + netconsole=[src-port]@[src-ip]/[],[tgt-port]@/[tgt-macaddr] where - src-port source for UDP packets - (defaults to 6665) - src-ip source IP to use - (defaults to the interface's address) - dev network interface - (defaults to eth0) - tgt-port port for logging agent - (defaults to 6666) - tgt-ip IP address for logging agent - (this is the required parameter) - tgt-macaddr ethernet MAC address for logging agent - (defaults to broadcast) +src-port + source for UDP packets (defaults to 6665) -Examples: +src-ip + source IP to use (defaults to the interface's address) + +dev + network interface (defaults to eth0) + +tgt-port + port for logging agent (defaults to 6666) + +tgt-ip + IP address for logging agent (this is the required parameter) + +tgt-macaddr + ethernet MAC address for logging agent (defaults to broadcast) + +Examples + +.. code-block:: bash netconsole=4444@10.0.0.1/eth1,9353@10.0.0.2/12:34:56:78:9a:bc - -or - netconsole=@/,@192.168.3.1/ Please note that for the Linux networked console to work, the @@ -91,6 +101,8 @@ in the ELDK-NFS-based environment. To browse the Linux network console output, use the 'netcat' tool invoked as follows: +.. code-block:: bash + nc -u -l -p 6666 Note that unlike the U-Boot implementation the Linux netconsole is From dce26c7d56ed26ba07e1da245c84690ec1edcf65 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 12 Dec 2020 10:14:22 +0100 Subject: [PATCH 134/222] doc: move README.trace to HTML documentation Convert README.trace to reStructured text and move it to develop/trace.rst. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- doc/develop/index.rst | 1 + doc/{README.trace => develop/trace.rst} | 229 ++++++++++++------------ 2 files changed, 120 insertions(+), 110 deletions(-) rename doc/{README.trace => develop/trace.rst} (64%) diff --git a/doc/develop/index.rst b/doc/develop/index.rst index c95a8d6b12..0a7e204b34 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -12,3 +12,4 @@ Develop U-Boot crash_dumps global_data logging + trace diff --git a/doc/README.trace b/doc/develop/trace.rst similarity index 64% rename from doc/README.trace rename to doc/develop/trace.rst index 2e7ca3319a..7776c48428 100644 --- a/doc/README.trace +++ b/doc/develop/trace.rst @@ -1,6 +1,5 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2013 The Chromium OS Authors. +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (c) 2013 The Chromium OS Authors. Tracing in U-Boot ================= @@ -33,73 +32,82 @@ this, follow these steps: Add the following to include/configs/sandbox.h (if not already there) -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x00100000 +.. code-block:: c + + #define CONFIG_TRACE + #define CONFIG_CMD_TRACE + #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) + #define CONFIG_TRACE_EARLY_SIZE (8 << 20) + #define CONFIG_TRACE_EARLY + #define CONFIG_TRACE_EARLY_ADDR 0x00100000 Build sandbox U-Boot with tracing enabled: -$ make FTRACE=1 O=sandbox sandbox_config -$ make FTRACE=1 O=sandbox +.. code-block:: console + + $ make FTRACE=1 O=sandbox sandbox_config + $ make FTRACE=1 O=sandbox Run sandbox, wait for a bit of trace information to appear, and then capture a trace: -$ ./sandbox/u-boot +.. code-block:: console + $ ./sandbox/u-boot -U-Boot 2013.04-rc2-00100-ga72fcef (Apr 17 2013 - 19:25:24) + U-Boot 2013.04-rc2-00100-ga72fcef (Apr 17 2013 - 19:25:24) -DRAM: 128 MiB -trace: enabled -Using default environment + DRAM: 128 MiB + trace: enabled + Using default environment -In: serial -Out: serial -Err: serial -=>trace stats - 671,406 function sites - 69,712 function calls - 0 untracked function calls - 73,373 traced function calls - 16 maximum observed call depth - 15 call depth limit - 66,491 calls not traced due to depth -=>trace stats - 671,406 function sites + In: serial + Out: serial + Err: serial + =>trace stats + 671,406 function sites + 69,712 function calls + 0 untracked function calls + 73,373 traced function calls + 16 maximum observed call depth + 15 call depth limit + 66,491 calls not traced due to depth + =>trace stats + 671,406 function sites 1,279,450 function calls - 0 untracked function calls - 950,490 traced function calls (333217 dropped due to overflow) - 16 maximum observed call depth - 15 call depth limit - 1,275,767 calls not traced due to depth -=>trace calls 0 e00000 -Call list dumped to 00000000, size 0xae0a40 -=>print -baudrate=115200 -profbase=0 -profoffset=ae0a40 -profsize=e00000 -stderr=serial -stdin=serial -stdout=serial + 0 untracked function calls + 950,490 traced function calls (333217 dropped due to overflow) + 16 maximum observed call depth + 15 call depth limit + 1,275,767 calls not traced due to depth + =>trace calls 0 e00000 + Call list dumped to 00000000, size 0xae0a40 + =>print + baudrate=115200 + profbase=0 + profoffset=ae0a40 + profsize=e00000 + stderr=serial + stdin=serial + stdout=serial -Environment size: 117/8188 bytes -=>host save host 0 trace 0 ${profoffset} -11405888 bytes written in 10 ms (1.1 GiB/s) -=>reset + Environment size: 117/8188 bytes + =>host save host 0 trace 0 ${profoffset} + 11405888 bytes written in 10 ms (1.1 GiB/s) + =>reset -Then run proftool to convert the trace information to ftrace format. +Then run proftool to convert the trace information to ftrace format -$ ./sandbox/tools/proftool -m sandbox/System.map -p trace dump-ftrace >trace.txt +.. code-block:: console -Finally run pytimechart to display it: + $ ./sandbox/tools/proftool -m sandbox/System.map -p trace dump-ftrace >trace.txt -$ pytimechart trace.txt +Finally run pytimechart to display it + +.. code-block:: console + + $ pytimechart trace.txt Using this tool you can zoom and pan across the trace, with the function calls on the left and little marks representing the start and end of each @@ -109,31 +117,31 @@ function. CONFIG Options -------------- -- CONFIG_TRACE - Enables the trace feature in U-Boot. +CONFIG_TRACE + Enables the trace feature in U-Boot. -- CONFIG_CMD_TRACE - Enables the trace command. +CONFIG_CMD_TRACE + Enables the trace command. -- CONFIG_TRACE_BUFFER_SIZE - Size of trace buffer to allocate for U-Boot. This buffer is - used after relocation, as a place to put function tracing - information. The address of the buffer is determined by - the relocation code. +CONFIG_TRACE_BUFFER_SIZE + Size of trace buffer to allocate for U-Boot. This buffer is + used after relocation, as a place to put function tracing + information. The address of the buffer is determined by + the relocation code. -- CONFIG_TRACE_EARLY - Define this to start tracing early, before relocation. +CONFIG_TRACE_EARLY + Define this to start tracing early, before relocation. -- CONFIG_TRACE_EARLY_SIZE - Size of 'early' trace buffer. Before U-Boot has relocated - it doesn't have a proper trace buffer. On many boards - you can define an area of memory to use for the trace - buffer until the 'real' trace buffer is available after - relocation. The contents of this buffer are then copied to - the real buffer. +CONFIG_TRACE_EARLY_SIZE + Size of 'early' trace buffer. Before U-Boot has relocated + it doesn't have a proper trace buffer. On many boards + you can define an area of memory to use for the trace + buffer until the 'real' trace buffer is available after + relocation. The contents of this buffer are then copied to + the real buffer. -- CONFIG_TRACE_EARLY_ADDR - Address of early trace buffer +CONFIG_TRACE_EARLY_ADDR + Address of early trace buffer Building U-Boot with Tracing Enabled @@ -191,20 +199,20 @@ Commands The trace command has variable sub-commands: -- stats - Display tracing statistics +stats + Display tracing statistics -- pause - Pause tracing +pause + Pause tracing -- resume - Resume tracing +resume + Resume tracing -- funclist [ ] - Dump a list of functions into the buffer +funclist [ ] + Dump a list of functions into the buffer -- calls [ ] - Dump function call trace into buffer +calls [ ] + Dump function call trace into buffer If the address and size are not given, these are obtained from environment variables (see below). In any case the environment variables are updated @@ -216,14 +224,14 @@ Environment Variables The following are used: -- profbase - Base address of trace output buffer +profbase + Base address of trace output buffer -- profoffset - Offset of first unwritten byte in trace output buffer +profoffset + Offset of first unwritten byte in trace output buffer -- profsize - Size of trace output buffer +profsize + Size of trace output buffer All of these are set by the 'trace calls' command. @@ -231,18 +239,18 @@ These variables keep track of the amount of data written to the trace output buffer by the 'trace' command. The trace commands which write data to the output buffer can use these to specify the buffer to write to, and update profoffset each time. This allows successive commands to append data -to the same buffer, for example: +to the same buffer, for example:: - trace funclist 10000 e00000 - trace calls + => trace funclist 10000 e00000 + => trace calls (the latter command appends more data to the buffer). -- fakegocmd - Specifies commands to run just before booting the OS. This - is a useful time to write the trace data to the host for - processing. +fakegocmd + Specifies commands to run just before booting the OS. This + is a useful time to write the trace data to the host for + processing. Writing Out Trace Data @@ -250,11 +258,11 @@ Writing Out Trace Data Once the trace data is in an output buffer in memory there are various ways to transmit it to the host. Notably you can use tftput to send the data -over a network link: +over a network link:: -fakegocmd=trace pause; usb start; set autoload n; bootp; - trace calls 10000000 1000000; - tftpput ${profbase} ${profoffset} 192.168.1.4:/tftpboot/calls + fakegocmd=trace pause; usb start; set autoload n; bootp; + trace calls 10000000 1000000; + tftpput ${profbase} ${profoffset} 192.168.1.4:/tftpboot/calls This starts up USB (to talk to an attached USB Ethernet dongle), writes a trace log to address 10000000 and sends it to a host machine using @@ -272,16 +280,17 @@ This tool must be given the U-Boot map file and the trace data received from running that U-Boot. It produces a text output file. Options - -m - Specify U-Boot map file - -p - Specifiy profile/trace file +-m + Specify U-Boot map file + +-p + Specifiy profile/trace file Commands: -- dump-ftrace - Write a text dump of the file in Linux ftrace format to stdout +dump-ftrace + Write a text dump of the file in Linux ftrace format to stdout Viewing the Trace Data @@ -301,17 +310,17 @@ The following suggestions may be helpful if you are trying to reduce boot time: 1. Enable CONFIG_BOOTSTAGE and CONFIG_BOOTSTAGE_REPORT. This should get -you are helpful overall snapshot of the boot time. + you are helpful overall snapshot of the boot time. 2. Build U-Boot with tracing and run it. Note the difference in boot time -(it is common for tracing to add 10% to the time) + (it is common for tracing to add 10% to the time) 3. Collect the trace information as descibed above. Use this to find where -all the time is being spent. + all the time is being spent. 4. Take a look at that code and see if you can optimise it. Perhaps it is -possible to speed up the initialisation of a device, or remove an unused -feature. + possible to speed up the initialisation of a device, or remove an unused + feature. 5. Rebuild, run and collect again. Compare your results. From 4cf91c886dc266df0713dfd1bd48b6f82ce4411f Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 12 Dec 2020 10:53:17 +0100 Subject: [PATCH 135/222] doc: move README.bootmenu to HTML doc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert README.bootmenu to reStructured text and move it to usage/bootmenu.rst. Adjust the text concerning configuration settings as these now are managed via Kconfig. Signed-off-by: Heinrich Schuchardt Reviewed-by: Pali Rohár --- doc/README.bootmenu | 98 ------------------------------------------ doc/usage/bootmenu.rst | 95 ++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 3 files changed, 96 insertions(+), 98 deletions(-) delete mode 100644 doc/README.bootmenu create mode 100644 doc/usage/bootmenu.rst diff --git a/doc/README.bootmenu b/doc/README.bootmenu deleted file mode 100644 index 9ff89f2e55..0000000000 --- a/doc/README.bootmenu +++ /dev/null @@ -1,98 +0,0 @@ -SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011-2012 Pali Rohár - */ - -ANSI terminal bootmenu command - -The "bootmenu" command uses U-Boot menu interfaces and provides -a simple mechanism for creating menus with different boot items. -The cursor keys "Up" and "Down" are used for navigation through -the items. Current active menu item is highlighted and can be -selected using the "Enter" key. The selection of the highlighted -menu entry invokes an U-Boot command (or a list of commands) -associated with this menu entry. - -The "bootmenu" command interprets ANSI escape sequencies, so -an ANSI terminal is required for proper menu rendering and item -selection. - -The assembling of the menu is done via a set of environment variables -"bootmenu_" and "bootmenu_delay", i.e.: - - bootmenu_delay= - bootmenu_="=<commands>" - - <delay> is the autoboot delay in seconds, after which the first - menu entry will be selected automatically - - <num> is the boot menu entry number, starting from zero - - <title> is the text of the menu entry shown on the console - or on the boot screen - - <commands> are commands which will be executed when a menu - entry is selected - - (title and commands are separated by first appearance of '=' - character in the environment variable) - -First (optional) argument of the "bootmenu" command is a delay specifier -and it overrides the delay value defined by "bootmenu_delay" environment -variable. If the environment variable "bootmenu_delay" is not set or if -the argument of the "bootmenu" command is not specified, the default delay -will be CONFIG_BOOTDELAY. If delay is 0, no menu entries will be shown on -the console (or on the screen) and the command of the first menu entry will -be called immediately. If delay is less then 0, bootmenu will be shown and -autoboot will be disabled. - -Bootmenu always adds menu entry "U-Boot console" at the end of all menu -entries specified by environment variables. When selecting this entry -the bootmenu terminates and the usual U-Boot command prompt is presented -to the user. - -Example environment: - - setenv bootmenu_0 Boot 1. kernel=bootm 0x82000000 # Set first menu entry - setenv bootmenu_1 Boot 2. kernel=bootm 0x83000000 # Set second menu entry - setenv bootmenu_2 Reset board=reset # Set third menu entry - setenv bootmenu_3 U-Boot boot order=boot # Set fourth menu entry - bootmenu 20 # Run bootmenu with autoboot delay 20s - - -The above example will be rendered as below -(without decorating rectangle): - -┌──────────────────────────────────────────┐ -│ │ -│ *** U-Boot Boot Menu *** │ -│ │ -│ Boot 1. kernel │ -│ Boot 2. kernel │ -│ Reset board │ -│ U-Boot boot order │ -│ U-Boot console │ -│ │ -│ Hit any key to stop autoboot: 20 │ -│ Press UP/DOWN to move, ENTER to select │ -│ │ -└──────────────────────────────────────────┘ - -Selected menu entry will be highlighted - it will have inverted -background and text colors. - -To enable the "bootmenu" command add following definitions to the -board config file: - - #define CONFIG_CMD_BOOTMENU - #define CONFIG_MENU - -To run the bootmenu at startup add these additional definitions: - - #define CONFIG_AUTOBOOT_KEYED - #define CONFIG_BOOTDELAY 30 - #define CONFIG_AUTOBOOT_MENU_SHOW - -When you intend to use the bootmenu on color frame buffer console, -make sure to additionally define CONFIG_CFB_CONSOLE_ANSI in the -board config file. diff --git a/doc/usage/bootmenu.rst b/doc/usage/bootmenu.rst new file mode 100644 index 0000000000..1f094ad6ed --- /dev/null +++ b/doc/usage/bootmenu.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. (C) Copyright 2011-2012 Pali Rohár <pali@kernel.org> + +bootmenu command +================ + +The "bootmenu" command uses U-Boot menu interfaces and provides +a simple mechanism for creating menus with different boot items. +The cursor keys "Up" and "Down" are used for navigation through +the items. Current active menu item is highlighted and can be +selected using the "Enter" key. The selection of the highlighted +menu entry invokes an U-Boot command (or a list of commands) +associated with this menu entry. + +The "bootmenu" command interprets ANSI escape sequencies, so +an ANSI terminal is required for proper menu rendering and item +selection. + +The assembling of the menu is done via a set of environment variables +"bootmenu_<num>" and "bootmenu_delay", i.e.:: + + bootmenu_delay=<delay> + bootmenu_<num>="<title>=<commands>" + +<delay> + is the autoboot delay in seconds, after which the first + menu entry will be selected automatically + +<num> + is the boot menu entry number, starting from zero + +<title> + is the text of the menu entry shown on the console + or on the boot screen + +<commands> + are commands which will be executed when a menu + entry is selected + +Title and commands are separated by the first appearance of a '=' +character in the value of the environment variable. + +The first (optional) argument of the "bootmenu" command is a delay specifier +and it overrides the delay value defined by "bootmenu_delay" environment +variable. If the environment variable "bootmenu_delay" is not set or if +the argument of the "bootmenu" command is not specified, the default delay +will be CONFIG_BOOTDELAY. If delay is 0, no menu entries will be shown on +the console (or on the screen) and the command of the first menu entry will +be called immediately. If delay is less then 0, bootmenu will be shown and +autoboot will be disabled. + +Bootmenu always adds menu entry "U-Boot console" at the end of all menu +entries specified by environment variables. When selecting this entry +the bootmenu terminates and the usual U-Boot command prompt is presented +to the user. + +Example environment:: + + setenv bootmenu_0 Boot 1. kernel=bootm 0x82000000 # Set first menu entry + setenv bootmenu_1 Boot 2. kernel=bootm 0x83000000 # Set second menu entry + setenv bootmenu_2 Reset board=reset # Set third menu entry + setenv bootmenu_3 U-Boot boot order=boot # Set fourth menu entry + bootmenu 20 # Run bootmenu with autoboot delay 20s + + +The above example will be rendered as below:: + + *** U-Boot Boot Menu *** + + Boot 1. kernel + Boot 2. kernel + Reset board + U-Boot boot order + U-Boot console + + Hit any key to stop autoboot: 20 + Press UP/DOWN to move, ENTER to select + +The selected menu entry will be highlighted - it will have inverted +background and text colors. + +The "bootmenu" cammand is enabled by:: + + CONFIG_CMD_BOOTMENU=y + +To run the bootmenu at startup add these additional settings:: + + CONFIG_AUTOBOOT_KEYED=y + CONFIG_BOOTDELAY=30 + CONFIG_AUTOBOOT_MENU_SHOW=y + +When you intend to use the bootmenu on a color frame buffer console, +make sure to additionally define:: + + CONFIG_CFB_CONSOLE_ANSI=y diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 063e970981..d0f5a9f26e 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -11,4 +11,5 @@ Shell commands .. toctree:: :maxdepth: 1 + bootmenu pstore From abd40a8f98ad546e34918f73865d7561a94bda44 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Sat, 12 Dec 2020 09:15:12 +0100 Subject: [PATCH 136/222] doc: uefi: remove leading $ from bash commands Use the same formatting for all bash commands. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- doc/uefi/uefi.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/uefi/uefi.rst b/doc/uefi/uefi.rst index 07eb3f01b4..dc930d9240 100644 --- a/doc/uefi/uefi.rst +++ b/doc/uefi/uefi.rst @@ -156,11 +156,11 @@ The whitelist database .. code-block:: bash - $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db/ \ + openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db/ \ -keyout db.key -out db.crt -nodes -days 365 - $ cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \ + cert-to-efi-sig-list -g 11111111-2222-3333-4444-123456789abc \ db.crt db.esl - $ sign-efi-sig-list -c KEK.crt -k KEK.key db db.esl db.auth + sign-efi-sig-list -c KEK.crt -k KEK.key db db.esl db.auth Copy the \*.auth files to media, say mmc, that is accessible from U-Boot. From c9cb6a6002fc91b045ac84b6d8fe0b34213dd320 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk <igor.opaniuk@toradex.com> Date: Thu, 29 Oct 2020 12:59:19 +0200 Subject: [PATCH 137/222] distro_bootcmd: set devtype for dhcp boot Set $devtype for DHCP boot, which can be handy for the boot.scr for detection of devtype used (for example, when the same boot.scr is used for both mmc/dhcp boot): if test ${devtype} = "dhcp"; then ... fi Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> --- include/config_distro_bootcmd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 82a3a365c5..c9862260a3 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -369,6 +369,7 @@ #endif #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ "bootcmd_dhcp=" \ + "setenv devtype " #devtypel "; " \ BOOTENV_RUN_NET_USB_START \ BOOTENV_RUN_PCI_ENUM \ "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ From 6c9a83502facf265406bc87f7a6949cc3c66872d Mon Sep 17 00:00:00 2001 From: Simon Glass <sjg@chromium.org> Date: Mon, 9 Nov 2020 07:12:24 -0700 Subject: [PATCH 138/222] x86: zimage: Update cmdline parameter to be an env var With the updated changes to bootargs substitution[1], the zboot command needs to be updated to get its command line from an environment variable instead of a memory address. This is because the command-line string must be updated to convert %U to ${uuid}, etc. In any case it is more flexible to use a environment variable and it is best to do this before the release to avoid a subsequent change. Update the command accordingly. [1] http://patchwork.ozlabs.org/project/uboot/list/?series=212481 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/lib/zimage.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 50fb16d2da..24a503d011 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -60,8 +60,8 @@ * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR * @base_ptr: Pointer to the boot parameters, typically at address * DEFAULT_SETUP_BASE - * @cmdline: Address of 'override' command line, or 0 to use the one in the - * setup block + * @cmdline: Environment variable containing the 'override' command line, or + * NULL to use the one in the setup block */ struct zboot_state { ulong bzimage_addr; @@ -70,7 +70,7 @@ struct zboot_state { ulong initrd_size; ulong load_address; struct boot_params *base_ptr; - ulong cmdline; + char *cmdline; } state; enum { @@ -406,7 +406,7 @@ static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc, state.bzimage_addr = 0; } if (argc >= 7) - state.cmdline = simple_strtoul(argv[6], NULL, 16); + state.cmdline = env_get(argv[6]); return 0; } @@ -452,7 +452,7 @@ static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc, } ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, 0, state.initrd_addr, state.initrd_size, - state.cmdline); + (ulong)state.cmdline); if (ret) { puts("Setting up boot parameters failed ...\n"); return CMD_RET_FAILURE; @@ -743,8 +743,9 @@ U_BOOT_CMDREP_COMPLETE( " initrd size - The size of the initrd image to use, if any.\n" " setup - The address of the kernel setup region, if this\n" " is not at addr\n" - " cmdline - The address of the kernel command line, to\n" - " override U-Boot's normal cmdline generation\n" + " cmdline - Environment variable containing the kernel\n" + " command line, to override U-Boot's normal\n" + " cmdline generation\n" "\n" "Sub-commands to do part of the zboot sequence:\n" "\tstart [addr [arg ...]] - specify arguments\n" From 1b6314be50df11d9c07ba3c13618bac9df838d07 Mon Sep 17 00:00:00 2001 From: Simon Glass <sjg@chromium.org> Date: Mon, 9 Nov 2020 07:12:25 -0700 Subject: [PATCH 139/222] x86: coral: Update the boot script Make use of the new bootargs substitution mechanism and zboot command syntax. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- include/configs/chromebook_coral.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index d4d32758e9..6e8e8ec170 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -15,10 +15,13 @@ "read mmc 2:2 100000 0 80; setexpr loader *001004f0; " \ "setexpr size *00100518; setexpr blocks $size / 200; " \ "read mmc 2:2 100000 80 $blocks; setexpr setup $loader - 1000; " \ - "setexpr cmdline $loader - 2000; " \ - "part uuid mmc 2:2 uuid; setenv bootargs_U $uuid; " \ - "zboot start 100000 0 0 0 $setup $cmdline; " \ - "zboot load; zboot setup; zboot dump; zboot go" + "setexpr cmdline_ptr $loader - 2000; " \ + "setexpr.s cmdline *$cmdline_ptr; " \ + "setexpr cmdline gsub %U \\\\${uuid}; " \ + "if part uuid mmc 2:2 uuid; then " \ + "zboot start 100000 0 0 0 $setup cmdline; " \ + "zboot load; zboot setup; zboot dump; zboot go;" \ + "fi" #include <configs/x86-common.h> #include <configs/x86-chromebook.h> From 21096c0af3733b63c1e9ee7772d95a0551b4fc85 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Fri, 27 Nov 2020 14:40:48 +0200 Subject: [PATCH 140/222] x86: tangier: Find proper memory region for relocation It appears that U-Boot works by luck on Intel Edison board because the amount of RAM is less than 1 GB and standard way of calculating the top of it work for this configuration. However, this won't work if the amount of RAM is different and split differently in address space. We have to find the suitable window correctly. Find proper memory region for relocation by scanning MMAP SFI table in board_get_usable_ram_top() callback. According to the address map documentation the Main Memory is guaranteed to lie in the 0..2 GB range, that's why we limit search by this range. Fixes: e71de54a4943 ("x86: Add Intel Tangier support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/cpu/tangier/sdram.c | 43 ++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index df3b9e4ec9..afb08476ed 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -196,6 +196,49 @@ unsigned int install_e820_map(unsigned int max_entries, return sfi_setup_e820(max_entries, entries); } +/* + * This function looks for the highest region of memory lower than 2GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. It + * overrides the default implementation found elsewhere which simply picks the + * end of RAM, wherever that may be. The location of the stack, the relocation + * address, and how far U-Boot is moved by relocation are set in the global + * data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + ulong dest_addr = 0; + u32 i; + + sb = sfi_search_mmap(); + if (!sb) + panic("No available memory found for relocation"); + + sfi_for_each_mentry(i, sb, mentry) { + unsigned long long start, end; + + if (mentry->type != SFI_MEM_CONV) + continue; + + start = mentry->phys_start; + end = start + (mentry->pages << 12); + + /* Filter memory over 2GB. */ + if (end > 0x7fffffffULL) + end = 0x80000000ULL; + /* Skip this region if it's too small. */ + if (end - start < total_size) + continue; + + /* Use this address if it's the largest so far. */ + if (end > dest_addr) + dest_addr = end; + } + + return dest_addr; +} + int dram_init_banksize(void) { sfi_get_bank_size(); From 5384a3f56ce19a0b394ff892c94d06092073b19b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Fri, 27 Nov 2020 14:41:16 +0200 Subject: [PATCH 141/222] x86: edison: Drop unneeded DM_PCI_COMPAT None of the driver for Edison is using DM_PCI_COMPAT, hence drop it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- configs/edison_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/edison_defconfig b/configs/edison_defconfig index c69c3f883c..ab2811eca9 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -37,7 +37,6 @@ CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_DM_PCI_COMPAT=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Intel" CONFIG_USB_GADGET_VENDOR_NUM=0x8087 From 35d29a8f55bec00bd59ed1e35fb900198c27bdb1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Wed, 2 Dec 2020 12:35:32 +0200 Subject: [PATCH 142/222] x86: edison: Add CPU to compatible string Like in the rest of x86 boards append CPU to the board compatible string. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/dts/edison.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index bc84bc892e..97cc6ec386 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -16,7 +16,7 @@ / { model = "Intel Edison"; - compatible = "intel,edison"; + compatible = "intel,edison", "intel,tangier"; aliases { serial0 = &serial0; From d067fb763680815fec05c21533d2aa23523a8b10 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Thu, 3 Dec 2020 17:40:11 +0200 Subject: [PATCH 143/222] x86: edison: BINMAN selection is specific to the board The platforms based on Intel Tangier may have different requirements how to create bootloader bundle to supply to a device. Currently the BINMAN approach is for Intel Edison only. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/cpu/tangier/Kconfig | 1 - board/intel/edison/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig index 571470c74b..d2b7edecd6 100644 --- a/arch/x86/cpu/tangier/Kconfig +++ b/arch/x86/cpu/tangier/Kconfig @@ -12,7 +12,6 @@ config INTEL_TANGIER imply MMC_SDHCI_TANGIER imply USB imply USB_DWC3 - imply BINMAN if INTEL_TANGIER diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig index 05d65445e4..23b2af4821 100644 --- a/board/intel/edison/Kconfig +++ b/board/intel/edison/Kconfig @@ -31,5 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_TANGIER select BOARD_LATE_INIT select MD5 + imply BINMAN endif From 23cdbba8b199f2f35c28e40dbb59a5e935dbbae9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Thu, 3 Dec 2020 19:45:01 +0200 Subject: [PATCH 144/222] x86: edison: Use dwc3-generic driver for Intel Edison Use generic Synopsys DesignWare 3 driver on Intel Edison. For now it's just a stub which allows future refactoring. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/cpu/tangier/Kconfig | 3 +++ arch/x86/dts/edison.dts | 4 ++++ drivers/usb/dwc3/dwc3-generic.c | 1 + 3 files changed, 8 insertions(+) diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig index d2b7edecd6..94d9d74a32 100644 --- a/arch/x86/cpu/tangier/Kconfig +++ b/arch/x86/cpu/tangier/Kconfig @@ -10,8 +10,11 @@ config INTEL_TANGIER imply MMC_SDHCI imply MMC_SDHCI_SDMA imply MMC_SDHCI_TANGIER + imply MISC imply USB + imply USB_XHCI_HCD imply USB_DWC3 + imply USB_DWC3_GENERIC if INTEL_TANGIER diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index 97cc6ec386..600d6d2562 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -105,6 +105,10 @@ reg = <0xff009000 0x1000>; }; + usb: usb@f9100000 { + compatible = "intel,tangier-dwc3"; + }; + watchdog: wdt@0 { compatible = "intel,tangier-wdt"; }; diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index a936f71d2e..222358d395 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -449,6 +449,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "rockchip,rk3328-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "qcom,dwc3" }, + { .compatible = "intel,tangier-dwc3" }, { } }; From f89e8acbc81ee6d9e57f0156c3ee6de44528c8b7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Thu, 3 Dec 2020 19:45:02 +0200 Subject: [PATCH 145/222] x86: edison: Switch to DM_USB_GADGET DM is the modern default approach for the drivers in U-Boot. It also allows to configure code via Device Tree. Move Intel Edison to use DM_USB_GADGET and drop hard coded values. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/cpu/tangier/Kconfig | 4 ---- arch/x86/dts/edison.dts | 8 ++++++++ board/intel/edison/edison.c | 35 ----------------------------------- configs/edison_defconfig | 1 + 4 files changed, 9 insertions(+), 39 deletions(-) diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig index 94d9d74a32..19aaf165d6 100644 --- a/arch/x86/cpu/tangier/Kconfig +++ b/arch/x86/cpu/tangier/Kconfig @@ -29,8 +29,4 @@ config SYS_CAR_SIZE Space in bytes in eSRAM used as Cache-As-RAM (CAR). Note this size must not exceed eSRAM's total size. -config SYS_USB_OTG_BASE - hex - default 0xf9100000 - endif diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index 600d6d2562..8d245bffc2 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -107,6 +107,14 @@ usb: usb@f9100000 { compatible = "intel,tangier-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + + dwc3: dwc3 { + reg = <0xf9100000 0x100000>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; }; watchdog: wdt@0 { diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c index 652f975515..11e7f74e47 100644 --- a/board/intel/edison/edison.c +++ b/board/intel/edison/edison.c @@ -3,15 +3,10 @@ * Copyright (c) 2017 Intel Corporation */ #include <common.h> -#include <dwc3-uboot.h> #include <env.h> #include <init.h> #include <mmc.h> #include <u-boot/md5.h> -#include <usb.h> -#include <watchdog.h> - -#include <linux/usb/gadget.h> #include <asm/cache.h> #include <asm/pmu.h> @@ -27,36 +22,6 @@ int board_early_init_r(void) return 0; } -static struct dwc3_device dwc3_device_data = { - .maximum_speed = USB_SPEED_HIGH, - .base = CONFIG_SYS_USB_OTG_BASE, - .dr_mode = USB_DR_MODE_PERIPHERAL, - .index = 0, -}; - -int usb_gadget_handle_interrupts(int controller_index) -{ - dwc3_uboot_handle_interrupt(controller_index); - WATCHDOG_RESET(); - return 0; -} - -int board_usb_init(int index, enum usb_init_type init) -{ - if (index == 0 && init == USB_INIT_DEVICE) - return dwc3_uboot_init(&dwc3_device_data); - return -EINVAL; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - if (index == 0 && init == USB_INIT_DEVICE) { - dwc3_uboot_exit(index); - return 0; - } - return -EINVAL; -} - static void assign_serial(void) { struct mmc *mmc = find_mmc_device(0); diff --git a/configs/edison_defconfig b/configs/edison_defconfig index ab2811eca9..304a172a1b 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -37,6 +37,7 @@ CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Intel" CONFIG_USB_GADGET_VENDOR_NUM=0x8087 From 621ed49d3a2ea3c45be1cf774bef48439bd566f3 Mon Sep 17 00:00:00 2001 From: Ran Wang <ran.wang_1@nxp.com> Date: Wed, 18 Nov 2020 15:49:02 +0800 Subject: [PATCH 146/222] usb: xhci: fix lack of short packet event trb handling For bulk IN transfer, the codes will set ISP flag to request event TRB being generated by xHC for the case of short packet. So when encountering buffer-cross-64K-boundary (which we will divide payload and enqueuqe more than 1 transfer TRB), and the first TRB ends up with a short packet condition it will trigger an short packet code transfer event per that flag and cause more than 1 event TRB generated for this transfer. However, current codes will only handle the first transfer event TRB then mark current transfer completed, causing next transfer failure due to event TRB mis-match. Such issue has been observed on some Layerscape platforms (LS1028A, LS1088A, etc) with USB ethernet device. This patch adds a loop to make sure the event TRB for last transfer TRB has been handled in time. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- drivers/usb/host/xhci-ring.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 13065d7ca9..d708fc928b 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -580,10 +580,13 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, int ret; u32 trb_fields[4]; u64 val_64 = virt_to_phys(buffer); + void *last_transfer_trb_addr; + int available_length; debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n", udev, pipe, buffer, length); + available_length = length; ep_index = usb_pipe_ep_index(pipe); virt_dev = ctrl->devs[slot_id]; @@ -697,7 +700,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, trb_fields[2] = length_field; trb_fields[3] = field | TRB_TYPE(TRB_NORMAL); - queue_trb(ctrl, ring, (num_trbs > 1), trb_fields); + last_transfer_trb_addr = queue_trb(ctrl, ring, (num_trbs > 1), trb_fields); --num_trbs; @@ -710,6 +713,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, giveback_first_trb(udev, ep_index, start_cycle, start_trb); +again: event = xhci_wait_for_event(ctrl, TRB_TRANSFER); if (!event) { debug("XHCI bulk transfer timed out, aborting...\n"); @@ -718,12 +722,20 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, udev->act_len = 0; return -ETIMEDOUT; } - field = le32_to_cpu(event->trans_event.flags); + if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer)) + != (uintptr_t)last_transfer_trb_addr) { + available_length -= + (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)); + xhci_acknowledge_event(ctrl); + goto again; + } + + field = le32_to_cpu(event->trans_event.flags); BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); - record_transfer_result(udev, event, length); + record_transfer_result(udev, event, available_length); xhci_acknowledge_event(ctrl); xhci_inval_cache((uintptr_t)buffer, length); From 17d5a461a0da967c511032a160278b0e1d9fd349 Mon Sep 17 00:00:00 2001 From: Hayes Wang <hayeswang@realtek.com> Date: Wed, 16 Dec 2020 17:03:22 +0800 Subject: [PATCH 147/222] eth/r8152: free previous memory if r8152_eth_probe fail The r8152_eth_probe() may allocate a memory for ss->dev_priv. It has to be freed if r8152_eth_probe() fails finally. Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/usb/eth/r8152.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 215bcbbef8..82a05a9c35 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -1647,7 +1647,7 @@ int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || !ss->ep_in || !ss->ep_out || !ss->ep_int) { debug("Problems with device\n"); - return 0; + goto error; } dev->privptr = (void *)ss; @@ -1659,7 +1659,7 @@ int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, r8152b_get_version(tp); if (rtl_ops_init(tp)) - return 0; + goto error; tp->rtl_ops.init(tp); tp->rtl_ops.up(tp); @@ -1669,6 +1669,11 @@ int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, DUPLEX_FULL); return 1; + +error: + cfree(ss->dev_priv); + ss->dev_priv = 0; + return 0; } int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, From 72294407726e9652f4ab44add3dbd118797683d1 Mon Sep 17 00:00:00 2001 From: Hayes Wang <hayeswang@realtek.com> Date: Wed, 16 Dec 2020 17:03:23 +0800 Subject: [PATCH 148/222] eth/r8152: fix the aggregation issue Remove the redundant setting for USB_RX_EARLY_SIZE. Besides, for RTL8153B, it is necessary to notify the hardware of the changes of the aggregation settings. Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/usb/eth/r8152.c | 17 +++++++++++++++-- drivers/usb/eth/r8152.h | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 82a05a9c35..5f309192b4 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -447,6 +447,12 @@ static void rtl8152_set_rx_mode(struct r8152 *tp) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); } +static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) +{ + ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, + OWN_UPDATE | OWN_CLEAR); +} + static int rtl_enable(struct r8152 *tp) { u32 ocp_data; @@ -457,6 +463,15 @@ static int rtl_enable(struct r8152 *tp) ocp_data |= PLA_CR_RE | PLA_CR_TE; ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + switch (tp->version) { + case RTL_VER_08: + case RTL_VER_09: + r8153b_rx_agg_chg_indicate(tp); + break; + default: + break; + } + rxdy_gated_en(tp, false); rtl8152_set_rx_mode(tp); @@ -525,8 +540,6 @@ static void r8153_set_rx_early_size(struct r8152 *tp) debug("** %s Invalid Device\n", __func__); break; } - - ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); } static int rtl8153_enable(struct r8152 *tp) diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h index fa57e42502..45172c055f 100644 --- a/drivers/usb/eth/r8152.h +++ b/drivers/usb/eth/r8152.h @@ -92,6 +92,7 @@ #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ #define USB_TX_DMA 0xd434 +#define USB_UPT_RXDMA_OWN 0xd437 #define USB_TOLERANCE 0xd490 #define USB_LPM_CTRL 0xd41a #define USB_BMU_RESET 0xd4b0 @@ -346,6 +347,10 @@ #define BMU_RESET_EP_IN 0x01 #define BMU_RESET_EP_OUT 0x02 +/* USB_UPT_RXDMA_OWN */ +#define OWN_UPDATE BIT(0) +#define OWN_CLEAR BIT(1) + /* USB_UPS_CTRL */ #define POWER_CUT 0x0100 From a4391365995a00f196373cddd35d99f74a9e62ff Mon Sep 17 00:00:00 2001 From: Tom Rini <trini@konsulko.com> Date: Wed, 16 Dec 2020 10:58:24 -0500 Subject: [PATCH 149/222] configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com> --- configs/apalis-imx8x_defconfig | 4 +- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 41 ++++++--------- configs/lx2162aqds_tfa_defconfig | 47 ++++++++--------- .../lx2162aqds_tfa_verified_boot_defconfig | 50 ++++++++----------- scripts/config_whitelist.txt | 1 - 5 files changed, 61 insertions(+), 82 deletions(-) diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig index e6aa575380..777d3a9354 100644 --- a/configs/apalis-imx8x_defconfig +++ b/configs/apalis-imx8x_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y @@ -21,8 +23,6 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x89000000 CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 610e09d726..2ecd6b404a 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -1,17 +1,19 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2162AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 -CONFIG_NXP_ESBC=y +CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x500000 +CONFIG_NXP_ESBC=y +CONFIG_DM_GPIO=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_AHCI=y -CONFIG_NR_DRAM_BANKS=3 +CONFIG_OF_BOARD_FIXUP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -20,41 +22,39 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y -CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y -CONFIG_CMD_GPT=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y @@ -72,6 +72,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y @@ -88,14 +90,3 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 -CONFIG_DM_RTC=y -CONFIG_DM_GPIO=y -CONFIG_CMD_DATE=y -CONFIG_RTC_PCF2127=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MPC8XXX_GPIO=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index af7a63f6af..d0d3384047 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -1,16 +1,20 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2162AQDS=y +CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_FSPI_AHB_EN_4BYTE=y -CONFIG_TFABOOT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_AHCI=y -CONFIG_NR_DRAM_BANKS=3 +CONFIG_OF_BOARD_FIXUP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -20,23 +24,20 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y -CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y -CONFIG_CMD_GPT=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y @@ -47,15 +48,21 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y @@ -73,12 +80,16 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_NXP_FSPI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y @@ -86,19 +97,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 -CONFIG_DM_RTC=y -CONFIG_DM_GPIO=y -CONFIG_CMD_DATE=y -CONFIG_RTC_PCF2127=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_OPTEE_TA_AVB=y -CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_CMD_OPTEE_RPMB=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 32c583cf82..b9261251c1 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -1,19 +1,22 @@ CONFIG_ARM=y +CONFIG_GIC_V3_ITS=y CONFIG_TARGET_LX2162AQDS=y +CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_FSPI_AHB_EN_4BYTE=y -CONFIG_TFABOOT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_AHCI=y -CONFIG_NR_DRAM_BANKS=3 -CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_FIT_SIGNATURE=y -CONFIG_RSA=y +CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 @@ -22,23 +25,20 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_MISC_INIT_R=y -CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y -CONFIG_CMD_GPT=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y @@ -49,15 +49,21 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y @@ -75,12 +81,16 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_NXP_FSPI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y @@ -88,19 +98,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_GIC_V3_ITS=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0 -CONFIG_DM_RTC=y -CONFIG_DM_GPIO=y -CONFIG_CMD_DATE=y -CONFIG_RTC_PCF2127=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_CMD_OPTEE_RPMB=y -CONFIG_OPTEE_TA_AVB=y -CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MPC8XXX_GPIO=y diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c0339dcc00..55acc38d06 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -961,7 +961,6 @@ CONFIG_LCD_MENU CONFIG_LD9040 CONFIG_LEGACY CONFIG_LEGACY_BOOTCMD_ENV -CONFIG_LG4573 CONFIG_LINUX CONFIG_LINUX_RESET_VEC CONFIG_LITTLETON_LCD From 9ca54ef263c050c715a20945a645e5d7c6bdcfff Mon Sep 17 00:00:00 2001 From: Jagan Teki <jagan@amarulasolutions.com> Date: Fri, 23 Oct 2020 13:51:01 +0530 Subject: [PATCH 150/222] cl-som-imx7: Switch to DM_SPI/DM_SPI_FLASH Enable DM_SPI/DM_SPI_FLASH with associated config options. Build fine, but not tested. Cc: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- configs/cl-som-imx7_defconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index c174ed848b..4916d996c1 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y CONFIG_TARGET_CL_SOM_IMX7=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -39,7 +40,6 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -52,17 +52,19 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_MMC is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_CMD_PCA953X=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_ATMEL=y @@ -79,6 +81,7 @@ CONFIG_MII=y CONFIG_DM_REGULATOR=y CONFIG_MXC_UART=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y From 538fe2f4eccb444ffab9305f45ec286c8e4e46ee Mon Sep 17 00:00:00 2001 From: Jagan Teki <jagan@amarulasolutions.com> Date: Fri, 23 Oct 2020 13:56:49 +0530 Subject: [PATCH 151/222] cm_fx6: Switch to full DM-aware Enable DM_SPI/DM_SPI_FLASH with a related config option. Build fine, but not tested. Cc: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- configs/cm_fx6_defconfig | 3 +++ include/configs/cm_fx6.h | 7 ------- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 654a4fcc48..86e4135b11 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -54,10 +54,12 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)" CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y # CONFIG_DWC_AHSATA_AHCI is not set @@ -85,6 +87,7 @@ CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 72eb19b581..9892fb8817 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -150,13 +150,6 @@ /* APBH DMA is required for NAND support */ #endif -/* SPI Flash Configs */ -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD -#endif - /* Ethernet */ #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_PHYADDR 0 From 03a673cf49e8d2b1a3314f0f51390198e27b6d71 Mon Sep 17 00:00:00 2001 From: Jagan Teki <jagan@amarulasolutions.com> Date: Fri, 23 Oct 2020 14:02:48 +0530 Subject: [PATCH 152/222] dh_imx6: Switch to full DM-aware Enable DM_SPI/DM_SPI_FLASH with a related config option. Build fine, but not tested. Cc: Ludwig Zenz <lzenz@dh-electronics.de> Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- configs/dh_imx6_defconfig | 3 +++ include/configs/dh_imx6.h | 6 ------ 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 0d1f0cfeac..fbb8a3a0a5 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -51,12 +51,14 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_BOOTCOUNT_LIMIT=y @@ -103,4 +105,5 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y +# CONFIG_SPL_WDT is not set CONFIG_BZIP2=y diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 008a70a7c2..4a469af5e6 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -52,12 +52,6 @@ /* SATA Configs */ #define CONFIG_LBA48 -/* SPI Flash Configs */ -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#endif - /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE From 46c5391b3d047fefbf6d852130299196061c7d6f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay <patrick.delaunay@st.com> Date: Thu, 15 Oct 2020 17:18:17 +0200 Subject: [PATCH 153/222] spi: migrate trace to dev and log macro in spi uclass Define LOG_CATEGORY and change printf and pr_* to dev_ (when dev is available) or log_ macro. This patch adds the support of logging feature with log command (filtering, display of device name in trace) and allows to suppress traces via the syslog driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/spi-uclass.c | 51 ++++++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 55a8eed890..d5a1e3a676 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -3,12 +3,15 @@ * Copyright (c) 2014 Google, Inc */ +#define LOG_CATEGORY UCLASS_SPI + #include <common.h> #include <dm.h> #include <errno.h> #include <log.h> #include <malloc.h> #include <spi.h> +#include <dm/device_compat.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> #include <dm/lists.h> @@ -29,7 +32,7 @@ static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) else ret = -EINVAL; if (ret) { - printf("Cannot set speed (err=%d)\n", ret); + dev_err(bus, "Cannot set speed (err=%d)\n", ret); return ret; } @@ -38,7 +41,7 @@ static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) else ret = -EINVAL; if (ret) { - printf("Cannot set mode (err=%d)\n", ret); + dev_err(bus, "Cannot set mode (err=%d)\n", ret); return ret; } @@ -138,13 +141,15 @@ int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, ret = spi_xfer(slave, n_opcode * 8, opcode, NULL, flags); if (ret) { - debug("spi: failed to send command (%zu bytes): %d\n", - n_opcode, ret); + dev_dbg(slave->dev, + "spi: failed to send command (%zu bytes): %d\n", + n_opcode, ret); } else if (n_buf != 0) { ret = spi_xfer(slave, n_buf * 8, txbuf, rxbuf, SPI_XFER_END); if (ret) - debug("spi: failed to transfer %zu bytes of data: %d\n", - n_buf, ret); + dev_dbg(slave->dev, + "spi: failed to transfer %zu bytes of data: %d\n", + n_buf, ret); } return ret; @@ -248,7 +253,7 @@ int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp) } if (ret) { - printf("Invalid cs %d (err=%d)\n", cs, ret); + dev_err(bus, "Invalid cs %d (err=%d)\n", cs, ret); return ret; } @@ -257,7 +262,7 @@ int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp) struct dm_spi_slave_platdata *plat; plat = dev_get_parent_platdata(dev); - debug("%s: plat=%p, cs=%d\n", __func__, plat, plat->cs); + dev_dbg(bus, "%s: plat=%p, cs=%d\n", __func__, plat, plat->cs); if (plat->cs == cs) { *devp = dev; return 0; @@ -275,7 +280,7 @@ int spi_cs_is_valid(unsigned int busnum, unsigned int cs) ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus); if (ret) { - debug("%s: No bus %d\n", __func__, busnum); + log_debug("%s: No bus %d\n", __func__, busnum); return ret; } @@ -304,12 +309,12 @@ int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus); if (ret) { - debug("%s: No bus %d\n", __func__, busnum); + log_debug("%s: No bus %d\n", __func__, busnum); return ret; } ret = spi_find_chip_select(bus, cs, &dev); if (ret) { - debug("%s: No cs %d\n", __func__, cs); + dev_dbg(bus, "%s: No cs %d\n", __func__, cs); return ret; } *busp = bus; @@ -334,7 +339,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus); #endif if (ret) { - printf("Invalid bus %d (err=%d)\n", busnum, ret); + log_err("Invalid bus %d (err=%d)\n", busnum, ret); return ret; } ret = spi_find_chip_select(bus, cs, &dev); @@ -345,12 +350,12 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, * SPI flash chip - we will bind to the correct driver. */ if (ret == -ENODEV && drv_name) { - debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", - __func__, dev_name, busnum, cs, drv_name); + dev_dbg(bus, "%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", + __func__, dev_name, busnum, cs, drv_name); ret = device_bind_driver(bus, drv_name, dev_name, &dev); if (ret) { - debug("%s: Unable to bind driver (ret=%d)\n", __func__, - ret); + dev_dbg(bus, "%s: Unable to bind driver (ret=%d)\n", + __func__, ret); return ret; } plat = dev_get_parent_platdata(dev); @@ -358,15 +363,15 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, if (speed) { plat->max_hz = speed; } else { - printf("Warning: SPI speed fallback to %u kHz\n", - SPI_DEFAULT_SPEED_HZ / 1000); + dev_warn(bus, + "Warning: SPI speed fallback to %u kHz\n", + SPI_DEFAULT_SPEED_HZ / 1000); plat->max_hz = SPI_DEFAULT_SPEED_HZ; } plat->mode = mode; created = true; } else if (ret) { - printf("Invalid chip select %d:%d (err=%d)\n", busnum, cs, - ret); + dev_err(bus, "Invalid chip select %d:%d (err=%d)\n", busnum, cs, ret); return ret; } @@ -394,13 +399,13 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, *busp = bus; *devp = slave; - debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp); + log_debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp); return 0; err: - debug("%s: Error path, created=%d, device '%s'\n", __func__, - created, dev->name); + log_debug("%s: Error path, created=%d, device '%s'\n", __func__, + created, dev->name); if (created) { device_remove(dev, DM_REMOVE_NORMAL); device_unbind(dev); From 1910aca0f1a34d3762145e4ec4b718b9dace115f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Date: Thu, 17 Sep 2020 15:50:30 +0100 Subject: [PATCH 154/222] mtd: spi-nor-ids: Add Winbond W25M512JV flash entry Add Winbond W25M512JV flash device description. Linux already has the flash entry present. A snippet below: { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...}, Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 09e8196048..c361371b79 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -320,6 +320,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ From 9dddead735389c46b85840a80a0be312a4b35672 Mon Sep 17 00:00:00 2001 From: Biju Das <biju.das.jz@bp.renesas.com> Date: Tue, 29 Sep 2020 11:04:02 +0100 Subject: [PATCH 155/222] mtd: spi-nor-ids: Add Winbond W25M512JW flash entry Add Winbond W25M512JW flash device description. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index c361371b79..be562f25f5 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -320,6 +320,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XMC From d1b6b942f8c0d20150987a3437031c35e64fecb7 Mon Sep 17 00:00:00 2001 From: Robert Marko <robert.marko@sartura.hr> Date: Fri, 23 Oct 2020 14:22:38 +0530 Subject: [PATCH 156/222] mtd: spi-nor-ids: Add SECT_4K to mx25l12805d According to the mx25l12805d datasheet it supports using 4K or 64K sectors. So lets add the SECT_4K to enable 4K sector usage. Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index be562f25f5..2812e600ea 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -150,7 +150,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, - { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, + { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) }, { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, From 55a2bec7b570fdbc32211e487f2a4d51ccd56c8c Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 7 Aug 2020 13:13:31 -0400 Subject: [PATCH 157/222] doc: Fix typo in FIT documentation u_boot should be u-boot Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- doc/uImage.FIT/source_file_format.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 884a58456f..633f227c59 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -172,7 +172,7 @@ the '/images' node should have the following layout: - os : OS name, mandatory for types "kernel" and "ramdisk". Valid OS names are: "openbsd", "netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix", "solaris", "irix", "sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx", - "u_boot", "rtems", "unity", "integrity". + "u-boot", "rtems", "unity", "integrity". - arch : Architecture name, mandatory for types: "standalone", "kernel", "firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha", "arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc", From 40fc33fae0bf72ddad8a0ed48130180acb74ffb2 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 7 Aug 2020 13:13:34 -0400 Subject: [PATCH 158/222] spi: Fix typo in header Spelling. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- include/spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/spi.h b/include/spi.h index ef8c1f6692..2d34e4af11 100644 --- a/include/spi.h +++ b/include/spi.h @@ -51,7 +51,7 @@ struct dm_spi_bus { * struct from a spi_slave, use dev_get_parent_platdata(dev) or * dev_get_parent_platdata(slave->dev). * - * This data is immuatable. Each time the device is probed, @max_hz and @mode + * This data is immutable. Each time the device is probed, @max_hz and @mode * will be copied to struct spi_slave. * * @cs: Chip select number (0..n-1) From 987f1e56edb161431175a4bdb058870d1e4da541 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf <frieder.schrempf@kontron.de> Date: Mon, 22 Jun 2020 16:16:31 +0300 Subject: [PATCH 159/222] mtd: spinand: Stop using spinand->oobbuf for buffering bad block markers For reading and writing the bad block markers, spinand->oobbuf is currently used as a buffer for the marker bytes. During the underlying read and write operations to actually get/set the content of the OOB area, the content of spinand->oobbuf is reused and changed by accessing it through spinand->oobbuf and/or spinand->databuf. This is a flaw in the original design of the SPI NAND core and at the latest from 13c15e07eedf ("mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache") on, it results in not having the bad block marker written at all, as the spinand->oobbuf is cleared to 0xff after setting the marker bytes to zero. To fix it, we now just store the two bytes for the marker on the stack and let the read/write operations copy it from/to the page buffer later. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de --- drivers/mtd/nand/spi/core.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 8c7e07d463..77188ec176 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -655,16 +655,16 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) { struct spinand_device *spinand = nand_to_spinand(nand); + u8 marker[2] = { }; struct nand_page_io_req req = { .pos = *pos, - .ooblen = 2, + .ooblen = sizeof(marker), .ooboffs = 0, - .oobbuf.in = spinand->oobbuf, + .oobbuf.in = marker, .mode = MTD_OPS_RAW, }; int ret; - memset(spinand->oobbuf, 0, 2); ret = spinand_select_target(spinand, pos->target); if (ret) return ret; @@ -673,7 +673,7 @@ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) if (ret) return ret; - if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff) + if (marker[0] != 0xff || marker[1] != 0xff) return true; return false; @@ -702,11 +702,12 @@ static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) { struct spinand_device *spinand = nand_to_spinand(nand); + u8 marker[2] = { }; struct nand_page_io_req req = { .pos = *pos, .ooboffs = 0, - .ooblen = 2, - .oobbuf.out = spinand->oobbuf, + .ooblen = sizeof(marker), + .oobbuf.out = marker, }; int ret; @@ -723,7 +724,6 @@ static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) if (ret) return ret; - memset(spinand->oobbuf, 0, 2); return spinand_write_page(spinand, &req); } From e6108004e66b7f0a8a2b9109d339558a1043b7de Mon Sep 17 00:00:00 2001 From: Frieder Schrempf <frieder.schrempf@kontron.de> Date: Mon, 22 Jun 2020 16:16:32 +0300 Subject: [PATCH 160/222] mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOB When writing the bad block marker to the OOB area the access mode should be set to MTD_OPS_RAW as it is done for reading the marker. Currently this only works because req.mode is initialized to MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for req.mode != MTD_OPS_AUTO_OOB. Fix this by explicitly setting req.mode to MTD_OPS_RAW. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de --- drivers/mtd/nand/spi/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 77188ec176..9ab43d948b 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -708,6 +708,7 @@ static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) .ooboffs = 0, .ooblen = sizeof(marker), .oobbuf.out = marker, + .mode = MTD_OPS_RAW, }; int ret; From 031b89e51b0fde5aabc258c2eb9c3f913f375f65 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf <frieder.schrempf@kontron.de> Date: Mon, 22 Jun 2020 16:16:33 +0300 Subject: [PATCH 161/222] mtd: spinand: Do not erase the block before writing a bad block marker Currently when marking a block, we use spinand_erase_op() to erase the block before writing the marker to the OOB area. Doing so without waiting for the operation to finish can lead to the marking failing silently and no bad block marker being written to the flash. In fact we don't need to do an erase at all before writing the BBM. The ECC is disabled for raw accesses to the OOB data and we don't need to work around any issues with chips reporting ECC errors as it is known to be the case for raw NAND. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de --- drivers/mtd/nand/spi/core.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 9ab43d948b..36d040038e 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -712,19 +712,10 @@ static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) }; int ret; - /* Erase block before marking it bad. */ ret = spinand_select_target(spinand, pos->target); if (ret) return ret; - ret = spinand_write_enable_op(spinand); - if (ret) - return ret; - - ret = spinand_erase_op(spinand, pos); - if (ret) - return ret; - return spinand_write_page(spinand, &req); } From 25f068aa3e8aebda96a1a908a0bebd56f59374ca Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy <mikhail.kshevetskiy@oktetlabs.ru> Date: Mon, 22 Jun 2020 16:16:34 +0300 Subject: [PATCH 162/222] mtd: spinand: enable erasing of bad mtd blocks U-Boot is able to erase bad mtd blocks on raw nand devices, but this is not true for spinand flashes. Lets enable this feature for spinand flashes as well. This is extemelly useful for flash testing. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@oktetlabs.ru> --- drivers/mtd/nand/core.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 6fbd24ba74..219efdc895 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -130,10 +130,18 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved); */ int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) { + unsigned int entry; + if (nanddev_isbad(nand, pos) || nanddev_isreserved(nand, pos)) { pr_warn("attempt to erase a bad/reserved block @%llx\n", nanddev_pos_to_offs(nand, pos)); - return -EIO; + if (nanddev_isreserved(nand, pos)) + return -EIO; + + /* remove bad block from BBT */ + entry = nanddev_bbt_pos_to_entry(nand, pos); + nanddev_bbt_set_block_status(nand, entry, + NAND_BBT_BLOCK_STATUS_UNKNOWN); } return nand->ops->erase(nand, pos); From caf110798ccca5d1fe7e75ae73397212262b9ee9 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:43 -0400 Subject: [PATCH 163/222] spi: dw: Fix driving MOSI low while recieving The resting state of MOSI is high when nothing is driving it. If we drive it low while recieving, it looks like we are transmitting 0x00 instead of transmitting nothing. This can confuse slaves (like SD cards) which allow new commands to be sent over MOSI while they are returning data over MISO. The return of MOSI from 0 to 1 at the end of recieving a byte can look like a start bit and a transmission bit to an SD card. This will cause the card to become out-of-sync with the SPI device, as it thinks the device has already started transmitting two bytes of a new command. The mmc-spi driver will not detect the R1 response from the SD card, since it is sent too early, and offset by two bits. This patch fixes transfer errors when using SD cards with dw spi. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 2559aac2e9..74372171aa 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -322,7 +322,7 @@ static inline u32 rx_max(struct dw_spi_priv *priv) static void dw_writer(struct dw_spi_priv *priv) { u32 max = tx_max(priv); - u16 txw = 0; + u16 txw = 0xFFFF; while (max--) { /* Set the tx word if the transfer's original "tx" is not null */ From 1b3dd491e6fc787f47a3ae91f6a58aeb97466140 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:44 -0400 Subject: [PATCH 164/222] spi: dw: Convert calls to debug to dev_* This allows different log levels to be enabled or disabled depending on the desired level of verbosity. In particular, it allows for general debug information to be printed while excluding more verbose logging which may interfere with timing. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 38 ++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 74372171aa..b23655d4d9 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -9,6 +9,7 @@ * Copyright (c) 2009, Intel Corporation. */ +#define LOG_CATEGORY UCLASS_SPI #include <common.h> #include <log.h> #include <asm-generic/gpio.h> @@ -139,7 +140,7 @@ static int request_gpio_cs(struct udevice *bus) return 0; if (ret < 0) { - printf("Error: %d: Can't get %s gpio!\n", ret, bus->name); + dev_err(bus, "Couldn't request gpio! (error %d)\n", ret); return ret; } @@ -148,7 +149,7 @@ static int request_gpio_cs(struct udevice *bus) GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); } - debug("%s: used external gpio for CS management\n", __func__); + dev_dbg(bus, "Using external gpio for CS management\n"); #endif return 0; } @@ -162,8 +163,7 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus) /* Use 500KHz as a suitable default */ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000); - debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, - plat->frequency); + dev_info(bus, "max-frequency=%d\n", plat->frequency); return request_gpio_cs(bus); } @@ -174,7 +174,7 @@ static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) } /* Restart the controller, disable all interrupts, clean rx fifo */ -static void spi_hw_init(struct dw_spi_priv *priv) +static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv) { spi_enable_chip(priv, 0); dw_write(priv, DW_SPI_IMR, 0xff); @@ -196,7 +196,7 @@ static void spi_hw_init(struct dw_spi_priv *priv) priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_write(priv, DW_SPI_TXFLTR, 0); } - debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); + dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len); } /* @@ -221,8 +221,7 @@ __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate) if (!*rate) goto err_rate; - debug("%s: get spi controller clk via device tree: %lu Hz\n", - __func__, *rate); + dev_dbg(bus, "Got clock via device tree: %lu Hz\n", *rate); return 0; @@ -247,14 +246,16 @@ static int dw_spi_reset(struct udevice *bus) if (ret == -ENOENT || ret == -ENOTSUPP) return 0; - dev_warn(bus, "Can't get reset: %d\n", ret); + dev_warn(bus, "Couldn't find/assert reset device (error %d)\n", + ret); return ret; } ret = reset_deassert_bulk(&priv->resets); if (ret) { reset_release_bulk(&priv->resets); - dev_err(bus, "Failed to reset: %d\n", ret); + dev_err(bus, "Failed to de-assert reset for SPI (error %d)\n", + ret); return ret; } @@ -284,7 +285,7 @@ static int dw_spi_probe(struct udevice *bus) priv->tmode = 0; /* Tx & Rx */ /* Basic HW init */ - spi_hw_init(priv); + spi_hw_init(bus, priv); return 0; } @@ -333,7 +334,7 @@ static void dw_writer(struct dw_spi_priv *priv) txw = *(u16 *)(priv->tx); } dw_write(priv, DW_SPI_DR, txw); - debug("%s: tx=0x%02x\n", __func__, txw); + log_content("tx=0x%02x\n", txw); priv->tx += priv->bits_per_word >> 3; } } @@ -345,7 +346,7 @@ static void dw_reader(struct dw_spi_priv *priv) while (max--) { rxw = dw_read(priv, DW_SPI_DR); - debug("%s: rx=0x%02x\n", __func__, rxw); + log_content("rx=0x%02x\n", rxw); /* Care about rx if the transfer's original "rx" is not null */ if (priv->rx_end - priv->len) { @@ -400,7 +401,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, /* spi core configured to do 8 bit transfers */ if (bitlen % 8) { - debug("Non byte aligned SPI transfer.\n"); + dev_err(dev, "Non byte aligned SPI transfer.\n"); return -1; } @@ -427,7 +428,6 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, cr0 |= (priv->tmode << SPI_TMOD_OFFSET); priv->len = bitlen >> 3; - debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len); priv->tx = (void *)tx; priv->tx_end = priv->tx + priv->len; @@ -437,7 +437,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, /* Disable controller before writing control registers */ spi_enable_chip(priv, 0); - debug("%s: cr0=%08x\n", __func__, cr0); + dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx, + priv->len); /* Reprogram cr0 only if changed */ if (dw_read(priv, DW_SPI_CTRL0) != cr0) dw_write(priv, DW_SPI_CTRL0, cr0); @@ -497,8 +498,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed) spi_enable_chip(priv, 1); priv->freq = speed; - debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs, - priv->freq, clk_div); + dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div); return 0; } @@ -513,7 +513,7 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode) * real transfer function. */ priv->mode = mode; - debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + dev_dbg(bus, "mode=%d\n", priv->mode); return 0; } From 13fc44e2223b90290a2bfdfe97d3a9d37b90c7a0 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:45 -0400 Subject: [PATCH 165/222] spi: dw: Rename "cs-gpio" to "cs-gpios" This property is named differently than other SPI drivers with the same property, as well as the property as used in Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/arc/dts/axs10x_mb.dtsi | 3 ++- arch/arc/dts/hsdk-common.dtsi | 3 ++- drivers/spi/designware_spi.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi index 33b0593438..daf7ca68fb 100644 --- a/arch/arc/dts/axs10x_mb.dtsi +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -97,7 +97,8 @@ spi-max-frequency = <4000000>; clocks = <&apbclk>; clock-names = "spi_clk"; - cs-gpio = <&cs_gpio 0>; + num-cs = <1>; + cs-gpios = <&cs_gpio 0>; spi_flash@0 { compatible = "jedec,spi-nor"; reg = <0>; diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi index 9aa10e4b25..a4b348b948 100644 --- a/arch/arc/dts/hsdk-common.dtsi +++ b/arch/arc/dts/hsdk-common.dtsi @@ -135,7 +135,8 @@ spi-max-frequency = <4000000>; clocks = <&cgu_clk CLK_SYS_SPI_REF>; clock-names = "spi_clk"; - cs-gpio = <&cs_gpio 0>; + num-cs = <1>; + cs-gpios = <&cs_gpio 0>; spi_flash@0 { compatible = "jedec,spi-nor"; reg = <0>; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index b23655d4d9..32de33f695 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -135,7 +135,8 @@ static int request_gpio_cs(struct udevice *bus) int ret; /* External chip select gpio line is optional */ - ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0); + ret = gpio_request_by_name(bus, "cs-gpios", 0, &priv->cs_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret == -ENOENT) return 0; From c785f43ffdf402ecd109bbce972c25e32bc4c85b Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:46 -0400 Subject: [PATCH 166/222] spi: dw: Use generic function to read reg address Using an fdt-specific function causes problems when compiled with a live tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 32de33f695..e8ba80ef41 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -160,6 +160,8 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus) struct dw_spi_platdata *plat = bus->platdata; plat->regs = dev_read_addr_ptr(bus); + if (!plat->regs) + return -EINVAL; /* Use 500KHz as a suitable default */ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", From 3004034989ac6d4752c384a5c74a69f37b8ce9d1 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:47 -0400 Subject: [PATCH 167/222] spi: dw: Rename registers to match datasheet A few registers had slightly different names from what is in the datasheet. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index e8ba80ef41..8abcdde8a3 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -27,14 +27,14 @@ #include <asm/io.h> /* Register offsets */ -#define DW_SPI_CTRL0 0x00 -#define DW_SPI_CTRL1 0x04 +#define DW_SPI_CTRLR0 0x00 +#define DW_SPI_CTRLR1 0x04 #define DW_SPI_SSIENR 0x08 #define DW_SPI_MWCR 0x0c #define DW_SPI_SER 0x10 #define DW_SPI_BAUDR 0x14 -#define DW_SPI_TXFLTR 0x18 -#define DW_SPI_RXFLTR 0x1c +#define DW_SPI_TXFTLR 0x18 +#define DW_SPI_RXFTLR 0x1c #define DW_SPI_TXFLR 0x20 #define DW_SPI_RXFLR 0x24 #define DW_SPI_SR 0x28 @@ -191,13 +191,13 @@ static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv) u32 fifo; for (fifo = 1; fifo < 256; fifo++) { - dw_write(priv, DW_SPI_TXFLTR, fifo); - if (fifo != dw_read(priv, DW_SPI_TXFLTR)) + dw_write(priv, DW_SPI_TXFTLR, fifo); + if (fifo != dw_read(priv, DW_SPI_TXFTLR)) break; } priv->fifo_len = (fifo == 1) ? 0 : fifo; - dw_write(priv, DW_SPI_TXFLTR, 0); + dw_write(priv, DW_SPI_TXFTLR, 0); } dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len); } @@ -443,8 +443,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx, priv->len); /* Reprogram cr0 only if changed */ - if (dw_read(priv, DW_SPI_CTRL0) != cr0) - dw_write(priv, DW_SPI_CTRL0, cr0); + if (dw_read(priv, DW_SPI_CTRLR0) != cr0) + dw_write(priv, DW_SPI_CTRLR0, cr0); /* * Configure the desired SS (slave select 0...3) in the controller From 934beab88248fa8e9a07f2f046427006156dca97 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:48 -0400 Subject: [PATCH 168/222] spi: dw: Remove spi_enable_chip This function does nothing but wrap dw_write. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 8abcdde8a3..89a8266052 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -171,17 +171,12 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus) return request_gpio_cs(bus); } -static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) -{ - dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); -} - /* Restart the controller, disable all interrupts, clean rx fifo */ static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv) { - spi_enable_chip(priv, 0); + dw_write(priv, DW_SPI_SSIENR, 0); dw_write(priv, DW_SPI_IMR, 0xff); - spi_enable_chip(priv, 1); + dw_write(priv, DW_SPI_SSIENR, 1); /* * Try to detect the FIFO depth if not set by interface driver, @@ -438,7 +433,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, priv->rx_end = priv->rx + priv->len; /* Disable controller before writing control registers */ - spi_enable_chip(priv, 0); + dw_write(priv, DW_SPI_SSIENR, 0); dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx, priv->len); @@ -455,7 +450,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, dw_write(priv, DW_SPI_SER, 1 << cs); /* Enable controller after writing control registers */ - spi_enable_chip(priv, 1); + dw_write(priv, DW_SPI_SSIENR, 1); /* Start transfer in a polling loop */ ret = poll_transfer(priv); @@ -490,7 +485,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed) speed = plat->frequency; /* Disable controller before writing control registers */ - spi_enable_chip(priv, 0); + dw_write(priv, DW_SPI_SSIENR, 0); /* clk_div doesn't support odd number */ clk_div = priv->bus_clk_rate / speed; @@ -498,7 +493,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed) dw_write(priv, DW_SPI_BAUDR, clk_div); /* Enable controller after writing control registers */ - spi_enable_chip(priv, 1); + dw_write(priv, DW_SPI_SSIENR, 1); priv->freq = speed; dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div); From ddd3450f399051478263e823f5f778745824bdb3 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:49 -0400 Subject: [PATCH 169/222] spi: dw: Rearrange struct dw_spi_priv This should reduce the size of the struct, and also groups more similar fields together. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 89a8266052..0ebd2cf3cb 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -95,27 +95,26 @@ struct dw_spi_platdata { }; struct dw_spi_priv { - void __iomem *regs; - unsigned int freq; /* Default frequency */ - unsigned int mode; struct clk clk; - unsigned long bus_clk_rate; - + struct reset_ctl_bulk resets; struct gpio_desc cs_gpio; /* External chip-select gpio */ - int bits_per_word; - u8 cs; /* chip select pin */ - u8 tmode; /* TR/TO/RO/EEPROM */ - u8 type; /* SPI/SSP/MicroWire */ - int len; + void __iomem *regs; + unsigned long bus_clk_rate; + unsigned int freq; /* Default frequency */ + unsigned int mode; - u32 fifo_len; /* depth of the FIFO buffer */ - void *tx; - void *tx_end; + const void *tx; + const void *tx_end; void *rx; void *rx_end; + u32 fifo_len; /* depth of the FIFO buffer */ - struct reset_ctl_bulk resets; + int bits_per_word; + int len; + u8 cs; /* chip select pin */ + u8 tmode; /* TR/TO/RO/EEPROM */ + u8 type; /* SPI/SSP/MicroWire */ }; static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset) From 237e5880f8778ef2d26d029f53b57df56a72db4e Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:50 -0400 Subject: [PATCH 170/222] spi: dw: Add SoC-specific compatible strings This adds SoC-specific compatible strings to all users of the designware spi device. This will allow for the correct driver to be selected for each device. Where it is publicly documented, a compatible string for the specific device version has also been added. Devices without publicly-documented device versions include MSCC SoCs, and Arc Socs. All compatible strings except those for SoCFPGAs and some of the versioned strings have been taken from Linux. Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly necessary. However, it is a good cleanup and brings things closer to Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/arc/dts/axs10x_mb.dtsi | 2 +- arch/arc/dts/hsdk-common.dtsi | 2 +- arch/arm/dts/socfpga.dtsi | 6 ++++-- arch/arm/dts/socfpga_agilex.dtsi | 6 ++++-- arch/arm/dts/socfpga_arria10.dtsi | 6 ++++-- arch/arm/dts/socfpga_stratix10.dtsi | 6 ++++-- arch/mips/dts/mscc,jr2.dtsi | 2 +- arch/mips/dts/mscc,ocelot.dtsi | 2 +- arch/riscv/dts/k210.dtsi | 13 ++++++++----- 9 files changed, 28 insertions(+), 17 deletions(-) diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi index daf7ca68fb..d4ff4f7039 100644 --- a/arch/arc/dts/axs10x_mb.dtsi +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -90,7 +90,7 @@ }; spi0: spi@0 { - compatible = "snps,dw-apb-ssi"; + compatible = "snps,axs10x-spi", "snps,dw-apb-ssi"; reg = <0x0 0x100>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi index a4b348b948..3fc82e57d7 100644 --- a/arch/arc/dts/hsdk-common.dtsi +++ b/arch/arc/dts/hsdk-common.dtsi @@ -128,7 +128,7 @@ }; spi0: spi@f0020000 { - compatible = "snps,dw-apb-ssi"; + compatible = "snps,hsdk-spi", "snps,dw-apb-ssi"; reg = <0xf0020000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index eda558f2fe..ff79d335ac 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -804,7 +804,8 @@ }; spi0: spi@fff00000 { - compatible = "snps,dw-apb-ssi"; + compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20", + "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xfff00000 0x1000>; @@ -816,7 +817,8 @@ }; spi1: spi@fff01000 { - compatible = "snps,dw-apb-ssi"; + compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20", + "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xfff01000 0x1000>; diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi index 179b4d5591..c3ead2d72b 100644 --- a/arch/arm/dts/socfpga_agilex.dtsi +++ b/arch/arm/dts/socfpga_agilex.dtsi @@ -366,7 +366,8 @@ }; spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda4000 0x1000>; @@ -379,7 +380,8 @@ }; spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda5000 0x1000>; diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index a598c75542..bab34ab56c 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -604,7 +604,8 @@ }; spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; + compatible = "altr,socfpga-arria10-spi", + "snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda4000 0x100>; @@ -617,7 +618,8 @@ }; spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; + compatible = "altr,socfpga-arria10-spi", + "snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda5000 0x100>; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index cb799bc551..7a7777202c 100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -268,7 +268,8 @@ }; spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; + compatible = "intel,stratix10-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda4000 0x1000>; @@ -281,7 +282,8 @@ }; spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; + compatible = "intel,stratix10-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xffda5000 0x1000>; diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi index 7f5a96fecd..c44e9a2b3a 100644 --- a/arch/mips/dts/mscc,jr2.dtsi +++ b/arch/mips/dts/mscc,jr2.dtsi @@ -94,7 +94,7 @@ spi0: spi-master@101000 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,dw-apb-ssi"; + compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi"; reg = <0x101000 0x40>; num-chipselect = <4>; bus-num = <0>; diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi index 9a187b6e58..aeb4bf8f4b 100644 --- a/arch/mips/dts/mscc,ocelot.dtsi +++ b/arch/mips/dts/mscc,ocelot.dtsi @@ -100,7 +100,7 @@ spi0: spi-master@101000 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,dw-apb-ssi"; + compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi"; reg = <0x101000 0x40>; num-chipselect = <4>; bus-num = <0>; diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 81ef8ca4f7..fce98b0fc3 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -284,7 +284,8 @@ }; spi2: spi@50240000 { - compatible = "kendryte,k120-spislave", + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", "snps,dw-apb-ssi"; spi-slave; reg = <0x50240000 0x100>; @@ -557,7 +558,8 @@ spi0: spi@52000000 { #address-cells = <1>; #size-cells = <0>; - compatible = "kendryte,k210-spi", + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", "snps,dw-apb-ssi"; reg = <0x52000000 0x100>; interrupts = <1>; @@ -573,7 +575,8 @@ spi1: spi@53000000 { #address-cells = <1>; #size-cells = <0>; - compatible = "kendryte,k210-spi", + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", "snps,dw-apb-ssi"; reg = <0x53000000 0x100>; interrupts = <2>; @@ -589,8 +592,8 @@ spi3: spi@54000000 { #address-cells = <1>; #size-cells = <0>; - compatible = "kendryte,k210-spi", - "snps,dw-apb-ssi"; + compatible = "canaan,kendryte-k210-ssi", + "snps,dwc-ssi-1.01a"; reg = <0x54000000 0x200>; interrupts = <4>; clocks = <&sysclk K210_CLK_SPI3>; From 58875790fd50a78bed8df3c75b50285da1729d3c Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:51 -0400 Subject: [PATCH 171/222] spi: dw: Add support for multiple CTRLR0 layouts CTRLR0 can have several different layouts depending on the specific device (dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis. Update the driver to support three specific configurations: dw-apb-ssi with SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi. dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver supported before this change. The register layout before version 3.23a is: | 31 .. 16 | | other stuff | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | DFS | Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data frames of 16 bits or less. In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This parameter defaults to 16 (resulting in the same layout as prior versions), but may also be set to 32. To allow setting longer data frame sizes, a new DFS_32 register was introduced: | 31 .. 21 | 20 .. 16 | | other stuff | DFS_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | all zeros | The old DFS field no longer controls the data frame size. To detect this layout, we try writing 0xF to DFS. If we read back 0x0, then this device has SSI_MAX_XFER_SIZE=32. dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan Kendryte K210 SoCs. The layout of ctrlr0 is: | 31 .. 16 | | other stuff | | 15 .. 12 | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 | | other stuff | TMOD | MODE | FRF | DFS_32 | The semantics of the fields have not changed since the previous version. However, SSI_MAX_XFER_SIZE is effectively always 32. To support these different layouts, we model our approach on the one which the Linux kernel has taken. During probe, the driver calls an init function stored in driver_data. This init function is responsible for determining the layout of CTRLR0, and supplying the update_cr0 function. The style of and information behind this commit is based on the Linux MMIO driver for these devices. Specific reference was made to the series adding support for Intel Keem Bay SoCs [1]. [1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/ Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 176 +++++++++++++++++++++++++++++------ 1 file changed, 145 insertions(+), 31 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 0ebd2cf3cb..9e02fce6c6 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -3,6 +3,7 @@ * Designware master SPI core controller driver * * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> * * Very loosely based on the Linux driver: * drivers/spi/spi-dw.c, which is: @@ -22,6 +23,7 @@ #include <reset.h> #include <dm/device_compat.h> #include <linux/bitops.h> +#include <linux/bitfield.h> #include <linux/compat.h> #include <linux/iopoll.h> #include <asm/io.h> @@ -54,28 +56,48 @@ #define DW_SPI_DR 0x60 /* Bit fields in CTRLR0 */ -#define SPI_DFS_OFFSET 0 +/* + * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only + * option before version 3.23a. + */ +#define CTRLR0_DFS_MASK GENMASK(3, 0) -#define SPI_FRF_OFFSET 4 -#define SPI_FRF_SPI 0x0 -#define SPI_FRF_SSP 0x1 -#define SPI_FRF_MICROWIRE 0x2 -#define SPI_FRF_RESV 0x3 +#define CTRLR0_FRF_MASK GENMASK(5, 4) +#define CTRLR0_FRF_SPI 0x0 +#define CTRLR0_FRF_SSP 0x1 +#define CTRLR0_FRF_MICROWIRE 0x2 +#define CTRLR0_FRF_RESV 0x3 -#define SPI_MODE_OFFSET 6 -#define SPI_SCPH_OFFSET 6 -#define SPI_SCOL_OFFSET 7 +#define CTRLR0_MODE_MASK GENMASK(7, 6) +#define CTRLR0_MODE_SCPH 0x1 +#define CTRLR0_MODE_SCPOL 0x2 -#define SPI_TMOD_OFFSET 8 -#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) -#define SPI_TMOD_TR 0x0 /* xmit & recv */ -#define SPI_TMOD_TO 0x1 /* xmit only */ -#define SPI_TMOD_RO 0x2 /* recv only */ -#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ +#define CTRLR0_TMOD_MASK GENMASK(9, 8) +#define CTRLR0_TMOD_TR 0x0 /* xmit & recv */ +#define CTRLR0_TMOD_TO 0x1 /* xmit only */ +#define CTRLR0_TMOD_RO 0x2 /* recv only */ +#define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */ -#define SPI_SLVOE_OFFSET 10 -#define SPI_SRL_OFFSET 11 -#define SPI_CFS_OFFSET 12 +#define CTRLR0_SLVOE_OFFSET 10 +#define CTRLR0_SRL_OFFSET 11 +#define CTRLR0_CFS_MASK GENMASK(15, 12) + +/* Only present when SSI_MAX_XFER_SIZE=32 */ +#define CTRLR0_DFS_32_MASK GENMASK(20, 16) + +/* The next field is only present on versions after 4.00a */ +#define CTRLR0_SPI_FRF_MASK GENMASK(22, 21) +#define CTRLR0_SPI_FRF_BYTE 0x0 +#define CTRLR0_SPI_FRF_DUAL 0x1 +#define CTRLR0_SPI_FRF_QUAD 0x2 + +/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ +#define DWC_SSI_CTRLR0_DFS_MASK GENMASK(4, 0) +#define DWC_SSI_CTRLR0_FRF_MASK GENMASK(7, 6) +#define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8) +#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10) +#define DWC_SSI_CTRLR0_SRL_OFFSET 13 +#define DWC_SSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22) /* Bit fields in SR, 7 bits */ #define SR_MASK GENMASK(6, 0) /* cover 7 bits */ @@ -99,6 +121,8 @@ struct dw_spi_priv { struct reset_ctl_bulk resets; struct gpio_desc cs_gpio; /* External chip-select gpio */ + u32 (*update_cr0)(struct dw_spi_priv *priv); + void __iomem *regs; unsigned long bus_clk_rate; unsigned int freq; /* Default frequency */ @@ -109,6 +133,7 @@ struct dw_spi_priv { void *rx; void *rx_end; u32 fifo_len; /* depth of the FIFO buffer */ + u32 max_xfer; /* Maximum transfer size (in bits) */ int bits_per_word; int len; @@ -127,6 +152,53 @@ static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val) __raw_writel(val, priv->regs + offset); } +static u32 dw_spi_dw16_update_cr0(struct dw_spi_priv *priv) +{ + return FIELD_PREP(CTRLR0_DFS_MASK, priv->bits_per_word - 1) + | FIELD_PREP(CTRLR0_FRF_MASK, priv->type) + | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode) + | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode); +} + +static u32 dw_spi_dw32_update_cr0(struct dw_spi_priv *priv) +{ + return FIELD_PREP(CTRLR0_DFS_32_MASK, priv->bits_per_word - 1) + | FIELD_PREP(CTRLR0_FRF_MASK, priv->type) + | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode) + | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode); +} + +static u32 dw_spi_dwc_update_cr0(struct dw_spi_priv *priv) +{ + return FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK, priv->bits_per_word - 1) + | FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type) + | FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode) + | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode); +} + +static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv) +{ + /* If we read zeros from DFS, then we need to use DFS_32 instead */ + dw_write(priv, DW_SPI_SSIENR, 0); + dw_write(priv, DW_SPI_CTRLR0, 0xffffffff); + if (FIELD_GET(CTRLR0_DFS_MASK, dw_read(priv, DW_SPI_CTRLR0))) { + priv->max_xfer = 16; + priv->update_cr0 = dw_spi_dw16_update_cr0; + } else { + priv->max_xfer = 32; + priv->update_cr0 = dw_spi_dw32_update_cr0; + } + + return 0; +} + +static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv) +{ + priv->max_xfer = 32; + priv->update_cr0 = dw_spi_dwc_update_cr0; + return 0; +} + static int request_gpio_cs(struct udevice *bus) { #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD) @@ -165,6 +237,10 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus) /* Use 500KHz as a suitable default */ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000); + + if (dev_read_bool(bus, "spi-slave")) + return -EINVAL; + dev_info(bus, "max-frequency=%d\n", plat->frequency); return request_gpio_cs(bus); @@ -259,11 +335,15 @@ static int dw_spi_reset(struct udevice *bus) return 0; } +typedef int (*dw_spi_init_t)(struct udevice *bus, struct dw_spi_priv *priv); + static int dw_spi_probe(struct udevice *bus) { + dw_spi_init_t init = (dw_spi_init_t)dev_get_driver_data(bus); struct dw_spi_platdata *plat = dev_get_platdata(bus); struct dw_spi_priv *priv = dev_get_priv(bus); int ret; + u32 version; priv->regs = plat->regs; priv->freq = plat->frequency; @@ -276,6 +356,17 @@ static int dw_spi_probe(struct udevice *bus) if (ret) return ret; + if (!init) + return -EINVAL; + ret = init(bus, priv); + if (ret) + return ret; + + version = dw_read(priv, DW_SPI_VERSION); + dev_dbg(bus, "ssi_version_id=%c.%c%c%c ssi_max_xfer_size=%u\n", + version >> 24, version >> 16, version >> 8, version, + priv->max_xfer); + /* Currently only bits_per_word == 8 supported */ priv->bits_per_word = 8; @@ -320,7 +411,7 @@ static inline u32 rx_max(struct dw_spi_priv *priv) static void dw_writer(struct dw_spi_priv *priv) { u32 max = tx_max(priv); - u16 txw = 0xFFFF; + u32 txw = 0xFFFFFFFF; while (max--) { /* Set the tx word if the transfer's original "tx" is not null */ @@ -406,23 +497,18 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) external_cs_manage(dev, false); - cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) | - (priv->mode << SPI_MODE_OFFSET) | - (priv->tmode << SPI_TMOD_OFFSET); - if (rx && tx) - priv->tmode = SPI_TMOD_TR; + priv->tmode = CTRLR0_TMOD_TR; else if (rx) - priv->tmode = SPI_TMOD_RO; + priv->tmode = CTRLR0_TMOD_RO; else /* - * In transmit only mode (SPI_TMOD_TO) input FIFO never gets + * In transmit only mode (CTRL0_TMOD_TO) input FIFO never gets * any data which breaks our logic in poll_transfer() above. */ - priv->tmode = SPI_TMOD_TR; + priv->tmode = CTRLR0_TMOD_TR; - cr0 &= ~SPI_TMOD_MASK; - cr0 |= (priv->tmode << SPI_TMOD_OFFSET); + cr0 = priv->update_cr0(priv); priv->len = bitlen >> 3; @@ -476,7 +562,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, static int dw_spi_set_speed(struct udevice *bus, uint speed) { - struct dw_spi_platdata *plat = bus->platdata; + struct dw_spi_platdata *plat = dev_get_platdata(bus); struct dw_spi_priv *priv = dev_get_priv(bus); u16 clk_div; @@ -547,7 +633,35 @@ static const struct dm_spi_ops dw_spi_ops = { }; static const struct udevice_id dw_spi_ids[] = { - { .compatible = "snps,dw-apb-ssi" }, + /* Generic compatible strings */ + + { .compatible = "snps,dw-apb-ssi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "snps,dw-apb-ssi-3.20a", .data = (ulong)dw_spi_apb_init }, + { .compatible = "snps,dw-apb-ssi-3.22a", .data = (ulong)dw_spi_apb_init }, + /* First version with SSI_MAX_XFER_SIZE */ + { .compatible = "snps,dw-apb-ssi-3.23a", .data = (ulong)dw_spi_apb_init }, + /* First version with Dual/Quad SPI; unused by this driver */ + { .compatible = "snps,dw-apb-ssi-4.00a", .data = (ulong)dw_spi_apb_init }, + { .compatible = "snps,dw-apb-ssi-4.01", .data = (ulong)dw_spi_apb_init }, + { .compatible = "snps,dwc-ssi-1.01a", .data = (ulong)dw_spi_dwc_init }, + + /* Compatible strings for specific SoCs */ + + /* + * Both the Cyclone V and Arria V share a device tree and have the same + * version of this device. This compatible string is used for those + * devices, and is not used for sofpgas in general. + */ + { .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "canaan,kendryte-k210-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "canaan,kendryte-k210-ssi", .data = (ulong)dw_spi_dwc_init }, + { .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "mscc,ocelot-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "mscc,jaguar2-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "snps,axs10x-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "snps,hsdk-spi", .data = (ulong)dw_spi_apb_init }, { } }; From 0d98f6de62dc02cbdbf0a40bdb02e465256e2150 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:52 -0400 Subject: [PATCH 172/222] spi: dw: Document devicetree binding This documentation has been taken from Linux commit 3d7db0f11c7a ("spi: dw: Refactor mid_spi_dma_setup() to separate DMA and IRQ config"), immediately before the file was deleted and replaced with a yaml version. Additional compatible strings from newer versions have been added, as well as a few U-Boot-specific ones. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- .../spi/snps,dw-apb-ssi.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt diff --git a/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt new file mode 100644 index 0000000000..8d2888fbe3 --- /dev/null +++ b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt @@ -0,0 +1,56 @@ +Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface +and Synopsys DesignWare High Performance Synchronous Serial Interface + +Required properties: +- compatible : One of + "altr,socfpga-spi", + "altr,socfpga-arria10-spi", + "canaan,kendryte-k210-spi", + "canaan,kendryte-k210-ssi", + "intel,stratix10-spi", + "intel,agilex-spi", + "mscc,ocelot-spi", + or "mscc,jaguar2-spi"; + and one of + "snps,dw-apb-ssi-3.20a", + "snps,dw-apb-ssi-3.22a", + "snps,dw-apb-ssi-3.23", + "snps,dw-apb-ssi-4.00a", + "snps,dw-apb-ssi-4.01", + or "snps,dwc-ssi-1.01a". + "snps,dw-apb-ssi" may also be used, but is deprecated in favor of specific + version strings. +- reg : The register base for the controller. For "mscc,<soc>-spi", a second + register set is required (named ICPU_CFG:SPI_MST) +- #address-cells : <1>, as required by generic SPI binding. +- #size-cells : <0>, also as required by generic SPI binding. +- clocks : phandles for the clocks, see the description of clock-names below. + The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock + is optional. If a single clock is specified but no clock-name, it is the + "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first. + +Optional properties: +- clock-names : Contains the names of the clocks: + "ssi_clk", for the core clock used to generate the external SPI clock. + "pclk", the interface clock, required for register access. +- cs-gpios : Specifies the gpio pins to be used for chipselects. +- num-cs : The number of chipselects. If omitted, this will default to 4. +- reg-io-width : The I/O register width (in bytes) implemented by this + device. Supported values are 2 or 4 (the default). + +Child nodes as per the generic SPI binding. + +Example: + + spi@fff00000 { + compatible = "altr,socfpga-arria10-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + reg = <0xfff00000 0x1000>; + interrupts = <0 154 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&spi_m_clk>; + num-cs = <2>; + cs-gpios = <&gpio0 13 0>, + <&gpio0 14 0>; + }; From fec7bf0460dbf5a6744e1f98298a9b664f856a34 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:53 -0400 Subject: [PATCH 173/222] spi: dw: Add mem_ops The designware ssi device has "broken" chip select behaviour [1], and needs specific manipulation to use the built-in chip select. The existing fix is to use an external GPIO for chip select, but typically the K210 has SPI3 directly connected to a flash chip with dedicated pins. This makes it impossible to use the spi_xfer function to use spi, since the CS is de-asserted in between calls. This patch adds an implementation of exec_op, which gives correct behaviour when reading/writing spi flash. This patch also rearranges the headers to conform to U-Boot style. [1] https://lkml.org/lkml/2015/12/23/132 Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/designware_spi.c | 122 ++++++++++++++++++++++++++++++++--- 1 file changed, 113 insertions(+), 9 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 9e02fce6c6..ce74ac0abc 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -12,21 +12,23 @@ #define LOG_CATEGORY UCLASS_SPI #include <common.h> -#include <log.h> -#include <asm-generic/gpio.h> #include <clk.h> #include <dm.h> -#include <errno.h> -#include <malloc.h> -#include <spi.h> -#include <fdtdec.h> -#include <reset.h> #include <dm/device_compat.h> -#include <linux/bitops.h> +#include <errno.h> +#include <fdtdec.h> +#include <log.h> +#include <malloc.h> +#include <reset.h> +#include <spi.h> +#include <spi-mem.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> #include <linux/bitfield.h> +#include <linux/bitops.h> #include <linux/compat.h> #include <linux/iopoll.h> -#include <asm/io.h> +#include <linux/sizes.h> /* Register offsets */ #define DW_SPI_CTRLR0 0x00 @@ -560,6 +562,107 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, return ret; } +/* + * This function is necessary for reading SPI flash with the native CS + * c.f. https://lkml.org/lkml/2015/12/23/132 + */ +static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + bool read = op->data.dir == SPI_MEM_DATA_IN; + int pos, i, ret = 0; + struct udevice *bus = slave->dev->parent; + struct dw_spi_priv *priv = dev_get_priv(bus); + u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + u8 op_buf[op_len]; + u32 cr0; + + if (read) + priv->tmode = CTRLR0_TMOD_EPROMREAD; + else + priv->tmode = CTRLR0_TMOD_TO; + + cr0 = priv->update_cr0(priv); + dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in, + op->data.nbytes); + + dw_write(priv, DW_SPI_SSIENR, 0); + dw_write(priv, DW_SPI_CTRLR0, cr0); + if (read) + dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1); + dw_write(priv, DW_SPI_SSIENR, 1); + + /* From spi_mem_exec_op */ + pos = 0; + op_buf[pos++] = op->cmd.opcode; + if (op->addr.nbytes) { + for (i = 0; i < op->addr.nbytes; i++) + op_buf[pos + i] = op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); + + pos += op->addr.nbytes; + } + if (op->dummy.nbytes) + memset(op_buf + pos, 0xff, op->dummy.nbytes); + + external_cs_manage(slave->dev, false); + + priv->tx = &op_buf; + priv->tx_end = priv->tx + op_len; + priv->rx = NULL; + priv->rx_end = NULL; + while (priv->tx != priv->tx_end) + dw_writer(priv); + + /* + * XXX: The following are tight loops! Enabling debug messages may cause + * them to fail because we are not reading/writing the fifo fast enough. + */ + if (read) { + priv->rx = op->data.buf.in; + priv->rx_end = priv->rx + op->data.nbytes; + + dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev)); + while (priv->rx != priv->rx_end) + dw_reader(priv); + } else { + u32 val; + + priv->tx = op->data.buf.out; + priv->tx_end = priv->tx + op->data.nbytes; + + /* Fill up the write fifo before starting the transfer */ + dw_writer(priv); + dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev)); + while (priv->tx != priv->tx_end) + dw_writer(priv); + + if (readl_poll_timeout(priv->regs + DW_SPI_SR, val, + (val & SR_TF_EMPT) && !(val & SR_BUSY), + RX_TIMEOUT * 1000)) { + ret = -ETIMEDOUT; + } + } + + dw_write(priv, DW_SPI_SER, 0); + external_cs_manage(slave->dev, true); + + dev_dbg(bus, "%u bytes xfered\n", op->data.nbytes); + return ret; +} + +/* The size of ctrl1 limits data transfers to 64K */ +static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) +{ + op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K); + + return 0; +} + +static const struct spi_controller_mem_ops dw_spi_mem_ops = { + .exec_op = dw_spi_exec_op, + .adjust_op_size = dw_spi_adjust_op_size, +}; + static int dw_spi_set_speed(struct udevice *bus, uint speed) { struct dw_spi_platdata *plat = dev_get_platdata(bus); @@ -624,6 +727,7 @@ static int dw_spi_remove(struct udevice *bus) static const struct dm_spi_ops dw_spi_ops = { .xfer = dw_spi_xfer, + .mem_ops = &dw_spi_mem_ops, .set_speed = dw_spi_set_speed, .set_mode = dw_spi_set_mode, /* From b55af5a2252be84a48c94a2d392c1da71c89be78 Mon Sep 17 00:00:00 2001 From: Sean Anderson <seanga2@gmail.com> Date: Fri, 16 Oct 2020 18:57:54 -0400 Subject: [PATCH 174/222] riscv: Add device tree bindings for SPI This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix Bit. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Rick Chen <rick@andestech.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/riscv/dts/k210-maix-bit.dts | 46 +++++++++++++++++++++++++++++++- arch/riscv/dts/k210.dtsi | 2 ++ 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts index c2beec602c..e4dea205b2 100644 --- a/arch/riscv/dts/k210-maix-bit.dts +++ b/arch/riscv/dts/k210-maix-bit.dts @@ -152,7 +152,7 @@ pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>, <K210_FPIOA(27, K210_PCF_SPI1_SCLK)>, <K210_FPIOA(28, K210_PCF_SPI1_D0)>, - <K210_FPIOA(29, K210_PCF_GPIOHS13)>; + <K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */ }; }; @@ -160,3 +160,47 @@ pinctrl-0 = <&fpioa_dvp>; pinctrl-names = "default"; }; + +&spi0 { + pinctrl-0 = <&fpioa_spi0>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 0>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&fpioa_spi1>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 0>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <25000000>; + voltage-ranges = <3300 3300>; + broken-cd; + }; +}; + +&spi3 { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index fce98b0fc3..81b04018c6 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -496,6 +496,8 @@ interrupts = <24>; clocks = <&sysclk K210_CLK_DVP>; resets = <&sysrst K210_RST_DVP>; + kendryte,sysctl = <&sysctl>; + kendryte,misc-offset = <K210_SYSCTL_MISC>; status = "disabled"; }; From 24f279423295a93c36a7b28945e53c8ccadb0922 Mon Sep 17 00:00:00 2001 From: Pengpeng Chen <pengpeng.chen@cortina-access.com> Date: Thu, 30 Jul 2020 12:52:45 -0700 Subject: [PATCH 175/222] spi: ca_sflash: Add CAxxxx SPI Flash Controller Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- MAINTAINERS | 2 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ca_sflash.c | 576 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 587 insertions(+) create mode 100644 drivers/spi/ca_sflash.c diff --git a/MAINTAINERS b/MAINTAINERS index 127e30c0a5..da2a05b303 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -195,6 +195,7 @@ F: drivers/watchdog/cortina_wdt.c F: drivers/serial/serial_cortina.c F: drivers/led/led_cortina.c F: drivers/mmc/ca_dw_mmc.c +F: drivers/spi/ca_sflash.c F: drivers/i2c/i2c-cortina.c F: drivers/i2c/i2c-cortina.h @@ -800,6 +801,7 @@ F: drivers/watchdog/cortina_wdt.c F: drivers/serial/serial_cortina.c F: drivers/led/led_cortina.c F: drivers/mmc/ca_dw_mmc.c +F: drivers/spi/ca_sflash.c F: drivers/i2c/i2c-cortina.c F: drivers/i2c/i2c-cortina.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f7a9852565..cd19b2d4b3 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -106,6 +106,14 @@ config BCMSTB_SPI be used to access the SPI flash on platforms embedding this Broadcom SPI core. +config CORTINA_SFLASH + bool "Cortina-Access Serial Flash controller driver" + depends on DM_SPI && SPI_MEM + help + Enable the Cortina-Access Serial Flash controller driver. This driver + can be used to access the SPI NOR/NAND flash on platforms embedding this + Cortina-Access IP core. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d9b5bd9b79..dc9ea34c0a 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o +obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c new file mode 100644 index 0000000000..00af6bffa6 --- /dev/null +++ b/drivers/spi/ca_sflash.c @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Cortina SPI-FLASH Controller + * + * Copyright (C) 2020 Cortina Access Inc. All Rights Reserved. + * + * Author: PengPeng Chen <pengpeng.chen@cortina-access.com> + */ + +#include <common.h> +#include <malloc.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/ioport.h> +#include <linux/sizes.h> +#include <spi.h> +#include <spi-mem.h> +#include <reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct ca_sflash_regs { + u32 idr; /* 0x00:Flash word ID Register */ + u32 tc; /* 0x04:Flash Timeout Counter Register */ + u32 sr; /* 0x08:Flash Status Register */ + u32 tr; /* 0x0C:Flash Type Register */ + u32 asr; /* 0x10:Flash ACCESS START/BUSY Register */ + u32 isr; /* 0x14:Flash Interrupt Status Register */ + u32 imr; /* 0x18:Flash Interrupt Mask Register */ + u32 fcr; /* 0x1C:NAND Flash FIFO Control Register */ + u32 ffsr; /* 0x20:Flash FIFO Status Register */ + u32 ffar; /* 0x24:Flash FIFO ADDRESS Register */ + u32 ffmar; /* 0x28:Flash FIFO MATCHING ADDRESS Register */ + u32 ffdr; /* 0x2C:Flash FIFO Data Register */ + u32 ar; /* 0x30:Serial Flash Access Register */ + u32 ear; /* 0x34:Serial Flash Extend Access Register */ + u32 adr; /* 0x38:Serial Flash ADdress Register */ + u32 dr; /* 0x3C:Serial Flash Data Register */ + u32 tmr; /* 0x40:Serial Flash Timing Register */ +}; + +/* + * FLASH_TYPE + */ +#define CA_FLASH_TR_PIN BIT(15) +#define CA_FLASH_TR_TYPE_MSK GENMASK(14, 12) +#define CA_FLASH_TR_TYPE(tp) (((tp) << 12) & CA_FLASH_TR_TYPE_MSK) +#define CA_FLASH_TR_WIDTH BIT(11) +#define CA_FLASH_TR_SIZE_MSK GENMASK(10, 9) +#define CA_FLASH_TR_SIZE(sz) (((sz) << 9) & CA_FLASH_TR_SIZE_MSK) + +/* + * FLASH_FLASH_ACCESS_START + */ +#define CA_FLASH_ASR_IND_START_EN BIT(1) +#define CA_FLASH_ASR_DMA_START_EN BIT(3) +#define CA_FLASH_ASR_WR_ACCESS_EN BIT(9) + +/* + * FLASH_FLASH_INTERRUPT + */ +#define CA_FLASH_ISR_REG_IRQ BIT(1) +#define CA_FLASH_ISR_FIFO_IRQ BIT(2) + +/* + * FLASH_SF_ACCESS + */ +#define CA_SF_AR_OP_MSK GENMASK(7, 0) +#define CA_SF_AR_OP(op) ((op) << 0 & CA_SF_AR_OP_MSK) +#define CA_SF_AR_ACCODE_MSK GENMASK(11, 8) +#define CA_SF_AR_ACCODE(ac) (((ac) << 8) & CA_SF_AR_ACCODE_MSK) +#define CA_SF_AR_FORCE_TERM BIT(12) +#define CA_SF_AR_FORCE_BURST BIT(13) +#define CA_SF_AR_AUTO_MODE_EN BIT(15) +#define CA_SF_AR_CHIP_EN_ALT BIT(16) +#define CA_SF_AR_HI_SPEED_RD BIT(17) +#define CA_SF_AR_MIO_INF_DC BIT(24) +#define CA_SF_AR_MIO_INF_AC BIT(25) +#define CA_SF_AR_MIO_INF_CC BIT(26) +#define CA_SF_AR_DDR_MSK GENMASK(29, 28) +#define CA_SF_AR_DDR(ddr) (((ddr) << 28) & CA_SF_AR_DDR_MSK) +#define CA_SF_AR_MIO_INF_MSK GENMASK(31, 30) +#define CA_SF_AR_MIO_INF(io) (((io) << 30) & CA_SF_AR_MIO_INF_MSK) + +/* + * FLASH_SF_EXT_ACCESS + */ +#define CA_SF_EAR_OP_MSK GENMASK(7, 0) +#define CA_SF_EAR_OP(op) (((op) << 0) & CA_SF_EAR_OP_MSK) +#define CA_SF_EAR_DATA_CNT_MSK GENMASK(20, 8) +#define CA_SF_EAR_DATA_CNT(cnt) (((cnt) << 8) & CA_SF_EAR_DATA_CNT_MSK) +#define CA_SF_EAR_DATA_CNT_MAX (4096) +#define CA_SF_EAR_ADDR_CNT_MSK GENMASK(23, 21) +#define CA_SF_EAR_ADDR_CNT(cnt) (((cnt) << 21) & CA_SF_EAR_ADDR_CNT_MSK) +#define CA_SF_EAR_ADDR_CNT_MAX (5) +#define CA_SF_EAR_DUMY_CNT_MSK GENMASK(29, 24) +#define CA_SF_EAR_DUMY_CNT(cnt) (((cnt) << 24) & CA_SF_EAR_DUMY_CNT_MSK) +#define CA_SF_EAR_DUMY_CNT_MAX (32) +#define CA_SF_EAR_DRD_CMD_EN BIT(31) + +/* + * FLASH_SF_ADDRESS + */ +#define CA_SF_ADR_REG_MSK GENMASK(31, 0) +#define CA_SF_ADR_REG(addr) (((addr) << 0) & CA_SF_ADR_REG_MSK) + +/* + * FLASH_SF_DATA + */ +#define CA_SF_DR_REG_MSK GENMASK(31, 0) +#define CA_SF_DR_REG(addr) (((addr) << 0) & CA_SF_DR_REG_MSK) + +/* + * FLASH_SF_TIMING + */ +#define CA_SF_TMR_IDLE_MSK GENMASK(7, 0) +#define CA_SF_TMR_IDLE(idle) (((idle) << 0) & CA_SF_TMR_IDLE_MSK) +#define CA_SF_TMR_HOLD_MSK GENMASK(15, 8) +#define CA_SF_TMR_HOLD(hold) (((hold) << 8) & CA_SF_TMR_HOLD_MSK) +#define CA_SF_TMR_SETUP_MSK GENMASK(23, 16) +#define CA_SF_TMR_SETUP(setup) (((setup) << 16) & CA_SF_TMR_SETUP_MSK) +#define CA_SF_TMR_CLK_MSK GENMASK(26, 24) +#define CA_SF_TMR_CLK(clk) (((clk) << 24) & CA_SF_TMR_CLK_MSK) + +#define CA_SFLASH_IND_WRITE 0 +#define CA_SFLASH_IND_READ 1 +#define CA_SFLASH_MEM_MAP 3 +#define CA_SFLASH_FIFO_TIMEOUT_US 30000 +#define CA_SFLASH_BUSY_TIMEOUT_US 40000 + +#define CA_SF_AC_OP 0x00 +#define CA_SF_AC_OP_1_DATA 0x01 +#define CA_SF_AC_OP_2_DATA 0x02 +#define CA_SF_AC_OP_3_DATA 0x03 +#define CA_SF_AC_OP_4_DATA 0x04 +#define CA_SF_AC_OP_3_ADDR 0x05 +#define CA_SF_AC_OP_4_ADDR (CA_SF_AC_OP_3_ADDR) +#define CA_SF_AC_OP_3_ADDR_1_DATA 0x06 +#define CA_SF_AC_OP_4_ADDR_1_DATA (CA_SF_AC_OP_3_ADDR_1_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_2_DATA 0x07 +#define CA_SF_AC_OP_4_ADDR_2_DATA (CA_SF_AC_OP_3_ADDR_2_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_3_DATA 0x08 +#define CA_SF_AC_OP_4_ADDR_3_DATA (CA_SF_AC_OP_3_ADDR_3_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_4_DATA 0x09 +#define CA_SF_AC_OP_4_ADDR_4_DATA (CA_SF_AC_OP_3_ADDR_4_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_X_1_DATA 0x0A +#define CA_SF_AC_OP_4_ADDR_X_1_DATA (CA_SF_AC_OP_3_ADDR_X_1_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_X_2_DATA 0x0B +#define CA_SF_AC_OP_4_ADDR_X_2_DATA (CA_SF_AC_OP_3_ADDR_X_2_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_X_3_DATA 0x0C +#define CA_SF_AC_OP_4_ADDR_X_3_DATA (CA_SF_AC_OP_3_ADDR_X_3_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_X_4_DATA 0x0D +#define CA_SF_AC_OP_4_ADDR_X_4_DATA (CA_SF_AC_OP_3_ADDR_X_4_DATA << 2) +#define CA_SF_AC_OP_3_ADDR_4X_1_DATA 0x0E +#define CA_SF_AC_OP_4_ADDR_4X_1_DATA (CA_SF_AC_OP_3_ADDR_4X_1_DATA << 2) +#define CA_SF_AC_OP_EXTEND 0x0F + +#define CA_SF_ACCESS_MIO_SINGLE 0 +#define CA_SF_ACCESS_MIO_DUAL 1 +#define CA_SF_ACCESS_MIO_QUARD 2 + +enum access_type { + RD_ACCESS, + WR_ACCESS, +}; + +struct ca_sflash_priv { + struct ca_sflash_regs *regs; + u8 rx_width; + u8 tx_width; +}; + +/* + * This function doesn't do anything except help with debugging + */ +static int ca_sflash_claim_bus(struct udevice *dev) +{ + debug("%s:\n", __func__); + return 0; +} + +static int ca_sflash_release_bus(struct udevice *dev) +{ + debug("%s:\n", __func__); + return 0; +} + +static int ca_sflash_set_speed(struct udevice *dev, uint speed) +{ + debug("%s:\n", __func__); + return 0; +} + +static int ca_sflash_set_mode(struct udevice *dev, uint mode) +{ + struct ca_sflash_priv *priv = dev_get_priv(dev); + + if (mode & SPI_RX_QUAD) + priv->rx_width = 4; + else if (mode & SPI_RX_DUAL) + priv->rx_width = 2; + else + priv->rx_width = 1; + + if (mode & SPI_TX_QUAD) + priv->tx_width = 4; + else if (mode & SPI_TX_DUAL) + priv->tx_width = 2; + else + priv->tx_width = 1; + + debug("%s: mode=%d, rx_width=%d, tx_width=%d\n", + __func__, mode, priv->rx_width, priv->tx_width); + + return 0; +} + +static int _ca_sflash_wait_for_not_busy(struct ca_sflash_priv *priv) +{ + u32 asr; + + if (readl_poll_timeout(&priv->regs->asr, asr, + !(asr & CA_FLASH_ASR_IND_START_EN), + CA_SFLASH_BUSY_TIMEOUT_US)) { + pr_err("busy timeout (stat:%#x)\n", asr); + return -1; + } + + return 0; +} + +static int _ca_sflash_wait_cmd(struct ca_sflash_priv *priv, + enum access_type type) +{ + if (type == WR_ACCESS) { + /* Enable write access and start the sflash indirect access */ + clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0), + CA_FLASH_ASR_WR_ACCESS_EN + | CA_FLASH_ASR_IND_START_EN); + } else if (type == RD_ACCESS) { + /* Start the sflash indirect access */ + clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0), + CA_FLASH_ASR_IND_START_EN); + } else { + printf("%s: !error access type.\n", __func__); + return -1; + } + + /* Wait til the action(rd/wr) completed */ + return _ca_sflash_wait_for_not_busy(priv); +} + +static int _ca_sflash_read(struct ca_sflash_priv *priv, + u8 *buf, unsigned int data_len) +{ + u32 reg_data; + int len; + + len = data_len; + while (len >= 4) { + if (_ca_sflash_wait_cmd(priv, RD_ACCESS)) + return -1; + reg_data = readl(&priv->regs->dr); + *buf++ = reg_data & 0xFF; + *buf++ = (reg_data >> 8) & 0xFF; + *buf++ = (reg_data >> 16) & 0xFF; + *buf++ = (reg_data >> 24) & 0xFF; + len -= 4; + debug("%s: reg_data=%#08x\n", + __func__, reg_data); + } + + if (len > 0) { + if (_ca_sflash_wait_cmd(priv, RD_ACCESS)) + return -1; + reg_data = readl(&priv->regs->dr); + debug("%s: reg_data=%#08x\n", + __func__, reg_data); + } + + switch (len) { + case 3: + *buf++ = reg_data & 0xFF; + *buf++ = (reg_data >> 8) & 0xFF; + *buf++ = (reg_data >> 16) & 0xFF; + break; + case 2: + *buf++ = reg_data & 0xFF; + *buf++ = (reg_data >> 8) & 0xFF; + break; + case 1: + *buf++ = reg_data & 0xFF; + break; + case 0: + break; + default: + printf("%s: error data_length %d!\n", __func__, len); + } + + return 0; +} + +static int _ca_sflash_mio_set(struct ca_sflash_priv *priv, + u8 width) +{ + if (width == 4) { + setbits_le32(&priv->regs->ar, + CA_SF_AR_MIO_INF_DC + | CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_QUARD) + | CA_SF_AR_FORCE_BURST); + } else if (width == 2) { + setbits_le32(&priv->regs->ar, + CA_SF_AR_MIO_INF_DC + | CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_DUAL) + | CA_SF_AR_FORCE_BURST); + } else if (width == 1) { + setbits_le32(&priv->regs->ar, + CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_SINGLE) + | CA_SF_AR_FORCE_BURST); + } else { + printf("%s: error rx/tx width %d!\n", __func__, width); + return -1; + } + + return 0; +} + +static int _ca_sflash_write(struct ca_sflash_priv *priv, + u8 *buf, unsigned int data_len) +{ + u32 reg_data; + int len; + + len = data_len; + while (len > 0) { + reg_data = buf[0] + | (buf[1] << 8) + | (buf[2] << 16) + | (buf[3] << 24); + + debug("%s: reg_data=%#08x\n", + __func__, reg_data); + /* Fill data */ + clrsetbits_le32(&priv->regs->dr, GENMASK(31, 0), reg_data); + + if (_ca_sflash_wait_cmd(priv, WR_ACCESS)) + return -1; + + len -= 4; + buf += 4; + } + + return 0; +} + +static int _ca_sflash_access_data(struct ca_sflash_priv *priv, + struct spi_mem_op *op) +{ + int total_cnt; + unsigned int len; + unsigned int data_cnt = op->data.nbytes; + u64 addr_offset = op->addr.val; + u8 addr_cnt = op->addr.nbytes; + u8 *data_buf = NULL; + u8 *buf = NULL; + + if (op->data.dir == SPI_MEM_DATA_IN) + data_buf = (u8 *)op->data.buf.in; + else + data_buf = (u8 *)op->data.buf.out; + + if (data_cnt > CA_SF_EAR_DATA_CNT_MAX) + buf = malloc(CA_SF_EAR_DATA_CNT_MAX); + else + buf = malloc(data_cnt); + + total_cnt = data_cnt; + while (total_cnt > 0) { + /* Fill address */ + if (addr_cnt > 0) + clrsetbits_le32(&priv->regs->adr, + GENMASK(31, 0), (u32)addr_offset); + + if (total_cnt > CA_SF_EAR_DATA_CNT_MAX) { + len = CA_SF_EAR_DATA_CNT_MAX; + addr_offset += CA_SF_EAR_DATA_CNT_MAX; + /* Clear start bit before next bulk read */ + clrbits_le32(&priv->regs->asr, GENMASK(31, 0)); + } else { + len = total_cnt; + } + + memset(buf, 0, len); + if (op->data.dir == SPI_MEM_DATA_IN) { + if (_ca_sflash_read(priv, buf, len)) + break; + memcpy(data_buf, buf, len); + } else { + memcpy(buf, data_buf, len); + if (_ca_sflash_write(priv, buf, len)) + break; + } + + total_cnt -= len; + data_buf += len; + } + if (buf) + free(buf); + + return total_cnt > 0 ? -1 : 0; +} + +static int _ca_sflash_issue_cmd(struct ca_sflash_priv *priv, + struct spi_mem_op *op, u8 opcode) +{ + u8 dummy_cnt = op->dummy.nbytes; + u8 addr_cnt = op->addr.nbytes; + u8 mio_width; + unsigned int data_cnt = op->data.nbytes; + u64 addr_offset = op->addr.val; + + /* Set the access register */ + clrsetbits_le32(&priv->regs->ar, + GENMASK(31, 0), CA_SF_AR_ACCODE(opcode)); + + if (opcode == CA_SF_AC_OP_EXTEND) { /* read_data, write_data */ + if (data_cnt > 6) { + if (op->data.dir == SPI_MEM_DATA_IN) + mio_width = priv->rx_width; + else + mio_width = priv->tx_width; + if (_ca_sflash_mio_set(priv, mio_width)) + return -1; + } + debug("%s: FLASH ACCESS reg=%#08x\n", + __func__, readl(&priv->regs->ar)); + + /* Use command in extend_access register */ + clrsetbits_le32(&priv->regs->ear, + GENMASK(31, 0), CA_SF_EAR_OP(op->cmd.opcode) + | CA_SF_EAR_DUMY_CNT(dummy_cnt * 8 - 1) + | CA_SF_EAR_ADDR_CNT(addr_cnt - 1) + | CA_SF_EAR_DATA_CNT(4 - 1) + | CA_SF_EAR_DRD_CMD_EN); + debug("%s: FLASH EXT ACCESS reg=%#08x\n", + __func__, readl(&priv->regs->ear)); + + if (_ca_sflash_access_data(priv, op)) + return -1; + } else { /* reset_op, wr_enable, wr_disable */ + setbits_le32(&priv->regs->ar, + CA_SF_AR_OP(op->cmd.opcode)); + debug("%s: FLASH ACCESS reg=%#08x\n", + __func__, readl(&priv->regs->ar)); + + if (opcode == CA_SF_AC_OP_4_ADDR) { /* erase_op */ + /* Configure address length */ + if (addr_cnt > 3) /* 4 Bytes address */ + setbits_le32(&priv->regs->tr, + CA_FLASH_TR_SIZE(2)); + else /* 3 Bytes address */ + clrbits_le32(&priv->regs->tr, + CA_FLASH_TR_SIZE_MSK); + + /* Fill address */ + if (addr_cnt > 0) + clrsetbits_le32(&priv->regs->adr, + GENMASK(31, 0), + (u32)addr_offset); + } + + if (_ca_sflash_wait_cmd(priv, RD_ACCESS)) + return -1; + } + /* elapse 10us before issuing any other command */ + udelay(10); + + return 0; +} + +static int ca_sflash_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct ca_sflash_priv *priv = dev_get_priv(slave->dev->parent); + u8 opcode; + + debug("%s: cmd:%#02x addr.val:%#llx addr.len:%#x data.len:%#x data.dir:%#x\n", + __func__, op->cmd.opcode, op->addr.val, + op->addr.nbytes, op->data.nbytes, op->data.dir); + + if (op->data.nbytes == 0 && op->addr.nbytes == 0) { + opcode = CA_SF_AC_OP; + } else if (op->data.nbytes == 0 && op->addr.nbytes > 0) { + opcode = CA_SF_AC_OP_4_ADDR; + } else if (op->data.nbytes > 0) { + opcode = CA_SF_AC_OP_EXTEND; + } else { + printf("%s: can't support cmd.opcode:(%#02x) type currently!\n", + __func__, op->cmd.opcode); + return -1; + } + + return _ca_sflash_issue_cmd(priv, (struct spi_mem_op *)op, opcode); +} + +static void ca_sflash_init(struct ca_sflash_priv *priv) +{ + /* Set FLASH_TYPE as serial flash, value: 0x0400*/ + clrsetbits_le32(&priv->regs->tr, + GENMASK(31, 0), CA_FLASH_TR_SIZE(2)); + debug("%s: FLASH_TYPE reg=%#x\n", + __func__, readl(&priv->regs->tr)); + + /* Minimize flash timing, value: 0x07010101 */ + clrsetbits_le32(&priv->regs->tmr, + GENMASK(31, 0), + CA_SF_TMR_CLK(0x07) + | CA_SF_TMR_SETUP(0x01) + | CA_SF_TMR_HOLD(0x01) + | CA_SF_TMR_IDLE(0x01)); + debug("%s: FLASH_TIMING reg=%#x\n", + __func__, readl(&priv->regs->tmr)); +} + +static int ca_sflash_probe(struct udevice *dev) +{ + struct ca_sflash_priv *priv = dev_get_priv(dev); + struct resource res; + int ret; + + /* Map the registers */ + ret = dev_read_resource_byname(dev, "sflash-regs", &res); + if (ret) { + dev_err(dev, "can't get regs base addresses(ret = %d)!\n", ret); + return ret; + } + priv->regs = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + ca_sflash_init(priv); + + printf("SFLASH: Controller probed ready\n"); + return 0; +} + +static const struct spi_controller_mem_ops ca_sflash_mem_ops = { + .exec_op = ca_sflash_exec_op, +}; + +static const struct dm_spi_ops ca_sflash_ops = { + .claim_bus = ca_sflash_claim_bus, + .release_bus = ca_sflash_release_bus, + .set_speed = ca_sflash_set_speed, + .set_mode = ca_sflash_set_mode, + .mem_ops = &ca_sflash_mem_ops, +}; + +static const struct udevice_id ca_sflash_ids[] = { + {.compatible = "cortina,ca-sflash"}, + {} +}; + +U_BOOT_DRIVER(ca_sflash) = { + .name = "ca_sflash", + .id = UCLASS_SPI, + .of_match = ca_sflash_ids, + .ops = &ca_sflash_ops, + .priv_auto_alloc_size = sizeof(struct ca_sflash_priv), + .probe = ca_sflash_probe, +}; From 936a645609145363b9580adeda831ab3d9ac1d78 Mon Sep 17 00:00:00 2001 From: Hongwei Zhang <hongweiz@ami.com> Date: Mon, 7 Dec 2020 17:40:01 -0500 Subject: [PATCH 176/222] mtd: spi-nor-ids: add Micron MT25QL01G flash Add Micron MT25QL01G flash, used on AST2600 board. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2812e600ea..5bd5dd3003 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -185,6 +185,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, From 21a1bc6a900c33efe4da4cc1b33efcfa543fd9d0 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski <m.szyprowski@samsung.com> Date: Fri, 18 Dec 2020 11:43:45 +0100 Subject: [PATCH 177/222] ARM: dts: meson: switch TFLASH_VDD_EN pin to open drain on Odroid-C4 For the proper reboot Odroid-C4 board requires to switch TFLASH_VDD_EN pin to the high impedance mode, otherwise the board is stuck in the middle of loading early stages of the bootloader from SD card. This can be achieved by using the OPEN_DRAIN flag instead if the ACTIVE_HIGH, what will leave the pin in input to achieve high state (pin has the pull-up) and solve the issue. Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi index c431988075..fbcc8287c5 100644 --- a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi +++ b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi @@ -11,3 +11,7 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; }; + +&tflash_vdd { + gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; +}; From 24ceb441c7c04cee6f3fd3faad4b875a7e09eafe Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Wed, 16 Dec 2020 12:15:49 +0100 Subject: [PATCH 178/222] doc: button command Provide a description of the 'button' command. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- doc/usage/button.rst | 64 ++++++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 2 files changed, 65 insertions(+) create mode 100644 doc/usage/button.rst diff --git a/doc/usage/button.rst b/doc/usage/button.rst new file mode 100644 index 0000000000..ea41762757 --- /dev/null +++ b/doc/usage/button.rst @@ -0,0 +1,64 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +button command +============== + +Synopsis +-------- + +:: + + button list + button <name> + +Description +----------- + +The button command is used to retrieve the status of a button. To show the +status of a button with name 'button1' you would issue the command + +:: + + button button1 + +The status of the button is both written to the console as *ON* or *OFF* and +set in the return value variable *$?* as 0 (true) or 1 (false). To retrieve +the status of a button with name *button1* and to write it to environment +variable *status1* you would execute the commands + +:: + + button button1 + setenv status1 $? + +A list of all available buttons and their status can be displayed using + +:: + + button list + +If a button device has not been probed yet, its status will be shown as +*<inactive>* in the list. + +Configuration +------------- + +To use the button command you must specify CONFIG_CMD_BUTTON=y and enable a +button driver. The available buttons are defined in the device-tree. + +Return value +------------ + +The variable *$?* takes the following values + ++---+-----------------------------+ +| 0 | ON, the button is pressed | ++---+-----------------------------+ +| 1 | OFF, the button is released | ++---+-----------------------------+ +| 0 | button list was shown | ++---+-----------------------------+ +| 1 | button not found | ++---+-----------------------------+ +| 1 | invalid arguments | ++---+-----------------------------+ diff --git a/doc/usage/index.rst b/doc/usage/index.rst index d0f5a9f26e..6c4b5b9240 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -12,4 +12,5 @@ Shell commands :maxdepth: 1 bootmenu + button pstore From 0c1b71cd07bf101586508b9d6e91948c0b493885 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Wed, 16 Dec 2020 22:08:38 +0100 Subject: [PATCH 179/222] doc: man-page for bootefi command Provide a description of the bootefi command. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- MAINTAINERS | 1 + doc/usage/bootefi.rst | 135 ++++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 3 files changed, 137 insertions(+) create mode 100644 doc/usage/bootefi.rst diff --git a/MAINTAINERS b/MAINTAINERS index 127e30c0a5..8675965fe5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -679,6 +679,7 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git F: doc/api/efi.rst F: doc/uefi/* +F: doc/usage/bootefi.rst F: drivers/rtc/emul_rtc.c F: include/capitalization.h F: include/charset.h diff --git a/doc/usage/bootefi.rst b/doc/usage/bootefi.rst new file mode 100644 index 0000000000..282f22aac9 --- /dev/null +++ b/doc/usage/bootefi.rst @@ -0,0 +1,135 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de> + +bootefi command +=============== + +Synopsis +-------- + +:: + + bootefi [image_addr] [fdt_addr] + bootefi bootmgr [fdt_addr] + bootefi hello [fdt_addr] + bootefi selftest [fdt_addr] + +Description +----------- + +The *bootefi* command is used to launch a UEFI binary which can be either of + +* UEFI application +* UEFI boot services driver +* UEFI run-time services driver + +An operating system requires a hardware description which can either be +presented as ACPI table (CONFIG\_GENERATE\_ACPI\_TABLE=y) or as device-tree +The load address of the device-tree may be provided as parameter *fdt\_addr*. If +this address is not specified, the bootefi command will try to fall back in +sequence to: + +* the device-tree specified by environment variable *fdt\_addr* +* the device-tree specified by environment variable *fdtcontroladdr* + +The load address of the binary is specified by parameter *image_address*. A +command sequence to run a UEFI application might look like + +:: + + load mmc 0:2 $fdt_addr_r dtb + load mmc 0:1 $kernel_addr_r /EFI/grub/grubaa64.efi + bootefi $kernel_addr_r $fdt_addr_r + +The last file loaded defines the image file path in the loaded image protocol. +Hence the executable should always be loaded last. + +The value of the environment variable *bootargs* is converted from UTF-8 to +UTF-16 and passed as load options in the loaded image protocol to the UEFI +binary. + +Note + UEFI binaries that are contained in FIT images are launched via the + *bootm* command. + +UEFI boot manager +''''''''''''''''' + +The UEFI boot manager is invoked by the *bootefi bootmgr* sub-command. +Here boot options are defined by UEFI variables with a name consisting of the +letters *Boot* followed by a four digit hexadecimal number, e.g. *Boot0001* or +*BootA03E*. The boot variable defines a label, the device path of the binary to +execute as well as the load options passed in the loaded image protocol. + +If the UEFI variable *BootNext* is defined, it specifies the number of the boot +option to execute next. If no binary can be loaded via *BootNext* the variable +*BootOrder* specifies in which sequence boot options shalled be tried. + +The values of these variables can be managed using the U-Boot command +*efidebug*. + +UEFI hello world application +'''''''''''''''''''''''''''' + +U-Boot can be compiled with a hello world application that can be launched using +the *bootefi hello* sub-command. A session might look like + +:: + + => setenv bootargs 'Greetings to the world' + => bootefi hello + Booting /MemoryMapped(0x0,0x10001000,0x1000) + Hello, world! + Running on UEFI 2.8 + Have SMBIOS table + Have device tree + Load options: Greetings to the world + +UEFI selftest +''''''''''''' + +U-Boot can be compiled with UEFI unit tests. These unit tests are invoked using +the *bootefi selftest* sub-command. + +Which unit test is executed is controlled by the environment variable +*efi\_selftest*. If this variable is not set, all unit tests that are not marked +as 'on request' are executed. + +To show a list of the available unit tests the value *list* can be used + +:: + + => setenv efi_selftest list + => bootefi selftest + + Available tests: + 'block image transfer' - on request + 'block device' + 'configuration tables' + ... + +A single test is selected for execution by setting the *efi\_selftest* +environment variable to match one of the listed identifiers + +:: + + => setenv efi_selftest 'block image transfer' + => bootefi selftest + +Some of the tests execute the ExitBootServices() UEFI boot service and will not +return to the command line but require a board reset. + +Configuration +------------- + +To use the *bootefi* command you must specify CONFIG\_CMD\_BOOTEFI=y. +The *bootefi hello* sub-command requries CMD\_BOOTEFI\_HELLO=y. +The *bootefi selftest* sub-command depends on CMD\_BOOTEFI\_SELFTEST=y. + +See also +-------- + +* *bootm* for launching UEFI binaries packed in FIT images +* *booti*, *bootm*, *bootz* for launching a Linux kernel without using the + UEFI sub-system +* *efidebug* for setting UEFI boot variables diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 6c4b5b9240..fbb2c0481c 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -11,6 +11,7 @@ Shell commands .. toctree:: :maxdepth: 1 + bootefi bootmenu button pstore From 265ce19485ab8aae9964307e80e0c52f8105c589 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Sun, 20 Dec 2020 11:05:38 +0100 Subject: [PATCH 180/222] efi_loader: make variable store size customizable Currently the size of the buffer to keep UEFI variables in memory is fixed at 16384 bytes. This size has proven to be too small for some use cases. Make the size of the memory buffer for UEFI variables customizable. Reported-by: Paulo Alcantara (SUSE) <pc@cjr.nz> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> --- include/efi_variable.h | 2 +- lib/efi_loader/Kconfig | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/efi_variable.h b/include/efi_variable.h index 4704a3c16e..bf5076233e 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -91,7 +91,7 @@ efi_status_t efi_query_variable_info_int(u32 attributes, #define EFI_VAR_FILE_NAME "ubootefi.var" -#define EFI_VAR_BUF_SIZE 0x4000 +#define EFI_VAR_BUF_SIZE CONFIG_EFI_VAR_BUF_SIZE /* * This constant identifies the file format for storing UEFI variables in diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 7fd3a3c90c..dd8b93bd3c 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -77,6 +77,20 @@ config EFI_VAR_SEED_FILE endif +config EFI_VAR_BUF_SIZE + int "Memory size of the UEFI variable store" + default 16384 + range 4096 2147483647 + help + This defines the size in bytes of the memory area reserved for keeping + UEFI variables. + + When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) this value should + match the value of PcdFlashNvStorageVariableSize used to compile the + StandAloneMM module. + + Minimum 4096, default 16384. + config EFI_GET_TIME bool "GetTime() runtime service" depends on DM_RTC From 73253d7765cd7da4f34ff64622913c40a7e23635 Mon Sep 17 00:00:00 2001 From: Paulo Alcantara <pc@cjr.nz> Date: Tue, 8 Dec 2020 20:10:48 -0300 Subject: [PATCH 181/222] tools: add a simple script to generate EFI variables This script generates EFI variables for U-Boot variable store format. A few examples: - Generating secure boot keys $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_PK/ \ -keyout PK.key -out PK.crt -nodes -days 365 $ efisiglist -a -c PK.crt -o foo.esl $ tools/efivar.py set -i ubootefi.var -n db -d foo.esl -t file $ tools/efivar.py set -i ubootefi.var -n kek -d foo.esl -t file $ tools/efivar.py set -i ubootefi.var -n pk -d foo.esl -t file - Printing out variables $ tools/efivar.py set -i ubootefi.var -n var1 -d foo -t str $ tools/efivar.py set -i ubootefi.var -n var2 -d bar -t str $ tools/efivar.py print -i ubootefi.var var1: 8be4df61-93ca-11d2-aa0d-00e098032b8c EFI_GLOBAL_VARIABLE_GUID NV|BS|RT, DataSize = 0x3 0000000000: 66 6F 6F foo var2: 8be4df61-93ca-11d2-aa0d-00e098032b8c EFI_GLOBAL_VARIABLE_GUID NV|BS|RT, DataSize = 0x3 0000000000: 62 61 72 bar - Removing variables $ tools/efivar.py del -i ubootefi.var -n var1 $ tools/efivar.py set -i ubootefi.var -n var1 -a nv,bs -d foo -t str $ tools/efivar.py print -i ubootefi.var -n var1 var1: 8be4df61-93ca-11d2-aa0d-00e098032b8c EFI_GLOBAL_VARIABLE_GUID NV|BS, DataSize = 0x3 0000000000: 66 6F 6F foo $ tools/efivar.py del -i ubootefi.var -n var1 err: attributes don't match $ tools/efivar.py del -i ubootefi.var -n var1 -a nv,bs $ tools/efivar.py print -i ubootefi.var -n var1 err: variable not found Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz> Correct examples in commit message. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- tools/efivar.py | 380 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 380 insertions(+) create mode 100755 tools/efivar.py diff --git a/tools/efivar.py b/tools/efivar.py new file mode 100755 index 0000000000..ebfcab2f0a --- /dev/null +++ b/tools/efivar.py @@ -0,0 +1,380 @@ +#!/usr/bin/env python3 +## SPDX-License-Identifier: GPL-2.0-only +# +# EFI variable store utilities. +# +# (c) 2020 Paulo Alcantara <palcantara@suse.de> +# + +import os +import struct +import uuid +import time +import zlib +import argparse +from OpenSSL import crypto + +# U-Boot variable store format (version 1) +UBOOT_EFI_VAR_FILE_MAGIC = 0x0161566966456255 + +# UEFI variable attributes +EFI_VARIABLE_NON_VOLATILE = 0x1 +EFI_VARIABLE_BOOTSERVICE_ACCESS = 0x2 +EFI_VARIABLE_RUNTIME_ACCESS = 0x4 +EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS = 0x10 +EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS = 0x20 +EFI_VARIABLE_READ_ONLY = 1 << 31 +NV_BS = EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS +NV_BS_RT = NV_BS | EFI_VARIABLE_RUNTIME_ACCESS +NV_BS_RT_AT = NV_BS_RT | EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS +DEFAULT_VAR_ATTRS = NV_BS_RT + +# vendor GUIDs +EFI_GLOBAL_VARIABLE_GUID = '8be4df61-93ca-11d2-aa0d-00e098032b8c' +EFI_IMAGE_SECURITY_DATABASE_GUID = 'd719b2cb-3d3a-4596-a3bc-dad00e67656f' +EFI_CERT_TYPE_PKCS7_GUID = '4aafd29d-68df-49ee-8aa9-347d375665a7' +WIN_CERT_TYPE_EFI_GUID = 0x0ef1 +WIN_CERT_REVISION = 0x0200 + +var_attrs = { + 'NV': EFI_VARIABLE_NON_VOLATILE, + 'BS': EFI_VARIABLE_BOOTSERVICE_ACCESS, + 'RT': EFI_VARIABLE_RUNTIME_ACCESS, + 'AT': EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS, + 'RO': EFI_VARIABLE_READ_ONLY, + 'AW': EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS, +} + +var_guids = { + 'EFI_GLOBAL_VARIABLE_GUID': EFI_GLOBAL_VARIABLE_GUID, + 'EFI_IMAGE_SECURITY_DATABASE_GUID': EFI_IMAGE_SECURITY_DATABASE_GUID, +} + +class EfiStruct: + # struct efi_var_file + var_file_fmt = '<QQLL' + var_file_size = struct.calcsize(var_file_fmt) + # struct efi_var_entry + var_entry_fmt = '<LLQ16s' + var_entry_size = struct.calcsize(var_entry_fmt) + # struct efi_time + var_time_fmt = '<H6BLh2B' + var_time_size = struct.calcsize(var_time_fmt) + # WIN_CERTIFICATE + var_win_cert_fmt = '<L2H' + var_win_cert_size = struct.calcsize(var_win_cert_fmt) + # WIN_CERTIFICATE_UEFI_GUID + var_win_cert_uefi_guid_fmt = var_win_cert_fmt+'16s' + var_win_cert_uefi_guid_size = struct.calcsize(var_win_cert_uefi_guid_fmt) + +class EfiVariable: + def __init__(self, size, attrs, time, guid, name, data): + self.size = size + self.attrs = attrs + self.time = time + self.guid = guid + self.name = name + self.data = data + +def calc_crc32(buf): + return zlib.crc32(buf) & 0xffffffff + +class EfiVariableStore: + def __init__(self, infile): + self.infile = infile + self.efi = EfiStruct() + if os.path.exists(self.infile) and os.stat(self.infile).st_size > self.efi.var_file_size: + with open(self.infile, 'rb') as f: + buf = f.read() + self._check_header(buf) + self.ents = buf[self.efi.var_file_size:] + else: + self.ents = bytearray() + + def _check_header(self, buf): + hdr = struct.unpack_from(self.efi.var_file_fmt, buf, 0) + magic, crc32 = hdr[1], hdr[3] + + if magic != UBOOT_EFI_VAR_FILE_MAGIC: + print("err: invalid magic number: %s"%hex(magic)) + exit(1) + if crc32 != calc_crc32(buf[self.efi.var_file_size:]): + print("err: invalid crc32: %s"%hex(crc32)) + exit(1) + + def _get_var_name(self, buf): + name = '' + for i in range(0, len(buf) - 1, 2): + if not buf[i] and not buf[i+1]: + break + name += chr(buf[i]) + return ''.join([chr(x) for x in name.encode('utf_16_le') if x]), i + 2 + + def _next_var(self, offs=0): + size, attrs, time, guid = struct.unpack_from(self.efi.var_entry_fmt, self.ents, offs) + data_fmt = str(size)+"s" + offs += self.efi.var_entry_size + name, namelen = self._get_var_name(self.ents[offs:]) + offs += namelen + data = struct.unpack_from(data_fmt, self.ents, offs)[0] + # offset to next 8-byte aligned variable entry + offs = (offs + len(data) + 7) & ~7 + return EfiVariable(size, attrs, time, uuid.UUID(bytes_le=guid), name, data), offs + + def __iter__(self): + self.offs = 0 + return self + + def __next__(self): + if self.offs < len(self.ents): + var, noffs = self._next_var(self.offs) + self.offs = noffs + return var + else: + raise StopIteration + + def __len__(self): + return len(self.ents) + + def _set_var(self, guid, name_data, size, attrs, tsec): + ent = struct.pack(self.efi.var_entry_fmt, + size, + attrs, + tsec, + uuid.UUID(guid).bytes_le) + ent += name_data + self.ents += ent + + def del_var(self, guid, name, attrs): + offs = 0 + while offs < len(self.ents): + var, loffs = self._next_var(offs) + if var.name == name and str(var.guid): + if var.attrs != attrs: + print("err: attributes don't match") + exit(1) + self.ents = self.ents[:offs] + self.ents[loffs:] + return + offs = loffs + print("err: variable not found") + exit(1) + + def set_var(self, guid, name, data, size, attrs): + offs = 0 + while offs < len(self.ents): + var, loffs = self._next_var(offs) + if var.name == name and str(var.guid) == guid: + if var.attrs != attrs: + print("err: attributes don't match") + exit(1) + # make room for updating var + self.ents = self.ents[:offs] + self.ents[loffs:] + break + offs = loffs + + tsec = int(time.time()) if attrs & EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS else 0 + nd = name.encode('utf_16_le') + b"\x00\x00" + data + # U-Boot variable format requires the name + data blob to be 8-byte aligned + pad = ((len(nd) + 7) & ~7) - len(nd) + nd += bytes([0] * pad) + + return self._set_var(guid, nd, size, attrs, tsec) + + def save(self): + hdr = struct.pack(self.efi.var_file_fmt, + 0, + UBOOT_EFI_VAR_FILE_MAGIC, + len(self.ents) + self.efi.var_file_size, + calc_crc32(self.ents)) + + with open(self.infile, 'wb') as f: + f.write(hdr) + f.write(self.ents) + +def parse_attrs(attrs): + v = DEFAULT_VAR_ATTRS + if attrs: + v = 0 + for i in attrs.split(','): + v |= var_attrs[i.upper()] + return v + +def parse_data(val, vtype): + if not val or not vtype: + return None, 0 + fmt = { 'u8': '<B', 'u16': '<H', 'u32': '<L', 'u64': '<Q' } + if vtype.lower() == 'file': + with open(val, 'rb') as f: + data = f.read() + return data, len(data) + if vtype.lower() == 'str': + data = val.encode('utf-8') + return data, len(data) + if vtype.lower() == 'nil': + return None, 0 + i = fmt[vtype.lower()] + return struct.pack(i, int(val)), struct.calcsize(i) + +def parse_args(args): + name = args.name + attrs = parse_attrs(args.attrs) + guid = args.guid if args.guid else EFI_GLOBAL_VARIABLE_GUID + + if name.lower() == 'db' or name.lower() == 'dbx': + name = name.lower() + guid = EFI_IMAGE_SECURITY_DATABASE_GUID + attrs = NV_BS_RT_AT + elif name.lower() == 'pk' or name.lower() == 'kek': + name = name.upper() + guid = EFI_GLOBAL_VARIABLE_GUID + attrs = NV_BS_RT_AT + + data, size = parse_data(args.data, args.type) + return guid, name, attrs, data, size + +def cmd_set(args): + env = EfiVariableStore(args.infile) + guid, name, attrs, data, size = parse_args(args) + env.set_var(guid=guid, name=name, data=data, size=size, attrs=attrs) + env.save() + +def print_var(var): + print(var.name+':') + print(" "+str(var.guid)+' '+''.join([x for x in var_guids if str(var.guid) == var_guids[x]])) + print(" "+'|'.join([x for x in var_attrs if var.attrs & var_attrs[x]])+", DataSize = %s"%hex(var.size)) + hexdump(var.data) + +def cmd_print(args): + env = EfiVariableStore(args.infile) + if not args.name and not args.guid and not len(env): + return + + found = False + for var in env: + if not args.name: + if args.guid and args.guid != str(var.guid): + continue + print_var(var) + found = True + else: + if args.name != var.name or (args.guid and args.guid != str(var.guid)): + continue + print_var(var) + found = True + + if not found: + print("err: variable not found") + exit(1) + +def cmd_del(args): + env = EfiVariableStore(args.infile) + attrs = parse_attrs(args.attrs) + guid = args.guid if args.guid else EFI_GLOBAL_VARIABLE_GUID + env.del_var(guid, args.name, attrs) + env.save() + +def pkcs7_sign(cert, key, buf): + with open(cert, 'r') as f: + crt = crypto.load_certificate(crypto.FILETYPE_PEM, f.read()) + with open(key, 'r') as f: + pkey = crypto.load_privatekey(crypto.FILETYPE_PEM, f.read()) + + PKCS7_BINARY = 0x80 + PKCS7_DETACHED = 0x40 + PKCS7_NOATTR = 0x100 + + bio_in = crypto._new_mem_buf(buf) + p7 = crypto._lib.PKCS7_sign(crt._x509, pkey._pkey, crypto._ffi.NULL, bio_in, + PKCS7_BINARY|PKCS7_DETACHED|PKCS7_NOATTR) + bio_out = crypto._new_mem_buf() + crypto._lib.i2d_PKCS7_bio(bio_out, p7) + return crypto._bio_to_string(bio_out) + +# UEFI 2.8 Errata B "8.2.2 Using the EFI_VARIABLE_AUTHENTICATION_2 descriptor" +def cmd_sign(args): + guid, name, attrs, data, size = parse_args(args) + attrs |= EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS + efi = EfiStruct() + + tm = time.localtime() + etime = struct.pack(efi.var_time_fmt, + tm.tm_year, tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec, + 0, 0, 0, 0, 0) + + buf = name.encode('utf_16_le') + uuid.UUID(guid).bytes_le + attrs.to_bytes(4, byteorder='little') + etime + if data: + buf += data + sig = pkcs7_sign(args.cert, args.key, buf) + + desc = struct.pack(efi.var_win_cert_uefi_guid_fmt, + efi.var_win_cert_uefi_guid_size + len(sig), + WIN_CERT_REVISION, + WIN_CERT_TYPE_EFI_GUID, + uuid.UUID(EFI_CERT_TYPE_PKCS7_GUID).bytes_le) + + with open(args.outfile, 'wb') as f: + if data: + f.write(etime + desc + sig + data) + else: + f.write(etime + desc + sig) + +def main(): + ap = argparse.ArgumentParser(description='EFI variable store utilities') + subp = ap.add_subparsers(help="sub-command help") + + printp = subp.add_parser('print', help='get/list EFI variables') + printp.add_argument('--infile', '-i', required=True, help='file to save the EFI variables') + printp.add_argument('--name', '-n', help='variable name') + printp.add_argument('--guid', '-g', help='vendor GUID') + printp.set_defaults(func=cmd_print) + + setp = subp.add_parser('set', help='set EFI variable') + setp.add_argument('--infile', '-i', required=True, help='file to save the EFI variables') + setp.add_argument('--name', '-n', required=True, help='variable name') + setp.add_argument('--attrs', '-a', help='variable attributes (values: nv,bs,rt,at,ro,aw)') + setp.add_argument('--guid', '-g', help="vendor GUID (default: %s)"%EFI_GLOBAL_VARIABLE_GUID) + setp.add_argument('--type', '-t', help='variable type (values: file|u8|u16|u32|u64|str)') + setp.add_argument('--data', '-d', help='data or filename') + setp.set_defaults(func=cmd_set) + + delp = subp.add_parser('del', help='delete EFI variable') + delp.add_argument('--infile', '-i', required=True, help='file to save the EFI variables') + delp.add_argument('--name', '-n', required=True, help='variable name') + delp.add_argument('--attrs', '-a', help='variable attributes (values: nv,bs,rt,at,ro,aw)') + delp.add_argument('--guid', '-g', help="vendor GUID (default: %s)"%EFI_GLOBAL_VARIABLE_GUID) + delp.set_defaults(func=cmd_del) + + signp = subp.add_parser('sign', help='sign time-based EFI payload') + signp.add_argument('--cert', '-c', required=True, help='x509 certificate filename in PEM format') + signp.add_argument('--key', '-k', required=True, help='signing certificate filename in PEM format') + signp.add_argument('--name', '-n', required=True, help='variable name') + signp.add_argument('--attrs', '-a', help='variable attributes (values: nv,bs,rt,at,ro,aw)') + signp.add_argument('--guid', '-g', help="vendor GUID (default: %s)"%EFI_GLOBAL_VARIABLE_GUID) + signp.add_argument('--type', '-t', required=True, help='variable type (values: file|u8|u16|u32|u64|str|nil)') + signp.add_argument('--data', '-d', help='data or filename') + signp.add_argument('--outfile', '-o', required=True, help='output filename of signed EFI payload') + signp.set_defaults(func=cmd_sign) + + args = ap.parse_args() + args.func(args) + +def group(a, *ns): + for n in ns: + a = [a[i:i+n] for i in range(0, len(a), n)] + return a + +def join(a, *cs): + return [cs[0].join(join(t, *cs[1:])) for t in a] if cs else a + +def hexdump(data): + toHex = lambda c: '{:02X}'.format(c) + toChr = lambda c: chr(c) if 32 <= c < 127 else '.' + make = lambda f, *cs: join(group(list(map(f, data)), 8, 2), *cs) + hs = make(toHex, ' ', ' ') + cs = make(toChr, ' ', '') + for i, (h, c) in enumerate(zip(hs, cs)): + print (' {:010X}: {:48} {:16}'.format(i * 16, h, c)) + +if __name__ == '__main__': + main() From 77504ee6764994f18039f7f634a419a1606296b0 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Sun, 20 Dec 2020 11:58:25 +0100 Subject: [PATCH 182/222] MAINTAINERS: add tools/efivar.py to EFI PAYLOAD tools/efivar.py allows to prepare a file with UEFI variables to preseed the UEFI variable store. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8675965fe5..f18a2966f1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -697,6 +697,7 @@ F: test/unicode_ut.c F: cmd/bootefi.c F: cmd/efidebug.c F: cmd/nvedit_efi.c +F: tools/efivar.py F: tools/file2include.c EFI VARIABLES VIA OP-TEE From e668bec96a5f8d9f6c1619038e8147816f040192 Mon Sep 17 00:00:00 2001 From: Michael Walle <michael@walle.cc> Date: Sun, 20 Dec 2020 22:35:13 +0100 Subject: [PATCH 183/222] board: kontron: sl28: reorder mmc devices Since linux commit 2e6cde96873253fd9eb0f20afd8ffd18278cff75 ("arm64: dts: ls1028a: make the eMMC and SD card controllers use fixed indices") mmc0 is the eMMC and mmc1 is the SD card. Also swap it in u-boot to avoid any confusion by the user and to be aligned with linux. Signed-off-by: Michael Walle <michael@walle.cc> --- arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 ++-- include/configs/kontron_sl28.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 2375549c6e..e63684c334 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -4,8 +4,8 @@ / { aliases { - mmc0 = &esdhc0; - mmc1 = &esdhc1; + mmc0 = &esdhc1; + mmc1 = &esdhc0; i2c0 = &i2c0; i2c1 = &i2c3; i2c2 = &i2c4; diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index afe512a8c7..442fb58b97 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -89,8 +89,8 @@ "ramdisk_addr_r=0x88080000\0" #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ func(NVME, nvme, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, 0) \ From 1e5f7df934e1e728357f5a329903737ff7d20585 Mon Sep 17 00:00:00 2001 From: Tom Rini <trini@konsulko.com> Date: Tue, 15 Dec 2020 19:06:03 -0500 Subject: [PATCH 184/222] Travis-CI: Drop support Travis-CI is changing their support for FOSS (understandably) to have a limited per-month number of build minutes. Unfortunately for us, the matrix of jobs we run will exhaust that very quickly. Remove the yml file. Thanks for all the builds, Travis-CI! Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- .travis.yml | 698 ---------------------------------------------------- 1 file changed, 698 deletions(-) delete mode 100644 .travis.yml diff --git a/.travis.yml b/.travis.yml deleted file mode 100644 index 69829fcfa0..0000000000 --- a/.travis.yml +++ /dev/null @@ -1,698 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright Roger Meier <r.meier@siemens.com> - -# build U-Boot on Travis CI - https://travis-ci.org/ - -sudo: required -dist: bionic - -language: c - -addons: - apt: - update: true - sources: - - sourceline: 'deb http://apt.llvm.org/bionic/ llvm-toolchain-bionic-10 main' - key_url: 'https://apt.llvm.org/llvm-snapshot.gpg.key' - packages: - - autopoint - - cppcheck - - sloccount - - sparse - - bc - - build-essential - - libsdl2-dev - - python - - python3-sphinx - - python3-virtualenv - - python3-pip - - python3-pygit2 - - swig - - libpython-dev - - iasl - - grub-efi-ia32-bin - - grub-efi-amd64-bin - - rpm2cpio - - wget - - device-tree-compiler - - lzop - - liblz4-tool - - lzma-alone - - libisl15 - - clang-10 - - srecord - - graphviz - - coreutils - - util-linux - - dosfstools - - gdisk - - mount - - mtools - - openssl - - sbsigntool - - fakeroot - - mtd-utils - - squashfs-tools - -install: - # Clone uboot-test-hooks - - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks - - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - # prepare buildman environment - - echo -e "[toolchain]\nroot = /usr" > ~/.buildman - - echo -e "arc = /tmp/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman - - echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman - - echo -e "x86 = i386" >> ~/.buildman; - - echo -e "riscv = riscv64" >> ~/.buildman; - - cat ~/.buildman - - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - - wget http://mirrors.kernel.org/ubuntu/pool/main/m/mpfr4/libmpfr4_3.1.4-1_amd64.deb && sudo dpkg -i libmpfr4_3.1.4-1_amd64.deb && rm libmpfr4_3.1.4-1_amd64.deb - - wget http://mirrors.kernel.org/ubuntu/pool/universe/e/efitools/efitools_1.8.1-0ubuntu2_amd64.deb && sudo dpkg -i efitools_1.8.1-0ubuntu2_amd64.deb && rm efitools_1.8.1-0ubuntu2_amd64.deb - -env: - global: - - PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/sbin:/usr/bin:/bin:/usr/local/bin - - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci - - BUILD_DIR=build - - HOSTCC="cc" - - HOSTCXX="c++" - - QEMU_VERSION="v4.2.0" - -before_script: - # install toolchains based on TOOLCHAIN} variable - - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi - - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi - - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi - - if [[ "${TOOLCHAIN}" == *sh* ]]; then ./tools/buildman/buildman --fetch-arch sh2 ; fi - - if [[ "${TOOLCHAIN}" == *i386* ]]; then - ./tools/buildman/buildman --fetch-arch i386; - fi - - if [[ "${TOOLCHAIN}" == arc ]]; then - wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2019.09-release/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install.tar.gz && - tar -C /tmp -xf arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install.tar.gz; - fi - - if [[ "${TOOLCHAIN}" == "nds32" ]]; then - wget https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz && - tar -C /tmp -xf nds32le-linux-glibc-v3-upstream.tar.gz && - echo -e "\n[toolchain-prefix]\nnds32 = /tmp/nds32le-linux-glibc-v3-upstream/bin/nds32le-linux-" >> ~/.buildman; - fi - - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then - wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz && - tar -C /tmp -xf x86_64-2018.02-${TOOLCHAIN}.tar.gz && - echo -e "\n[toolchain-prefix]\nxtensa = /tmp/2018.02/${TOOLCHAIN}/bin/${TOOLCHAIN}-" >> ~/.buildman; - fi - # If TOOLCHAIN is unset, we're on some flavour of ARM. - - if [[ "${TOOLCHAIN}" == "" ]]; then - ./tools/buildman/buildman --fetch-arch arm && - ./tools/buildman/buildman --fetch-arch aarch64; - fi - - if [[ "${TOOLCHAIN}" == "powerpc" ]]; then ./tools/buildman/buildman --fetch-arch powerpc; fi - - if [[ "${TOOLCHAIN}" == "riscv" ]]; then - ./tools/buildman/buildman --fetch-arch riscv32 && - ./tools/buildman/buildman --fetch-arch riscv64; - fi - - if [[ "${QEMU_TARGET}" != "" ]]; then - git clone git://git.qemu.org/qemu.git /tmp/qemu; - pushd /tmp/qemu; - git submodule update --init dtc && - git checkout ${QEMU_VERSION} && - ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} && - make -j4 all install; - popd; - fi - - # Build GRUB UEFI targets - - if [[ "${QEMU_TARGET}" == "arm-softmmu" ]]; then - git clone git://git.savannah.gnu.org/grub.git /tmp/grub && - pushd /tmp/grub && - git checkout grub-2.04 && - ./bootstrap && - ./configure --target=arm --with-platform=efi - CC=gcc - TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc - TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy - TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip - TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm - TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && - make -j4 && - ./grub-mkimage -O arm-efi -o ~/grub_arm.efi --prefix= -d - grub-core cat chain configfile echo efinet ext2 fat halt help linux - lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot - search search_fs_file search_fs_uuid search_label serial sleep test - true && - popd; - fi - - if [[ "${QEMU_TARGET}" == "aarch64-softmmu" ]]; then - git clone git://git.savannah.gnu.org/grub.git /tmp/grub && - pushd /tmp/grub && - git checkout grub-2.04 && - ./bootstrap && - ./configure --target=aarch64 --with-platform=efi - CC=gcc - TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc - TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy - TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip - TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm - TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && - make -j4 && - ./grub-mkimage -O arm64-efi -o ~/grub_arm64.efi --prefix= -d - grub-core cat chain configfile echo efinet ext2 fat halt help linux - lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot - search search_fs_file search_fs_uuid search_label serial sleep test - true && - popd; - fi - - if [[ "${QEMU_TARGET}" == "riscv32-softmmu" ]]; then - git clone git://git.savannah.gnu.org/grub.git /tmp/grub && - pushd /tmp/grub && - git checkout grub-2.04 && - ./bootstrap && - ./configure --target=riscv32 --with-platform=efi - CC=gcc - TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-gcc - TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-objcopy - TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-strip - TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-nm - TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-ranlib && - make -j4 && - ./grub-mkimage -O riscv32-efi -o ~/grub_riscv32.efi --prefix= -d - grub-core cat chain configfile echo efinet ext2 fat halt help linux - lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot - search search_fs_file search_fs_uuid search_label serial sleep test - true && - popd; - fi - - if [[ "${QEMU_TARGET}" == "riscv64-softmmu" ]]; then - git clone git://git.savannah.gnu.org/grub.git /tmp/grub && - pushd /tmp/grub && - git checkout grub-2.04 && - ./bootstrap && - ./configure --target=riscv64 --with-platform=efi - CC=gcc - TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc - TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy - TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip - TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm - TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && - make -j4 && - ./grub-mkimage -O riscv64-efi -o ~/grub_riscv64.efi --prefix= -d - grub-core cat chain configfile echo efinet ext2 fat halt help linux - lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot - search search_fs_file search_fs_uuid search_label serial sleep test - true && - popd; - fi - - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; - fi - - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; - fi - -script: - # Comments must be outside the command strings below, or the Travis parser - # will get confused. - # - # If we've been asked to use clang only do one configuration. - # - # Build a selection of boards if TEST_PY_BD is empty - - if [[ "${BUILDMAN}" != "" ]]; then - ret=0 - tools/buildman/buildman -P -E -W ${BUILDMAN} ${OVERRIDE} || ret=$?; - if [[ $ret -ne 0 ]]; then - tools/buildman/buildman -seP ${BUILDMAN}; - exit $ret; - fi; - fi - # Build just the one board needed for testing, if TEST_PY_BD is non-empty - # Note: "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not - - if [[ "${TEST_PY_BD}" != "" ]]; then - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/${TEST_PY_BD}; - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/; - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/; - if [[ -e ~/grub_arm.efi ]]; then - cp ~/grub_arm.efi $UBOOT_TRAVIS_BUILD_DIR/; - fi; - if [[ -e ~/grub_arm64.efi ]]; then - cp ~/grub_arm64.efi $UBOOT_TRAVIS_BUILD_DIR/; - fi; - if [[ -e ~/grub_riscv32.efi ]]; then - cp ~/grub_riscv32.efi $UBOOT_TRAVIS_BUILD_DIR/; - fi; - if [[ -e ~/grub_riscv64.efi ]]; then - cp ~/grub_riscv64.efi $UBOOT_TRAVIS_BUILD_DIR/; - fi; - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e - --board ${TEST_PY_BD} ${OVERRIDE} || exit; - virtualenv -p /usr/bin/python3 /tmp/venv; - . /tmp/venv/bin/activate; - pip install -r test/py/requirements.txt; - ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} - ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} - --build-dir "$UBOOT_TRAVIS_BUILD_DIR" || exit; - if [[ -n "${TEST_PY_TOOLS}" ]]; then - export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"; - export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"; - pip install pyelftools && - ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test && - ./tools/patman/patman test && - ./tools/buildman/buildman -t && - ./tools/dtoc/dtoc -t && - make testconfig; - fi; - fi - -matrix: - include: - # we need to build by vendor due to 50min time limit for builds - # each env setting here is a dedicated build - - name: "buildman arc" - env: - - BUILDMAN="arc" - TOOLCHAIN="arc" - - name: "buildman arm11 arm7 arm920t arm946es" - env: - - BUILDMAN="arm11 arm7 arm920t arm946es" - - name: "buildman arm926ejs (non-NXP,siemens,at91,kirkwood,spear)" - env: - - JOB="arm926ejs" - BUILDMAN="arm926ejs -x freescale,siemens,at91,kirkwood,spear,omap" - - name: "buildman at91 (non arm v7)" - env: - - BUILDMAN="at91 -x armv7" - - name: "buildman at91 (non arm926ejs)" - env: - - BUILDMAN="at91 -x arm926ejs" - - name: "buildman boundary engicam toradex" - env: - - BUILDMAN="boundary engicam toradex" - - name: "buildman ARM bcm" - env: - - BUILDMAN="bcm -x mips" - - name: "buildman NXP ARM32 (catch-all)" - env: - - BUILDMAN="freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216" - - name: "buildman NXP LS101x" - env: - - BUILDMAN="freescale&ls101" - - name: "buildman NXP LS102x" - env: - - BUILDMAN="freescale&ls102" - - name: "buildman NXP LS104x" - env: - - BUILDMAN="freescale&ls104" - - name: "buildman NXP LS108x" - env: - - BUILDMAN="freescale&ls108" - - name: "buildman NXP LS20xx" - env: - - BUILDMAN="freescale&ls20" - - name: "buildman NXP LX216x" - env: - - BUILDMAN="freescale&lx216" - - name: "buildman i.MX6 tqc" - env: - - BUILDMAN="mx6&tqc" - - name: "buildman i.MX6 (catch-all)" - env: - - BUILDMAN="mx6 -x boundary,engicam,freescale,technexion,toradex,tqc" - - name: "buildman i.MX (non-i.MX6 catch-all)" - env: - - BUILDMAN="mx -x freescale,mx6,toradex,technexion" - - name: "buildman keystone 2/3" - env: - - BUILDMAN="k2 k3" - - name: "buildman samsung socfpga" - env: - - BUILDMAN="samsung socfpga" - - name: "buildman spear" - env: - - BUILDMAN="spear" - - name: "buildman sun4i" - env: - - BUILDMAN="sun4i" - - name: "buildman sun5i" - env: - - BUILDMAN="sun5i" - - name: "buildman sun6i" - env: - - BUILDMAN="sun6i" - - name: "buildman sun7i" - env: - - BUILDMAN="sun7i" - - name: "buildman 64bit sun8i" - env: - - BUILDMAN="sun8i&aarch64 -x orangepi" - - name: "buildman 32bit sun8i" - env: - - BUILDMAN="sun8i&armv7 -x orangepi" - - name: "buildman sun9i" - env: - - BUILDMAN="sun9i" - - name: "buildman sun50i" - env: - - BUILDMAN="sun50i -x orangepi" - - name: "buildman catch-all ARM" - env: - - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq" - - name: "buildman sandbox x86" - env: - - BUILDMAN="sandbox x86" - TOOLCHAIN="i386" - - name: "buildman technexion" - env: - - BUILDMAN="technexion" - - name: "buildman kirkwood" - env: - - BUILDMAN="kirkwood" - - name: "buildman mvebu" - env: - - BUILDMAN="mvebu" - - name: "buildman m68k" - env: - - BUILDMAN="m68k" - TOOLCHAIN="m68k" - - name: "buildman microblaze" - env: - - BUILDMAN="microblaze" - TOOLCHAIN="microblaze" - - name: "buildman mips" - env: - - BUILDMAN="mips" - TOOLCHAIN="mips" - - name: "buildman non-Freescale PowerPC" - env: - - BUILDMAN="powerpc -x freescale" - TOOLCHAIN="powerpc" - - name: "buildman mpc85xx&freescale (excluding many)" - env: - - BUILDMAN="mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*" - TOOLCHAIN="powerpc" - - name: "buildman t208xrdb corenet_ds" - env: - - BUILDMAN="t208xrdb corenet_ds" - TOOLCHAIN="powerpc" - - name: "buildman Freescale PowerPC" - env: - - BUILDMAN="t4qds b4860qds mpc83xx&freescale mpc86xx&freescale" - TOOLCHAIN="powerpc" - - name: "buildman t102*" - env: - - BUILDMAN="t102*" - TOOLCHAIN="powerpc" - - name: "buildman p1_p2_rdb_pc" - env: - - BUILDMAN="p1_p2_rdb_pc" - TOOLCHAIN="powerpc" - - name: "buildman p1010rdb bsc91" - env: - - BUILDMAN="p1010rdb bsc91" - TOOLCHAIN="powerpc" - - name: "buildman siemens" - env: - - BUILDMAN="siemens" - - name: "buildman tegra" - env: - - BUILDMAN="tegra -x toradex" - - name: "buildman am33xx (no siemens)" - env: - - BUILDMAN="am33xx -x siemens" - - name: "buildman omap" - env: - - BUILDMAN="omap" - - name: "buildman orangepi" - env: - - BUILDMAN="orangepi" - - name: "buildman uniphier" - env: - - BUILDMAN="uniphier" - - name: "buildman catch-all AArch64" - env: - - BUILDMAN="aarch64 -x bcm,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,sunxi,samsung,socfpga,rk,versal,zynq" - - name: "buildman rockchip" - env: - - BUILDMAN="rk -x orangepi" - - name: "buildman sh" - env: - - BUILDMAN="sh -x arm" - TOOLCHAIN="sh" - - name: "buildman Zynq* (ARMv7)" - env: - - BUILDMAN="zynq&armv7" - - name: "buildman ZynqMP and Versal" - env: - - BUILDMAN="versal|zynqmp&aarch64" - - name: "buildman xtensa" - env: - - BUILDMAN="xtensa" - TOOLCHAIN="xtensa-dc233c-elf" - - name: "buildman riscv" - env: - - BUILDMAN="riscv" - TOOLCHAIN="riscv" - - name: "buildman nds32" - env: - - BUILDMAN="nds32" - TOOLCHAIN="nds32" - - # QA jobs for code analytics - # static code analysis with cppcheck (we can add --enable=all later) - - name: "cppcheck" - script: - - cppcheck -j$(nproc) --force --quiet --inline-suppr . - # build HTML documentation - - name: "htmldocs" - script: - - make htmldocs - # search for TODO within source tree - - name: "grep TODO" - script: - - grep -r TODO . - # search for FIXME within source tree - - name: "grep FIXME HACK" - script: - - grep -r FIXME . - # search for HACK within source tree and ignore HACKKIT board - script: - - grep -r HACK . | grep -v HACKKIT - # some statistics about the code base - - name: "sloccount" - script: - - sloccount . - # ensure all configs have MAINTAINERS entries - - name: "Check for configs without MAINTAINERS entry" - script: - - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi - # Ensure host tools build - - name: "Build tools-only" - script: - - make tools-only_config tools-only -j$(nproc) - # Ensure env tools build - - name: "Build envtools" - script: - - make tools-only_config envtools -j$(nproc) - - - name: "Run tests for Nokia RX-51 (aka N900)" - script: - - export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH - - test/nokia_rx51_test.sh - - # test/py - - name: "test/py sandbox" - env: - - TEST_PY_BD="sandbox" - TOOLCHAIN="i386" - - name: "test/py sandbox with clang" - env: - - TEST_PY_BD="sandbox" - OVERRIDE="-O clang-10" - - name: "test/py sandbox_spl" - env: - - TEST_PY_BD="sandbox_spl" - TEST_PY_TEST_SPEC="test_ofplatdata or test_handoff or test_spl" - TOOLCHAIN="i386" - TEST_PY_TOOLS="yes" - - name: "test/py sandbox_flattree" - env: - - TEST_PY_BD="sandbox_flattree" - TOOLCHAIN="i386" - - name: "test/py evb-ast2500" - env: - - TEST_PY_BD="evb-ast2500" - TEST_PY_ID="--id qemu" - QEMU_TARGET="arm-softmmu" - - name: "test/py vexpress_ca15_tc2" - env: - - TEST_PY_BD="vexpress_ca15_tc2" - TEST_PY_ID="--id qemu" - QEMU_TARGET="arm-softmmu" - - name: "test/py vexpress_ca9x4" - env: - - TEST_PY_BD="vexpress_ca9x4" - TEST_PY_ID="--id qemu" - QEMU_TARGET="arm-softmmu" - - name: "test/py integratorcp_cm926ejs" - env: - - TEST_PY_BD="integratorcp_cm926ejs" - TEST_PY_TEST_SPEC="not sleep" - TEST_PY_ID="--id qemu" - QEMU_TARGET="arm-softmmu" - - name: "test/py qemu_arm" - env: - - TEST_PY_BD="qemu_arm" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="arm-softmmu" - - name: "test/py qemu_arm64" - env: - - TEST_PY_BD="qemu_arm64" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="aarch64-softmmu" - - name: "test/py qemu_mips" - env: - - TEST_PY_BD="qemu_mips" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="mips-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu_mipsel" - env: - - TEST_PY_BD="qemu_mipsel" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="mipsel-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu_mips64" - env: - - TEST_PY_BD="qemu_mips64" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="mips64-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu_mips64el" - env: - - TEST_PY_BD="qemu_mips64el" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="mips64el-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu-malta" - env: - - TEST_PY_BD="malta" - TEST_PY_TEST_SPEC="not sleep and not efi" - TEST_PY_ID="--id qemu" - QEMU_TARGET="mips-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu-maltael" - env: - - TEST_PY_BD="maltael" - TEST_PY_TEST_SPEC="not sleep and not efi" - TEST_PY_ID="--id qemu" - QEMU_TARGET="mipsel-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu-malta64" - env: - - TEST_PY_BD="malta64" - TEST_PY_TEST_SPEC="not sleep and not efi" - TEST_PY_ID="--id qemu" - QEMU_TARGET="mips64-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu-malta64el" - env: - - TEST_PY_BD="malta64el" - TEST_PY_TEST_SPEC="not sleep and not efi" - TEST_PY_ID="--id qemu" - QEMU_TARGET="mips64el-softmmu" - TOOLCHAIN="mips" - - name: "test/py qemu-ppce500" - env: - - TEST_PY_BD="qemu-ppce500" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="ppc-softmmu" - TOOLCHAIN="powerpc" - - name: "test/py qemu-riscv32" - env: - - TEST_PY_BD="qemu-riscv32" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="riscv32-softmmu" - TOOLCHAIN="riscv" - - name: "test/py qemu-riscv64" - env: - - TEST_PY_BD="qemu-riscv64" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="riscv64-softmmu" - TOOLCHAIN="riscv" - - name: "test/py qemu-riscv32_spl" - env: - - TEST_PY_BD="qemu-riscv32_spl" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="riscv32-softmmu" - TOOLCHAIN="riscv" - - name: "test/py qemu-riscv64_spl" - env: - - TEST_PY_BD="qemu-riscv64_spl" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="riscv64-softmmu" - TOOLCHAIN="riscv" - - name: "test/py qemu-x86" - env: - - TEST_PY_BD="qemu-x86" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="i386-softmmu" - TOOLCHAIN="i386" - BUILD_ROM="yes" - - name: "test/py qemu-x86_64" - env: - - TEST_PY_BD="qemu-x86_64" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="x86_64-softmmu" - TOOLCHAIN="i386" - BUILD_ROM="yes" - - name: "test/py r2dplus_i82557c" - env: - - TEST_PY_BD="r2dplus" - TEST_PY_ID="--id i82557c_qemu" - QEMU_TARGET="sh4-softmmu" - BUILDMAN="sh -x arm" - TOOLCHAIN="sh" - - name: "test/py r2dplus_pcnet" - env: - - TEST_PY_BD="r2dplus" - TEST_PY_ID="--id pcnet_qemu" - QEMU_TARGET="sh4-softmmu" - BUILDMAN="sh -x arm" - TOOLCHAIN="sh" - - name: "test/py r2dplus_rtl8139" - env: - - TEST_PY_BD="r2dplus" - TEST_PY_ID="--id rtl8139_qemu" - QEMU_TARGET="sh4-softmmu" - BUILDMAN="sh -x arm" - TOOLCHAIN="sh" - - name: "test/py r2dplus_tulip" - env: - - TEST_PY_BD="r2dplus" - TEST_PY_ID="--id tulip_qemu" - QEMU_TARGET="sh4-softmmu" - BUILDMAN="sh -x arm" - TOOLCHAIN="sh" - - name: "test/py xilinx_zynq_virt" - env: - - TEST_PY_BD="xilinx_zynq_virt" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="arm-softmmu" - TEST_PY_ID="--id qemu" - - name: "test/py xilinx_versal_virt" - env: - - TEST_PY_BD="xilinx_versal_virt" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="aarch64-softmmu" - TEST_PY_ID="--id qemu" - - name: "test/py xtfpga" - env: - - TEST_PY_BD="xtfpga" - TEST_PY_TEST_SPEC="not sleep" - QEMU_TARGET="xtensa-softmmu" - TEST_PY_ID="--id qemu" - TOOLCHAIN="xtensa-dc233c-elf" - -# TODO make it perfect ;-r From c15f44acf9d473f4682bfdc63b8aebd313492b15 Mon Sep 17 00:00:00 2001 From: Tom Rini <trini@konsulko.com> Date: Mon, 21 Dec 2020 15:03:24 -0500 Subject: [PATCH 185/222] Prepare v2021.01-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 41446d80cb..679e4a603a 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2021 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* From e7eeb6dd2d727ae32c3b796a4c04604fc3eb5650 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Fri, 27 Nov 2020 17:59:09 +0200 Subject: [PATCH 186/222] doc: edison: Update information about xFSTK xFSTK sources got a new home under Edison Firmware Group on GitHub [1]. Update Intel Edison documentation accordingly. While here, fix couple of typos. [1]: https://github.com/edison-fw Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> --- doc/board/intel/edison.rst | 49 ++++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/doc/board/intel/edison.rst b/doc/board/intel/edison.rst index d658fac02c..5a65673d1e 100644 --- a/doc/board/intel/edison.rst +++ b/doc/board/intel/edison.rst @@ -23,38 +23,48 @@ use. more step (if and only if you have original U-Boot), i.e. run the following command:: - $ truncate -s %4096 u-boot.bin + $ truncate -s %4096 u-boot.bin 2. Run your board and interrupt booting to U-Boot console. In the console call:: - => run do_force_flash_os + => run do_force_flash_os 3. Wait for few seconds, it will prepare environment variable and runs DFU. Run DFU command from the host system:: - $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin + $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin 4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and reset the board:: - => reset - + => reset Updating U-Boot using xFSTK --------------------------- You can also update U-Boot using the xfstk-dldr-solo tool if you can build it. -One way to do that is to follow the `xFSTK`_ instructions. You may need to use -a virtual machine running Ubuntu Trusty. Once you have built it and installed -libboost-all-dev, you can copy xfstk-dldr-solo to /usr/local/bin and +One way to do that is to follow the `xFSTK`_ instructions. In short, after you +install all necessary dependencies and clone repository, it will look like this: + +.. code-block:: sh + + cd xFSTK + export DISTRIBUTION_NAME=ubuntu20.04 + export BUILD_VERSION=1.8.5 + git checkout v$BUILD_VERSION + ... + +Once you have built it, you can copy xfstk-dldr-solo to /usr/local/bin and libboost_program_options.so.1.54.0 to /usr/lib/i386-linux-gnu/ and with luck -it will work. You might fine this `drive`_ helpful. +it will work. You might find this `drive`_ helpful. -If it does, then you can download and unpack the Edison reocovery image, -install dfu-util, reset your board and flash U-Boot like this:: +If it does, then you can download and unpack the Edison recovery image, +install dfu-util, reset your board and flash U-Boot like this: - $ xfstk-dldr-solo --gpflags 0x80000007 \ +.. code-block:: sh + + xfstk-dldr-solo --gpflags 0x80000007 \ --osimage u-boot-edison.img \ --fwdnx recover/edison_dnx_fwr.bin \ --fwimage recover/edison_ifwi-dbg-00.bin \ @@ -64,7 +74,7 @@ This should show the following .. code-block:: none - XFSTK Downloader Solo 0.0.0 + XFSTK Downloader Solo 1.8.5 Copyright (c) 2015 Intel Corporation Build date and time: Aug 15 2020 15:07:13 @@ -75,13 +85,12 @@ This should show the following .......(lots of dots)........XFSTK-STATUS--Reconnecting to device - Attempt #1 .......(even more dots)...................... - You have about 10 seconds after resetting the board to type the above command. If you want to check if the board is ready, type: .. code-block:: none - lsusb |egrep "8087|8086" + lsusb | egrep "8087|8086" Bus 001 Device 004: ID 8086:e005 Intel Corp. If you see a device with the same ID as above, the board is waiting for your @@ -112,9 +121,9 @@ After about 5 seconds you should see some console output from the board: *** Ready to receive application *** - After another 10 seconds the xFSTK tool completes and the board resets. About - 10 seconds after that should see the above message again and then within a - few seconds U-Boot should start on your board: +After another 10 seconds the xFSTK tool completes and the board resets. About +10 seconds after that should see the above message again and then within a few +seconds U-Boot should start on your board: .. code-block:: none @@ -146,7 +155,7 @@ After about 5 seconds you should see some console output from the board: Building boot_params at 0x00090000 Loading bzImage at address 100000 (5427456 bytes) Magic signature found - Kernel command line: "rootwait root=PARTUUID=ada722ed-6410-764e-8619-abff6f66e10e rootfstype=ext4 console=ttyMFD2 earlyprintk=ttyMFD2,keep loglevel=4 g_multi.ethernet_config=cdc systemd.unit=multi-user.target hardware_id=00 g_multi.iSerialNumber=2249baf774c675598661a63098c0ad41 g_multi.dev_addr=02:00:86:c0:ad:41 platform_mrfld_audio.audio_codec=dummy" + Kernel command line: "rootwait ..." Magic signature found Starting kernel ... @@ -157,5 +166,5 @@ After about 5 seconds you should see some console output from the board: edison login: -.. _xFSTK: https://community.intel.com/t5/Intel-Makers/Building-xFSTK-on-Ubuntu-14-04-32-bit-for-flashing-Edison/td-p/538081 +.. _xFSTK: https://github.com/edison-fw/xFSTK .. _drive: https://drive.google.com/drive/u/0/folders/1URPHrOk9-UBsh8hjv-7WwC0W6Fy61uAJ From 6ef1b7508740dfce9b30f172839b385361e8bd50 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu <sughosh.ganu@linaro.org> Date: Mon, 14 Dec 2020 11:52:44 +0530 Subject: [PATCH 187/222] fsp: Move and rename fsp_types.h file The fsp_types.h header file contains macros for building signatures of different widths. These signature macros are architecture agnostic, and can be used in all places which use signatures in a data structure. Move and rename the fsp_types.h under the common include header. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/include/asm/fsp/fsp_support.h | 3 ++- .../x86/include/asm/fsp/fsp_types.h => include/signatures.h | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) rename arch/x86/include/asm/fsp/fsp_types.h => include/signatures.h (95%) diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 29e511415c..3cd3e4fcf5 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -7,11 +7,12 @@ #ifndef __FSP_SUPPORT_H__ #define __FSP_SUPPORT_H__ +#include <signatures.h> + #include <asm/fsp/fsp_bootmode.h> #include <asm/fsp/fsp_fv.h> #include <asm/fsp/fsp_hob.h> #include <asm/fsp/fsp_infoheader.h> -#include <asm/fsp/fsp_types.h> #include <asm/fsp_arch.h> #include <asm/fsp/fsp_azalia.h> diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/include/signatures.h similarity index 95% rename from arch/x86/include/asm/fsp/fsp_types.h rename to include/signatures.h index 3d5b17ecf1..4042db1e00 100644 --- a/arch/x86/include/asm/fsp/fsp_types.h +++ b/include/signatures.h @@ -4,8 +4,8 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ +#ifndef __SIGNATURES_H__ +#define __SIGNATURES_H__ /** * Returns a 16-bit signature built from 2 ASCII characters. @@ -59,4 +59,4 @@ #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) -#endif +#endif /* __SIGNATURES_H__ */ From 2055103f0848cfbb773420057e2e38c76aceb697 Mon Sep 17 00:00:00 2001 From: Oliver Graute <oliver.graute@kococonnector.com> Date: Fri, 4 Dec 2020 15:26:16 +0100 Subject: [PATCH 188/222] ARM: dts: imx: imx8qm-rom7720: Fix AR8031 phy-mode Fixed wrong PHY Interface Mode As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Fix the phy-mode accordingly to fix the regression. Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> --- arch/arm/dts/imx8qm-rom7720-a1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts index 5f9ac955ed..d1f2fff869 100644 --- a/arch/arm/dts/imx8qm-rom7720-a1.dts +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts @@ -293,7 +293,7 @@ &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,ar8031-phy-fixup; fsl,magic-packet; @@ -318,7 +318,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy1>; fsl,ar8031-phy-fixup; fsl,magic-packet; From d72cecec7fc0b04d6d52df44ae1e7033ee7e4099 Mon Sep 17 00:00:00 2001 From: Adam Ford <aford173@gmail.com> Date: Fri, 4 Dec 2020 17:27:45 -0600 Subject: [PATCH 189/222] imx: imx8mm: Update clock bindings header Import clock bindings header file from Linux 5.10-rc6 Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> --- include/dt-bindings/clock/imx8mm-clock.h | 28 +++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 07e6c686f3..e63a5530ae 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -248,6 +248,32 @@ #define IMX8MM_CLK_SNVS_ROOT 228 #define IMX8MM_CLK_GIC 229 -#define IMX8MM_CLK_END 230 +#define IMX8MM_SYS_PLL1_40M_CG 230 +#define IMX8MM_SYS_PLL1_80M_CG 231 +#define IMX8MM_SYS_PLL1_100M_CG 232 +#define IMX8MM_SYS_PLL1_133M_CG 233 +#define IMX8MM_SYS_PLL1_160M_CG 234 +#define IMX8MM_SYS_PLL1_200M_CG 235 +#define IMX8MM_SYS_PLL1_266M_CG 236 +#define IMX8MM_SYS_PLL1_400M_CG 237 +#define IMX8MM_SYS_PLL2_50M_CG 238 +#define IMX8MM_SYS_PLL2_100M_CG 239 +#define IMX8MM_SYS_PLL2_125M_CG 240 +#define IMX8MM_SYS_PLL2_166M_CG 241 +#define IMX8MM_SYS_PLL2_200M_CG 242 +#define IMX8MM_SYS_PLL2_250M_CG 243 +#define IMX8MM_SYS_PLL2_333M_CG 244 +#define IMX8MM_SYS_PLL2_500M_CG 245 + +#define IMX8MM_CLK_M4_CORE 246 +#define IMX8MM_CLK_VPU_CORE 247 +#define IMX8MM_CLK_GPU3D_CORE 248 +#define IMX8MM_CLK_GPU2D_CORE 249 + +#define IMX8MM_CLK_CLKO2 250 + +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_END 252 #endif From 15d79fcac09fee7d27ff0a0c36389433507ce3bd Mon Sep 17 00:00:00 2001 From: Adam Ford <aford173@gmail.com> Date: Fri, 4 Dec 2020 17:27:46 -0600 Subject: [PATCH 190/222] arm: dts: imx8mm: sync dts from Linux Kernel 5.10-rc6 There have been some updates to the device tree since 5.6. This also includes some clocks, and makes it easier to keep board device tree files in sync with Linux Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/dts/imx8mm.dtsi | 119 ++++++++++++++++++++++++++++++++------- 1 file changed, 99 insertions(+), 20 deletions(-) diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index 1e5e11592f..05ee062548 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -18,10 +18,18 @@ aliases { ethernet0 = &fec1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -29,14 +37,6 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; }; cpus { @@ -68,6 +68,7 @@ nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -80,6 +81,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -92,6 +94,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -104,6 +107,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -125,7 +129,7 @@ opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; + opp-microvolt = <950000>; opp-supported-hw = <0xc>, <0x7>; clock-latency-ns = <150000>; opp-suspend; @@ -204,6 +208,38 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; @@ -227,12 +263,14 @@ ranges = <0x0 0x0 0x0 0x3e000000>; aips1: bus@30000000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30000000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; sai1: sai@30010000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -246,6 +284,7 @@ }; sai2: sai@30020000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -273,6 +312,7 @@ }; sai5: sai@30050000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@ -286,6 +326,7 @@ }; sai6: sai@30060000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@ -363,6 +404,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -419,7 +467,7 @@ reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { + ocotp: efuse@30350000 { compatible = "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; @@ -455,6 +503,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "snvs-pwrkey"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; @@ -469,16 +519,20 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MM_CLK_NOC>, + assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, + <&clk IMX8MM_CLK_A53_CORE>, + <&clk IMX8MM_CLK_NOC>, <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL3_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, + assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, <750000000>, @@ -496,7 +550,8 @@ }; aips2: bus@30400000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30400000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; @@ -555,10 +610,12 @@ }; aips3: bus@30800000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30800000 0x400000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; ecspi1: spi@30820000 { compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; @@ -718,6 +775,14 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; @@ -760,6 +825,19 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, + <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -776,7 +854,8 @@ reg = <0x30be0000 0x10000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET_TIMER>, @@ -800,7 +879,8 @@ }; aips4: bus@32c00000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; @@ -896,7 +976,6 @@ ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; }; From 1170d2b759096af0e7ba6ffaf6abde286a7d6595 Mon Sep 17 00:00:00 2001 From: Adam Ford <aford173@gmail.com> Date: Fri, 4 Dec 2020 17:27:47 -0600 Subject: [PATCH 191/222] arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6 There have been some updates to the device trees, so re-sync. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 16 ++++----- arch/arm/dts/imx8mm-beacon-som.dtsi | 44 +++++++++++++++++------ 2 files changed, 41 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi index baa5f997d0..d6b9dedd16 100644 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi @@ -10,19 +10,19 @@ led0 { label = "gen_led0"; gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led1 { label = "gen_led1"; gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led2 { label = "gen_led2"; gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led3 { @@ -70,7 +70,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; eeprom@0 { @@ -210,7 +210,7 @@ >; }; - pinctrl_pcal6414: pcal6414-gpio { + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; @@ -240,7 +240,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -259,7 +259,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -271,7 +271,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index 801bd02eae..b88c3c99b0 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -24,6 +24,26 @@ cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -52,9 +72,10 @@ pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -116,7 +137,7 @@ ldo1_reg: LDO1 { regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; @@ -124,7 +145,7 @@ ldo2_reg: LDO2 { regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; @@ -164,7 +185,7 @@ status = "okay"; eeprom@50 { - compatible = "microchip, at24c64d", "atmel,24c64"; + compatible = "microchip,24c64", "atmel,24c64"; pagesize = <32>; read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x50>; @@ -190,6 +211,7 @@ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; clocks = <&osc_32k>; + max-speed = <4000000>; clock-names = "extclk"; }; }; @@ -270,9 +292,9 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; @@ -289,7 +311,7 @@ >; }; - pinctrl_usdhc1_gpio: usdhc1grpgpio { + pinctrl_usdhc1_gpio: usdhc1gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 >; @@ -306,7 +328,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 @@ -317,7 +339,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 @@ -344,7 +366,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -360,7 +382,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 From 1a5d9c84b47239ea527f5d8eaa19f35b7fdacb8f Mon Sep 17 00:00:00 2001 From: Adam Ford <aford173@gmail.com> Date: Fri, 4 Dec 2020 18:59:43 -0600 Subject: [PATCH 192/222] imx8mm_beacon: Enable HS400 on MMC controller The i.MX8MM is capable of HS400. Enable it in both U-Boot and SPL for faster throughput. Signed-off-by: Adam Ford <aford173@gmail.com> --- configs/imx8mm_beacon_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index c5d331f617..49d5453078 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -70,6 +70,13 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y From 247bbeb74c186963d9365db3136d0285618bd9a7 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Date: Sat, 5 Dec 2020 17:29:17 +0000 Subject: [PATCH 193/222] ARM: dts: imx8m: increase off-on delay on the SD Vcc regulator Some SD Card controller and power circuitry has increased capacitance, which keeps the internal logic remains powered after regulator is switch off. This is generally the case when card is switched to SD104 mode, where a power cycle should be performed. In case if the card internal logic remains powered, it causes a subsequent failure of mode transition, effectively leading to failed enumeration. Introduce a delay of 20 msec in order to provide a possibility for internal card circuitry to drain voltages and perform a power cycle correctly. Similar fix is done in commit c49d0ac38a76 ("ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator") targeted Renesas SOCs. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Stefano Babic <sbabic@denx.de> --- arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mq-evk-u-boot.dtsi | 5 +++++ arch/arm/dts/imx8mq-phanbell-u-boot.dtsi | 5 +++++ 6 files changed, 26 insertions(+) create mode 100644 arch/arm/dts/imx8mq-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mq-phanbell-u-boot.dtsi diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index fc1aebb2fe..6d80a529ae 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -37,6 +37,10 @@ /delete-property/ assigned-clock-rates; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &fec1 { phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index b5c12105a9..9f77d3c6ff 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -46,6 +46,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_reg_usdhc2_vmmc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 4419679d4c..98b0b9891b 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -47,6 +47,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_uart2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 24a93ac2d6..2452e9175c 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -48,6 +48,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + ®_usdhc2_vmmc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi new file mode 100644 index 0000000000..4712cf6a44 --- /dev/null +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi new file mode 100644 index 0000000000..4712cf6a44 --- /dev/null +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; From 50b1a69cee0dc06d0c713a5a978998f2b4a9cb31 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Date: Sat, 5 Dec 2020 17:29:18 +0000 Subject: [PATCH 194/222] ARM: dts: imx8m: add UHS or HS400/HS400ES properties i.MX8M series provide support for high speed grades in their usdhc controllers, which has eMMC and SDHC connected to them. Enable this support across the entire i.MX8M family by providing quirks to usdhc controllers designated by storage media connected to them. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> --- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 3 +++ arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 3 +++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mq-evk-u-boot.dtsi | 9 +++++++++ 6 files changed, 27 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 80d6475b7c..9e0d264b71 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 771ab635f1..701af4434d 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 9f77d3c6ff..e843a5648e 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -100,10 +100,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &i2c1 { diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 98b0b9891b..025090fff4 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -97,10 +97,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 2452e9175c..4f00b5a3a9 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -126,10 +126,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 4712cf6a44..44af663727 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -3,3 +3,12 @@ ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; + +&usdhc1 { + mmc-hs400-1_8v; +}; + +&usdhc2 { + sd-uhs-sdr104; + sd-uhs-ddr50; +}; From e601f0f9c966e5485a4b7d950082b97c81af3151 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Date: Sat, 5 Dec 2020 17:29:19 +0000 Subject: [PATCH 195/222] configs: imx8m: enable eMMC HS400ES and SD UHS mode on EVK i.MX8M series includes support for high speed modes in uSDHC controllers. Turn on corresponding configuration options for EVK boards, which would enable high speed modes to be included in U-Boot. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> --- configs/imx8mm_evk_defconfig | 4 ++++ configs/imx8mn_ddr4_evk_defconfig | 4 ++++ configs/imx8mp_evk_defconfig | 3 +++ 3 files changed, 11 insertions(+) diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 91d3bc3ac9..1aef1ab40d 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -66,6 +66,10 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 22e5f5aeea..41889c4624 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -65,6 +65,10 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index cd5724e811..f84696f030 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -70,6 +70,9 @@ CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y From 72397c9621ab37f117ac171d3090f11a2e6b33d6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam <festevam@gmail.com> Date: Mon, 14 Dec 2020 14:32:39 -0300 Subject: [PATCH 196/222] mx6sabresd: Remove unneeded checkboard() After the conversion to device tree the board information becomes redundant: Model: Freescale i.MX6 Quad Plus SABRE Smart Device Board Board: MX6-SabreSD Remove the printing of the board information. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 0d343da519..9a176f4711 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -575,12 +575,6 @@ int board_late_init(void) return 0; } -int checkboard(void) -{ - puts("Board: MX6-SabreSD\n"); - return 0; -} - #ifdef CONFIG_SPL_BUILD #include <asm/arch/mx6-ddr.h> #include <spl.h> From db43c0b72d1eb0dcf2778413743fcf355b5632a1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel <sebastian.reichel@collabora.com> Date: Tue, 15 Dec 2020 00:41:53 +0100 Subject: [PATCH 197/222] compiler.h: add host_build() Add a host_build() function, so that it's possible to check for software being build with USE_HOSTCC without relying on preprocessor conditions. In other words #ifdef USE_HOSTCC host_only_code(); #endif can be written like this instead: if (host_build()) host_only_code(); This improves code readability and test coverage and compiler will eleminate this unreachable code. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> --- include/compiler.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/compiler.h b/include/compiler.h index 90b7afae53..27b9843497 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -6,6 +6,7 @@ #define __COMPILER_H__ #include <stddef.h> +#include <stdbool.h> #ifdef USE_HOSTCC @@ -150,4 +151,12 @@ typedef unsigned long int uintptr_t; #define MEM_SUPPORT_64BIT_DATA 0 #endif +static inline bool host_build(void) { +#ifdef USE_HOSTCC + return true; +#else + return false; +#endif +} + #endif From 548fb67eef14f83d60310193415ac9d06a3bd286 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas <ilias.apalodimas@linaro.org> Date: Wed, 23 Dec 2020 13:25:00 +0200 Subject: [PATCH 198/222] efi_loader: Extra checks while opening an OPTEE session When opening an OP-TEE session we need to check the internal return value of OP-TEE call arguments as well the return code of the function itself. The code was also ignoring to close the OP-TEE session in case the shared memory registration failed. Fixes: f042e47e8fb43 ("efi_loader: Implement EFI variable handling via OP-TEE") Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- lib/efi_loader/efi_variable_tee.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index be6f3dfad4..b8808fdeca 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -36,20 +36,29 @@ static int get_connection(struct mm_connection *conn) static const struct tee_optee_ta_uuid uuid = PTA_STMM_UUID; struct udevice *tee = NULL; struct tee_open_session_arg arg; - int rc; + int rc = -ENODEV; tee = tee_find_device(tee, NULL, NULL, NULL); if (!tee) - return -ENODEV; + goto out; memset(&arg, 0, sizeof(arg)); tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); rc = tee_open_session(tee, &arg, 0, NULL); - if (!rc) { - conn->tee = tee; - conn->session = arg.session; + if (rc) + goto out; + + /* Check the internal OP-TEE result */ + if (arg.ret != TEE_SUCCESS) { + rc = -EIO; + goto out; } + conn->tee = tee; + conn->session = arg.session; + + return 0; +out: return rc; } @@ -88,6 +97,7 @@ static efi_status_t optee_mm_communicate(void *comm_buf, ulong dsize) if (tee_shm_register(conn.tee, comm_buf, buf_size, 0, &shm)) { log_err("Unable to register shared memory\n"); + tee_close_session(conn.tee, conn.session); return EFI_UNSUPPORTED; } From c44d374bef118a07b44a5a5f596569891cfc6d21 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel <sebastian.reichel@collabora.com> Date: Tue, 15 Dec 2020 00:41:56 +0100 Subject: [PATCH 199/222] board: ge: bx50v3: remove confidx magic numbers Instead of hardcoding index magic numbers in the board code, also rely on board_fit_config_name_match choosing the right config for the fitImage containing the kernel. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- board/ge/bx50v3/bx50v3.c | 16 ++++++++++------ include/configs/ge_bx50v3.h | 4 ++-- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 4754647fb4..a3ae037a82 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -356,15 +356,12 @@ static void process_vpd(struct vpd_cache *vpd) switch (vpd->product_id) { case VPD_PRODUCT_B450: - env_set("confidx", "1"); i210_index = 1; break; case VPD_PRODUCT_B650: - env_set("confidx", "2"); i210_index = 1; break; case VPD_PRODUCT_B850: - env_set("confidx", "3"); i210_index = 2; break; } @@ -554,16 +551,23 @@ int ft_board_setup(void *blob, struct bd_info *bd) int board_fit_config_name_match(const char *name) { + const char *machine = name; + if (!vpd.is_read) return strcmp(name, "imx6q-bx50v3"); + if (!strncmp(machine, "Boot ", 5)) + machine += 5; + if (!strncmp(machine, "imx6q-", 6)) + machine += 6; + switch (vpd.product_id) { case VPD_PRODUCT_B450: - return strcmp(name, "imx6q-b450v3"); + return strcasecmp(machine, "b450v3"); case VPD_PRODUCT_B650: - return strcmp(name, "imx6q-b650v3"); + return strcasecmp(machine, "b650v3"); case VPD_PRODUCT_B850: - return strcmp(name, "imx6q-b850v3"); + return strcasecmp(machine, "b850v3"); default: return -1; } diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index e5c580b3f9..2d854af9a0 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -62,7 +62,7 @@ "networkboot=" \ "run setnetworkboot; " \ "nfs ${loadaddr} /srv/nfs/fitImage; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ #define CONFIG_NETWORKBOOTCOMMAND \ "run networkboot; " \ @@ -111,7 +111,7 @@ "doboot=" \ "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ "run setargs; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ "tryboot=" \ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ "run loadimage || run swappartitions && run loadimage || " \ From 717bf50f4b362c1f4fac5ac9f030fab5bed9cf65 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel <sebastian.reichel@collabora.com> Date: Tue, 15 Dec 2020 00:41:57 +0100 Subject: [PATCH 200/222] board: ge: bx50v3: cleanup phy config The current PHY rework does the following things: 1. Configure 125MHz clock 2. Setup the TX clock delay (RX is enabled by default), 3. Setup reserved bits to avoid voltage peak The clock delays are nowadays already configured by the PHY driver (in ar803x_delay_config). The code for that can simply be dropped. The clock speed can also be configured by the PHY driver by adding the device tree property "qca,clk-out-frequency". What is left is setting up the undocumented reserved bits to avoid the voltage peak problem. I slightly improved its documentation while updating the board's PHY rework code. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- arch/arm/dts/imx6q-ba16.dtsi | 11 +++++++++++ board/ge/bx50v3/bx50v3.c | 35 ++++++++++++----------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/dts/imx6q-ba16.dtsi b/arch/arm/dts/imx6q-ba16.dtsi index 7d8f61f2fd..9da2bb6e86 100644 --- a/arch/arm/dts/imx6q-ba16.dtsi +++ b/arch/arm/dts/imx6q-ba16.dtsi @@ -174,6 +174,17 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; status = "okay"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &hdmi { diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index a3ae037a82..3ea9425fd1 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -47,6 +47,10 @@ DECLARE_GLOBAL_DATA_PTR; #define VPD_PRODUCT_B650 2 #define VPD_PRODUCT_B450 3 +#define AR8033_DBG_REG_ADDR 0x1d +#define AR8033_DBG_REG_DATA 0x1e +#define AR8033_SERDES_REG 0x5 + static int productid; /* Default to generic. */ static struct vpd_cache vpd; @@ -61,31 +65,16 @@ int dram_init(void) return 0; } -static int mx6_rgmii_rework(struct phy_device *phydev) -{ - /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ - /* set device address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - /* offset 0x8016: CLK_25M Clock Select */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - /* enable register write, no post increment, address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - /* set to 125 MHz from local PLL source */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); - - /* rgmii tx clock delay enable */ - /* set debug port address: SerDes Test and System Mode Control */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - /* enable rgmii tx clock delay */ - /* set the reserved bits to avoid board specific voltage peak issue*/ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); - - return 0; -} - int board_phy_config(struct phy_device *phydev) { - mx6_rgmii_rework(phydev); + /* + * Set reserved bits to avoid board specific voltage peak issue. The + * value is a magic number provided directly by Qualcomm. Note, that + * PHY driver will take control of BIT(8) in this register to control + * TX clock delay, so we do not initialize that bit here. + */ + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG); + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47); if (phydev->drv->config) phydev->drv->config(phydev); From 7d6a36a48d8226d363f8a4fab618e04b2a65e2cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= <peron.clem@gmail.com> Date: Mon, 21 Dec 2020 18:31:28 +0100 Subject: [PATCH 201/222] imx: ahab: allow to bypass confirmation for ahab_close cmd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Calling ahab_close cmd force the user to interact for confirmation. This is not user-friendly when using this cmd during factory process. Allow the user to pass '-y' option to bypass this confirmation. Signed-off-by: Clément Péron <peron.clem@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Oliver Graute <oliver.graute@kococonnector.com> --- arch/arm/mach-imx/imx8/ahab.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 4bb7c46921..600a1108ce 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -303,10 +303,11 @@ static int confirm_close(void) static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + int confirmed = argc >= 2 && !strcmp(argv[1], "-y"); int err; u16 lc; - if (!confirm_close()) + if (!confirmed && !confirm_close()) return -EACCES; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); From b6b1b38a94b45c4580b52076c0aa5f72cc3ce0eb Mon Sep 17 00:00:00 2001 From: Fabio Estevam <festevam@gmail.com> Date: Mon, 21 Dec 2020 15:40:37 -0300 Subject: [PATCH 202/222] imx8mp_evk: Increase CONFIG_SYS_MALLOC_F_LEN When booting imx8mp-evk the following allocation error message is seen: U-Boot 2021.01-rc3-00200-ge668bec96a5f (Dec 21 2020 - 14:36:42 -0300) alloc space exhausted Fix it by increasing CONFIG_SYS_MALLOC_F_LEN to 0x10000 like it is done on other i.MX8MM/8MN boards. Reported-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> --- configs/imx8mp_evk_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index f84696f030..6166d103e3 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_SYS_I2C_MXC_I2C1=y From f23c7068633d6087a4909b2cd0d83a62689a7d47 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk <igor.opaniuk@toradex.com> Date: Tue, 22 Dec 2020 17:56:46 +0200 Subject: [PATCH 203/222] toradex: hand over maintainership Hand over maintainership of Toradex SoMs (that I was responsible of) to Oleksandr because of my resignation from Toradex, as such I will have no immediate involvement with these modules and as a result not able to continue maintaining these boards. CC: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> --- board/toradex/apalis-imx8x/MAINTAINERS | 2 +- board/toradex/apalis_imx6/MAINTAINERS | 2 +- board/toradex/colibri-imx6ull/MAINTAINERS | 2 +- board/toradex/colibri_imx6/MAINTAINERS | 2 +- board/toradex/colibri_imx7/MAINTAINERS | 2 +- board/toradex/colibri_t20/MAINTAINERS | 2 +- board/toradex/colibri_t30/MAINTAINERS | 2 +- board/toradex/colibri_vf/MAINTAINERS | 2 +- board/toradex/verdin-imx8mm/MAINTAINERS | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS index fbf9379931..5272154447 100644 --- a/board/toradex/apalis-imx8x/MAINTAINERS +++ b/board/toradex/apalis-imx8x/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX8X -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software S: Maintained F: arch/arm/dts/fsl-imx8x-apalis.dts diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS index 4a2707e771..fde4d92dc3 100644 --- a/board/toradex/apalis_imx6/MAINTAINERS +++ b/board/toradex/apalis_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX6 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index 4107d29876..899b1ff555 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6ULL -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS index 76f9446bba..2cbf65433d 100644 --- a/board/toradex/colibri_imx6/MAINTAINERS +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index 61a504487a..3d7d010d8a 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX7 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS index 2a8e6fb74b..61fbd2c1e0 100644 --- a/board/toradex/colibri_t20/MAINTAINERS +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -1,5 +1,5 @@ COLIBRI_T20 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> S: Maintained F: board/toradex/colibri_t20/ F: include/configs/colibri_t20.h diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS index 00c03c89b8..ded9e28295 100644 --- a/board/toradex/colibri_t30/MAINTAINERS +++ b/board/toradex/colibri_t30/MAINTAINERS @@ -1,5 +1,5 @@ Colibri T30 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> S: Maintained F: board/toradex/colibri_t30/ F: include/configs/colibri_t30.h diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index f94cc0fbe2..c6627654a2 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,5 +1,5 @@ Colibri VFxx -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS index 2495696e9d..08c370178c 100644 --- a/board/toradex/verdin-imx8mm/MAINTAINERS +++ b/board/toradex/verdin-imx8mm/MAINTAINERS @@ -1,5 +1,5 @@ Verdin iMX8M Mini -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini S: Maintained F: arch/arm/dts/imx8mm-verdin.dts From d4d7b663b8cae5ef4209aaef21a2435a7d5d4dd7 Mon Sep 17 00:00:00 2001 From: Marc Ferland <ferlandm@amotus.ca> Date: Tue, 22 Dec 2020 14:24:11 -0500 Subject: [PATCH 204/222] arm: dart6ul: change compatible string for eeprom The eeprom at address 0x50 is a BR24G04NUX-3TTR. It has a 4Kbit (512x8) capacity, change the compatible string to reflect this fact. Also, add an alias to easily refer to this eeprom with fdt_path_offset() which will be in another commit. Signed-off-by: Marc Ferland <ferlandm@amotus.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com> --- arch/arm/dts/imx6ull-dart-6ul.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi index e96669f493..fed40b0109 100644 --- a/arch/arm/dts/imx6ull-dart-6ul.dtsi +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi @@ -14,6 +14,10 @@ chosen { stdout-path = &uart1; }; + + aliases { + eeprom0 = &eeprom_som; + }; }; &fec1 { @@ -97,9 +101,10 @@ sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; status = "okay"; - eeprom@50 { - compatible = "cat,24c32"; + eeprom_som: eeprom@50 { + compatible = "atmel,24c04"; reg = <0x50>; + status = "okay"; }; }; From 37648b600cd16848e689e341b20da71356e24212 Mon Sep 17 00:00:00 2001 From: Marc Ferland <ferlandm@amotus.ca> Date: Tue, 22 Dec 2020 14:24:12 -0500 Subject: [PATCH 205/222] arm: dart6ul: read and print SoM info from eeprom on startup The dart6ul has an i2c eeprom at 0x50 which contains, among other things, the manufacturing/revision/options info of the SoM. This patch replaces the current checkboard() implementation with a more exhaustive one based on the content of the eeprom. Since this code uses the new driver model, some changes were also required in the DTS to make the nodes related to i2c available before relocation. This code was inspired from the supported u-boot code from Variscite which can be found here: https://github.com/varigit/uboot-imx/tree/imx_v2018.03_4.14.78_1.0.0_ga_var02 New output example: Board: PN: VSM-6UL-705B, Assy: AS1812142257, Date: 2019 Feb 17 Storage: eMMC, Wifi: yes, DDR: 1024 MiB, Rev: 2.4G Signed-off-by: Marc Ferland <ferlandm@amotus.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com> --- arch/arm/dts/imx6ull-dart-6ul.dtsi | 8 +++ board/variscite/dart_6ul/dart_6ul.c | 104 +++++++++++++++++++++++++++- configs/variscite_dart6ul_defconfig | 2 + 3 files changed, 113 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi index fed40b0109..805a382da9 100644 --- a/arch/arm/dts/imx6ull-dart-6ul.dtsi +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi @@ -56,6 +56,10 @@ }; }; +&gpio1 { + u-boot,dm-pre-reloc; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -100,8 +104,10 @@ scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; status = "okay"; + u-boot,dm-pre-reloc; eeprom_som: eeprom@50 { + u-boot,dm-pre-reloc; compatible = "atmel,24c04"; reg = <0x50>; status = "okay"; @@ -210,6 +216,7 @@ }; pinctrl_i2c2: i2cgrp { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 @@ -217,6 +224,7 @@ }; pinctrl_i2c2_gpio: i2c2grp_gpio { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c index d8e383d323..360be758bb 100644 --- a/board/variscite/dart_6ul/dart_6ul.c +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -12,8 +12,11 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> +#include <dm.h> #include <fsl_esdhc_imx.h> +#include <i2c_eeprom.h> #include <linux/bitops.h> +#include <malloc.h> #include <miiphy.h> #include <netdev.h> #include <usb.h> @@ -222,9 +225,108 @@ int board_init(void) return 0; } +/* length of strings stored in the eeprom */ +#define DART6UL_PN_LEN 16 +#define DART6UL_ASSY_LEN 16 +#define DART6UL_DATE_LEN 12 + +/* eeprom content, 512 bytes */ +struct dart6ul_info { + u32 magic; + u8 partnumber[DART6UL_PN_LEN]; + u8 assy[DART6UL_ASSY_LEN]; + u8 date[DART6UL_DATE_LEN]; + u32 custom_addr_val[32]; + struct cmd { + u8 addr; + u8 index; + } custom_cmd[150]; + u8 res[33]; + u8 som_info; + u8 ddr_size; + u8 crc; +} __attribute__ ((__packed__)); + +#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3) +#define DART6UL_INFO_WIFI_GET(n) ((n) >> 2 & 0x1) +#define DART6UL_INFO_REV_GET(n) ((n) >> 3 & 0x3) +#define DART6UL_DDRSIZE_IN_MIB(n) ((n) << 8) +#define DART6UL_INFO_MAGIC 0x32524156 + +static const char *som_info_storage_to_str(u8 som_info) +{ + switch (DART6UL_INFO_STORAGE_GET(som_info)) { + case 0x0: return "none (SD only)"; + case 0x1: return "NAND"; + case 0x2: return "eMMC"; + default: return "unknown"; + } +} + +static const char *som_info_rev_to_str(u8 som_info) +{ + switch (DART6UL_INFO_REV_GET(som_info)) { + case 0x0: return "2.4G"; + case 0x1: return "5G"; + default: return "unknown"; + } +} + int checkboard(void) { - puts("Board: Variscite DART-6UL Evaluation Kit\n"); + const char *path = "eeprom0"; + struct dart6ul_info *info; + struct udevice *dev; + int ret, off; + + off = fdt_path_offset(gd->fdt_blob, path); + if (off < 0) { + printf("%s: fdt_path_offset() failed: %d\n", __func__, off); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret); + return ret; + } + + info = malloc(sizeof(struct dart6ul_info)); + if (!info) + return -ENOMEM; + + ret = i2c_eeprom_read(dev, 0, (uint8_t *)info, + sizeof(struct dart6ul_info)); + if (ret) { + printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret); + free(info); + return ret; + } + + if (info->magic != DART6UL_INFO_MAGIC) { + printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n", + info->magic, DART6UL_INFO_MAGIC); + /* do not fail if the content is invalid */ + free(info); + return 0; + } + + /* make sure strings are null terminated */ + info->partnumber[DART6UL_PN_LEN - 1] = '\0'; + info->assy[DART6UL_ASSY_LEN - 1] = '\0'; + info->date[DART6UL_DATE_LEN - 1] = '\0'; + + printf("Board: PN: %s, Assy: %s, Date: %s\n" + " Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n", + info->partnumber, + info->assy, + info->date, + som_info_storage_to_str(info->som_info), + DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no", + DART6UL_DDRSIZE_IN_MIB(info->ddr_size), + som_info_rev_to_str(info->som_info)); + + free(info); return 0; } diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 5f94cea5dd..721882567d 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -36,6 +36,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PHYLIB=y From e6abe163bf0b81d2ff6cfbc849252bb30b0d6a19 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Fri, 25 Dec 2020 16:22:27 +0100 Subject: [PATCH 206/222] imx: mx7: clock: use correct format strings Use %u and not %d for unsigned values. Print kHz and not khz. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/mach-imx/mx7/clock.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index aba9461d92..6a1bad855e 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -916,7 +916,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (5 == i) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } } @@ -936,7 +936,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (best == 0) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } @@ -1115,17 +1115,17 @@ int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, printf("\n"); - printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); - printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); + printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); + printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); #ifdef CONFIG_MXC_SPI - printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); + printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); #endif - printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); - printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); - printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); - printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); - printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); - printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); + printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); + printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); + printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); return 0; } From 26c7048dd9d04158a23e9dbfe3f0dccc4febcaed Mon Sep 17 00:00:00 2001 From: Marc Ferland <ferlandm@amotus.ca> Date: Mon, 21 Dec 2020 09:50:16 -0500 Subject: [PATCH 207/222] i2c: mxc_i2c: improve error message readability Use 0x%2lx to print the i2c bus base address in hexadecimal format instead of printing as an integer. Signed-off-by: Marc Ferland <ferlandm@amotus.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com> --- drivers/i2c/mxc_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 7609594bd0..d486dab043 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -954,7 +954,7 @@ static int mxc_i2c_probe(struct udevice *bus) !dm_gpio_is_valid(&i2c_bus->scl_gpio) || ret || ret2) { dev_err(bus, - "i2c bus %d at %lu, fail to request scl/sda gpio\n", + "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base); return -EINVAL; } From 33fc6fc105993f0ba3b19e93912ef2cc59e22cef Mon Sep 17 00:00:00 2001 From: Stefan Roese <sr@denx.de> Date: Thu, 10 Dec 2020 06:40:10 +0100 Subject: [PATCH 208/222] arm: mvebu: Add armada-xp-gp-u-boot.dtsi for U-Boot properties Add some missing "u-boot,dm-pre-reloc;" properties to UART0, SPI controller and SPI NOR flash node to enable usage in SPL. Otherwise these devices will not be available. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dennis Gilmore <dgilmore@redhat.com> Tested-by: Dennis Gilmore <dgilmore@redhat.com> --- arch/arm/dts/armada-xp-gp-u-boot.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/dts/armada-xp-gp-u-boot.dtsi diff --git a/arch/arm/dts/armada-xp-gp-u-boot.dtsi b/arch/arm/dts/armada-xp-gp-u-boot.dtsi new file mode 100644 index 0000000000..2422856616 --- /dev/null +++ b/arch/arm/dts/armada-xp-gp-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + soc { + internal-regs { + serial@12000 { + u-boot,dm-pre-reloc; + }; + }; + }; +}; + +&spi0 { + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + }; +}; From ce040932b569591f2907e246b771cd632eef52e7 Mon Sep 17 00:00:00 2001 From: Stefan Roese <sr@denx.de> Date: Fri, 11 Dec 2020 05:47:40 +0100 Subject: [PATCH 209/222] arm: mvebu: armada-xp-gp.dts: Add spi0 alias For correct spi bus detection the spi0 alias is needed in the DT. Otherwise this error will ocurr in U-Boot: Invalid bus 0 (err=-19) Failed to initialize SPI flash at 0:0 (error -19) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dennis Gilmore <dgilmore@redhat.com> Tested-by: Dennis Gilmore <dgilmore@redhat.com> --- arch/arm/dts/armada-xp-gp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts index 1139e9469a..d46475fe22 100644 --- a/arch/arm/dts/armada-xp-gp.dts +++ b/arch/arm/dts/armada-xp-gp.dts @@ -31,6 +31,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory@0 { device_type = "memory"; /* From 0eb0eb4ab225fd0ffb3f63429dba8d4fb82cb71c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> Date: Wed, 23 Dec 2020 16:07:08 +0100 Subject: [PATCH 210/222] Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 828d32621686aec593076d16445d39b9b8d49c05. This change revers code which asserting PERST# signal when unloading driver. Driver's remove callback is still there as it is used for other functionality. Asserting PERST# signal prior booting kernel is causing that A3720 boards (Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and 4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900) and anymore. When PERST# signal is not asserted these cards are detected correctly. As this is regression for existing stable Linux kernel versions revert this problematic change in U-Boot. To make cards working with OpenWRT 4.14 kernel it is needed to disable link training prior booting kernel, which is already done in driver's remove callback. Described issue is in Linux kernel pci aardvark driver which is (hopefully) fixed in latest upstream versions. Latest upstream versions should be able to initialize PCIe bus and detects cards independently of the link training and PERST# signal state. So with this change, U-Boot on A3720 boards should be able to boot OpenWRT 4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> --- drivers/pci/pci-aardvark.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index babb84ca93..5c6e30e667 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -649,9 +649,6 @@ static int pcie_advk_remove(struct udevice *dev) struct pcie_advk *pcie = dev_get_priv(dev); u32 reg; - if (dm_gpio_is_valid(&pcie->reset_gpio)) - dm_gpio_set_value(&pcie->reset_gpio, 1); - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg &= ~LINK_TRAINING_EN; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); From 5f9b53753118ade7b502bce9866ea527a8a86372 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Sun, 27 Dec 2020 15:33:09 +0100 Subject: [PATCH 211/222] efi_loader: missing parentheses after if IS_ENABLED() contains parentheses. But we should still put extra parentheses around it in an if statement for readability. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- lib/efi_loader/efi_boottime.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 246b59d3b3..32bdb81914 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -2000,7 +2000,7 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle, } if (!efi_st_keep_devices) { - if IS_ENABLED(CONFIG_USB_DEVICE) + if (IS_ENABLED(CONFIG_USB_DEVICE)) udc_disconnect(); board_quiesce_devices(); dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); From 9abb01af749f61de8467de05a27f7262fb1dec7b Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Sun, 27 Dec 2020 14:47:50 +0100 Subject: [PATCH 212/222] efi_loader: escape key handling Up to now the escape key was not correctly detected in UEFI applications. We had to hit it twice for a single escape to be recognized. Use a 10 ms delay to detect if we are dealing with the escape key or an escape sequence. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- lib/efi_loader/efi_console.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 011accab78..705109596e 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -14,6 +14,7 @@ #include <env.h> #include <stdio_dev.h> #include <video_console.h> +#include <linux/delay.h> #define EFI_COUT_MODE_2 2 #define EFI_MAX_COUT_MODE 3 @@ -688,6 +689,17 @@ static efi_status_t efi_cin_read_key(struct efi_key_data *key) switch (ch) { case 0x1b: + /* + * If a second key is received within 10 ms, assume that we are + * dealing with an escape sequence. Otherwise consider this the + * escape key being hit. 10 ms is long enough to work fine at + * 1200 baud and above. + */ + udelay(10000); + if (!tstc()) { + pressed_key.scan_code = 23; + break; + } /* * Xterm Control Sequences * https://www.xfree86.org/4.8.0/ctlseqs.html From e434311dbaf1e79b09ac01dce198499e328549f8 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Sun, 27 Dec 2020 15:46:00 +0100 Subject: [PATCH 213/222] efi_loader: avoid invalid free load_options passed from do_efibootmgr() to do_bootefi_exec() may contain invalid data from the stack which will lead to an invalid free(). Fixes: 0ad64007feb9 ("efi_loader: set load options in boot manager") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- lib/efi_loader/efi_bootmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 61dc72a23d..d3be2f94c6 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -275,7 +275,7 @@ static efi_status_t try_load_entry(u16 n, efi_handle_t *handle, memcpy(*load_options, lo.optional_data, size); ret = efi_set_load_options(*handle, size, *load_options); } else { - load_options = NULL; + *load_options = NULL; } error: From 34dc4a9ec9bef5ec5291d61a18fa523260302108 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Mon, 28 Dec 2020 00:59:09 +0100 Subject: [PATCH 214/222] efi_loader: efi_signal_event() fix comment typos Add missing commas. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- lib/efi_loader/efi_boottime.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 32bdb81914..417215a210 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -271,8 +271,8 @@ efi_status_t is_valid_tpl(efi_uintn_t tpl) * efi_signal_event() - signal an EFI event * @event: event to signal * - * This function signals an event. If the event belongs to an event group all - * events of the group are signaled. If they are of type EVT_NOTIFY_SIGNAL + * This function signals an event. If the event belongs to an event group, all + * events of the group are signaled. If they are of type EVT_NOTIFY_SIGNAL, * their notification function is queued. * * For the SignalEvent service see efi_signal_event_ext. From aeaf0e6d58093102aa35921c7bc6fcb0580504bd Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Mon, 28 Dec 2020 22:42:51 +0100 Subject: [PATCH 215/222] efi_loader: describe struct efi_loaded_image_obj Add the missing description of some fields of struct efi_loaded_image_obj. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- include/efi_loader.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/efi_loader.h b/include/efi_loader.h index 3c68b85b68..dc3c6ac304 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -297,8 +297,10 @@ enum efi_image_auth_status { * @exit_status: exit status passed to Exit() * @exit_data_size: exit data size passed to Exit() * @exit_data: exit data passed to Exit() - * @exit_jmp: long jump buffer for returning form started image + * @exit_jmp: long jump buffer for returning from started image * @entry: entry address of the relocated image + * @image_type: indicates if the image is an applicition or a driver + * @auth_status: indicates if the image is authenticated */ struct efi_loaded_image_obj { struct efi_object header; From be48b0f453a3903e924a4f1790f134b9b36e5fa8 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Mon, 28 Dec 2020 23:24:40 +0100 Subject: [PATCH 216/222] efi_loader: use after free in efi_exit() Do not use data from the loaded image object after deleting it. Fixes: 126a43f15b36 ("efi_loader: unload applications upon Exit()") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- include/efi_loader.h | 4 ++-- lib/efi_loader/efi_boottime.c | 17 ++++++++++++----- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/include/efi_loader.h b/include/efi_loader.h index dc3c6ac304..0fc2255f3f 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -304,10 +304,10 @@ enum efi_image_auth_status { */ struct efi_loaded_image_obj { struct efi_object header; - efi_status_t exit_status; + efi_status_t *exit_status; efi_uintn_t *exit_data_size; u16 **exit_data; - struct jmp_buf_data exit_jmp; + struct jmp_buf_data *exit_jmp; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); u16 image_type; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 417215a210..a89bdb3140 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -2899,6 +2899,8 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, efi_status_t ret; void *info; efi_handle_t parent_image = current_image; + efi_status_t exit_status; + struct jmp_buf_data exit_jmp; EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data); @@ -2920,9 +2922,11 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, image_obj->exit_data_size = exit_data_size; image_obj->exit_data = exit_data; + image_obj->exit_status = &exit_status; + image_obj->exit_jmp = &exit_jmp; /* call the image! */ - if (setjmp(&image_obj->exit_jmp)) { + if (setjmp(&exit_jmp)) { /* * We called the entry point of the child image with EFI_CALL * in the lines below. The child image called the Exit() boot @@ -2944,10 +2948,10 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, */ assert(__efi_entry_check()); EFI_PRINT("%lu returned by started image\n", - (unsigned long)((uintptr_t)image_obj->exit_status & + (unsigned long)((uintptr_t)exit_status & ~EFI_ERROR_MASK)); current_image = parent_image; - return EFI_EXIT(image_obj->exit_status); + return EFI_EXIT(exit_status); } current_image = image_handle; @@ -3130,6 +3134,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, struct efi_loaded_image *loaded_image_protocol; struct efi_loaded_image_obj *image_obj = (struct efi_loaded_image_obj *)image_handle; + struct jmp_buf_data *exit_jmp; EFI_ENTRY("%p, %ld, %zu, %p", image_handle, exit_status, exit_data_size, exit_data); @@ -3171,6 +3176,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, if (ret != EFI_SUCCESS) EFI_PRINT("%s: out of memory\n", __func__); } + /* efi_delete_image() frees image_obj. Copy before the call. */ + exit_jmp = image_obj->exit_jmp; + *image_obj->exit_status = exit_status; if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION || exit_status != EFI_SUCCESS) efi_delete_image(image_obj, loaded_image_protocol); @@ -3184,8 +3192,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, */ efi_restore_gd(); - image_obj->exit_status = exit_status; - longjmp(&image_obj->exit_jmp, 1); + longjmp(exit_jmp, 1); panic("EFI application exited"); out: From 71fd11b9013eda5b618737f91e2b19daabb775a3 Mon Sep 17 00:00:00 2001 From: Stefan Agner <stefan@agner.ch> Date: Wed, 30 Dec 2020 13:16:36 +0100 Subject: [PATCH 217/222] nvme: Use only 32-bit accesses in nvme_writeq/nvme_readq There might be hardware configurations where 64-bit data accesses to NVMe registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit NVMe registers, similarly as it is done in Linux kernel. This patch fixes operation of NVMe devices on RPi4 Broadcom BCM2711 SoC based board, where the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. nvme_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail probing. This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq"). Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Cc: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch> --- drivers/nvme/nvme.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h index 0e8cb221a7..aa4b3bac67 100644 --- a/drivers/nvme/nvme.h +++ b/drivers/nvme/nvme.h @@ -535,28 +535,20 @@ struct nvme_completion { */ static inline u64 nvme_readq(__le64 volatile *regs) { -#if BITS_PER_LONG == 64 - return readq(regs); -#else __u32 *ptr = (__u32 *)regs; u64 val_lo = readl(ptr); u64 val_hi = readl(ptr + 1); return val_lo + (val_hi << 32); -#endif } static inline void nvme_writeq(const u64 val, __le64 volatile *regs) { -#if BITS_PER_LONG == 64 - writeq(val, regs); -#else __u32 *ptr = (__u32 *)regs; u32 val_lo = lower_32_bits(val); u32 val_hi = upper_32_bits(val); writel(val_lo, ptr); writel(val_hi, ptr + 1); -#endif } struct nvme_bar { From 51549711b5960f2280629fe6231a07338bbcd57c Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt <xypron.glpk@gmx.de> Date: Wed, 30 Dec 2020 17:55:22 +0100 Subject: [PATCH 218/222] doc: android/boot-image: invalid C declaration make htmldocs results in an error: doc/android/boot-image.rst:33: WARNING: Unparseable C cross-reference: 'struct andr_img_hdr' Invalid C declaration: Expected identifier in nested name, got keyword: struct [error at 6] Follow the style prescribed in https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#highlights-and-cross-references Add missing definite article. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- doc/android/boot-image.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/doc/android/boot-image.rst b/doc/android/boot-image.rst index 195da688f4..fa8f2a47ee 100644 --- a/doc/android/boot-image.rst +++ b/doc/android/boot-image.rst @@ -30,9 +30,10 @@ next image headers: v2, v1 and v0 formats are backward compatible. -Android Boot Image format is represented by :c:type:`struct andr_img_hdr` in -U-Boot, and can be seen in ``include/android_image.h``. U-Boot supports booting -Android Boot Image and also has associated command +The Android Boot Image format is represented by +:c:type:`struct andr_img_hdr <andr_img_hdr>` in U-Boot, and can be seen in +``include/android_image.h``. U-Boot supports booting Android Boot Image and also +has associated command Booting ------- From 19408a397cc634672a405f6235f65a718fc8e14c Mon Sep 17 00:00:00 2001 From: Igor Opaniuk <igor.opaniuk@gmail.com> Date: Wed, 30 Dec 2020 19:25:47 +0200 Subject: [PATCH 219/222] mailmap: Update mail address for Igor Opaniuk My address at Toradex doesn't exist anymore, map this address to my personal email. Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index 33001f1e01..b76f02283c 100644 --- a/.mailmap +++ b/.mailmap @@ -30,6 +30,7 @@ Jagan Teki <jaganna@xilinx.com> Jagan Teki <jagannadh.teki@gmail.com> Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org> +Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com> Markus Klotzbuecher <mk@denx.de> Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com> Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com> From 1639988fa4c0049e6580dc781fe9bb2c94258c02 Mon Sep 17 00:00:00 2001 From: Philippe Reynes <philippe.reynes@softathome.com> Date: Wed, 23 Dec 2020 15:33:07 +0100 Subject: [PATCH 220/222] cmd: ubi: don't allow to rename a volume to a name that already exist This commits add a check on the command ubi rename. This check avoids to rename a volume to with a name that is already used on another ubi volume. If two volumes has the same name, then the ubi device can't be mounted anymore. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> --- cmd/ubi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cmd/ubi.c b/cmd/ubi.c index 171377cc66..cb14e3e1e7 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -264,6 +264,11 @@ static int ubi_rename_vol(char *oldname, char *newname) return ENODEV; } + if (!ubi_check(newname)) { + printf("%s: volume %s already exist\n", __func__, newname); + return EINVAL; + } + printf("Rename UBI volume %s to %s\n", oldname, newname); if (ubi->ro_mode) { From acff02c6dd05740ba5fbfaa6e2dd87c01b5c3257 Mon Sep 17 00:00:00 2001 From: Marc Ferland <ferlandm@amotus.ca> Date: Wed, 23 Dec 2020 10:13:22 -0500 Subject: [PATCH 221/222] cosmetic: fix typo in drivers/usb/Kconfig This commit fixes a simple typo: sPL --> SPL. Signed-off-by: Marc Ferland <ferlandm@amotus.ca> --- drivers/usb/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index fedc0134f5..6e291198ab 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -60,7 +60,7 @@ config DM_USB_GADGET mode) config SPL_DM_USB_GADGET - bool "Enable driver model for USB Gadget in sPL" + bool "Enable driver model for USB Gadget in SPL" depends on SPL_DM_USB help Enable driver model for USB Gadget in SPL From 62b07b5173e3d04fabfac42cf1f4779d021f94ad Mon Sep 17 00:00:00 2001 From: Tom Rini <trini@konsulko.com> Date: Tue, 5 Jan 2021 07:30:39 -0500 Subject: [PATCH 222/222] Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 679e4a603a..3ee4cc00dd 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2021 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION*