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https://github.com/brain-hackers/u-boot-brain
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ARM: dts: stm32: Sync DT files with v4.20 kernel for stm32f4
Synchronize stm32f7 device tree with kernel v4.20. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard
parent
933f84cab9
commit
71dfd5f3f5
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@ -1,6 +1,5 @@
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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@ -342,12 +341,12 @@
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sdio_pins: sdio_pins@0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>,
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<STM32_PINMUX('C', 9, AF12)>,
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<STM32_PINMUX('C', 10, AF12)>,
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<STM32_PINMUX('c', 11, AF12)>,
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<STM32_PINMUX('C', 12, AF12)>,
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<STM32_PINMUX('D', 2, AF12)>;
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
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<STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
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<STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
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drive-push-pull;
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slew-rate = <2>;
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};
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@ -355,17 +354,17 @@
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sdio_pins_od: sdio_pins_od@0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>,
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<STM32_PINMUX('C', 9, AF12)>,
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<STM32_PINMUX('C', 10, AF12)>,
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<STM32_PINMUX('C', 11, AF12)>,
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<STM32_PINMUX('C', 12, AF12)>;
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
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<STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 2, AF12)>;
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
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drive-open-drain;
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slew-rate = <2>;
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};
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@ -1,6 +1,5 @@
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/*
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* Copyright (C) 2015, STMicroelectronics - All Rights Reserved
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* Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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@ -76,6 +75,7 @@
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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button@0 {
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@ -1,6 +1,5 @@
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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@ -1,6 +1,5 @@
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/*
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* Copyright (C) 2015, STMicroelectronics - All Rights Reserved
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* Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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@ -259,6 +258,7 @@
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};
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timers13: timers@40001c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001C00 0x400>;
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@ -273,6 +273,7 @@
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};
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timers14: timers@40002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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@ -296,7 +297,7 @@
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interrupt-parent = <&exti>;
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interrupts = <17 1>;
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interrupt-names = "alarm";
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st,syscfg = <&pwrcfg>;
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st,syscfg = <&pwrcfg 0x00 0x100>;
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status = "disabled";
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};
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@ -304,6 +305,7 @@
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compatible = "st,stm32-iwdg";
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reg = <0x40003000 0x400>;
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clocks = <&clk_lsi>;
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clock-names = "lsi";
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status = "disabled";
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};
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@ -505,6 +507,17 @@
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};
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};
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sdio: sdio@40012c00 {
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compatible = "arm,pl180", "arm,primecell";
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arm,primecell-periphid = <0x00880180>;
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reg = <0x40012c00 0x400>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
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clock-names = "apb_pclk";
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interrupts = <49>;
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max-frequency = <48000000>;
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status = "disabled";
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};
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syscfg: system-config@40013800 {
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compatible = "syscon";
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reg = <0x40013800 0x400>;
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@ -540,6 +553,7 @@
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};
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timers10: timers@40014400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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@ -554,6 +568,7 @@
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};
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timers11: timers@40014800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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@ -572,18 +587,6 @@
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reg = <0x40007000 0x400>;
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};
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sdio: sdio@40012c00 {
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compatible = "st,stm32f4xx-sdio";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc 0 171>;
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interrupts = <49>;
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status = "disabled";
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pinctrl-0 = <&sdio_pins>;
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pinctrl-1 = <&sdio_pins_od>;
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pinctrl-names = "default", "opendrain";
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max-frequency = <48000000>;
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};
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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reg = <0x40016800 0x200>;
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@ -41,8 +41,10 @@
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*/
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/dts-v1/;
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#include "stm32f429.dtsi"
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#include "stm32f469.dtsi"
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#include "stm32f469-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "STMicroelectronics STM32F469i-DISCO board";
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@ -72,11 +74,40 @@
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dma-ranges = <0xc0000000 0x0 0x10000000>;
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};
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leds {
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compatible = "gpio-leds";
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green {
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gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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orange {
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gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
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};
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red {
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gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
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};
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blue {
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gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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button@0 {
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label = "User";
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linux,code = <KEY_WAKEUP>;
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gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
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};
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};
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/* This turns on vbus for otg for host mode (dwc2) */
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vcc5v_otg: vcc5v-otg-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpiob 2 0>;
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gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
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regulator-name = "vcc5_host1";
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regulator-always-on;
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};
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@ -90,6 +121,55 @@
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clock-frequency = <8000000>;
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};
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&dsi {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi_in: endpoint {
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remote-endpoint = <<dc_out_dsi>;
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};
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};
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port@1 {
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reg = <1>;
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dsi_out: endpoint {
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remote-endpoint = <&dsi_panel_in>;
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};
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};
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};
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panel-dsi@0 {
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compatible = "orisetech,otm8009a";
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reg = <0>; /* dsi virtual channel (0..3) */
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reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
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status = "okay";
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port {
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dsi_panel_in: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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};
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};
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<dc {
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dma-ranges;
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status = "okay";
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port {
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ltdc_out_dsi: endpoint@0 {
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remote-endpoint = <&dsi_in>;
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};
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};
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};
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&rtc {
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status = "okay";
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};
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@ -125,6 +205,8 @@
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&sdio {
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status = "okay";
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vmmc-supply = <&mmc_vcard>;
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cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
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broken-cd;
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pinctrl-names = "default", "opendrain";
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pinctrl-0 = <&sdio_pins>;
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pinctrl-1 = <&sdio_pins_od>;
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@ -1,6 +1,5 @@
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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19
arch/arm/dts/stm32f469.dtsi
Normal file
19
arch/arm/dts/stm32f469.dtsi
Normal file
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
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#include "stm32f429.dtsi"
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/ {
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soc {
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dsi: dsi@40016c00 {
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compatible = "st,stm32-dsi";
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reg = <0x40016c00 0x800>;
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interrupts = <92>;
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resets = <&rcc STM32F4_APB2_RESET(DSI)>;
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reset-names = "apb";
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clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
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clock-names = "pclk", "ref";
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status = "disabled";
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};
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};
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};
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@ -33,11 +33,12 @@
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#define CLK_SAI2 11
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#define CLK_I2SQ_PDIV 12
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#define CLK_SAIQ_PDIV 13
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#define END_PRIMARY_CLK 14
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#define CLK_HSI 14
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#define CLK_SYSCLK 15
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#define CLK_F469_DSI 16
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#define END_PRIMARY_CLK 17
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#define CLK_HDMI_CEC 16
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#define CLK_SPDIF 17
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#define CLK_USART1 18
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