mpc83xx: Migrate CONFIG_SYS_IMMR to Kconfig

Migrate CONFIG_SYS_IMMR to Kconfig for MPC83xx.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2019-01-21 09:18:10 +01:00
parent be5abb0a83
commit 71da747431
33 changed files with 9 additions and 121 deletions

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@ -282,6 +282,13 @@ config ARCH_MPC837X
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C_SUPPORT
config SYS_IMMR
hex "Value for IMMR"
default 0xE0000000
help
Address for the Internal Memory-Mapped Registers (IMMR) window used
to configure the features of the SoC.
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"

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@ -4,6 +4,7 @@ CONFIG_SYS_CLK_FREQ=66666000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_TQM834X=y
CONFIG_SYS_IMMR=0xff400000
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y

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@ -4,6 +4,7 @@ CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_IDS8313=y
CONFIG_SYS_IMMR=0xF0000000
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y

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@ -52,11 +52,6 @@
SICRL_I2C2_PF0 |\
SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* SERDES
*/

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@ -54,8 +54,6 @@
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
#define CONFIG_SYS_IMMR 0xE0000000
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif

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@ -30,8 +30,6 @@
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07f00000

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@ -31,11 +31,6 @@
#define CONFIG_HWCONFIG
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Arbiter Setup
*/

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@ -20,11 +20,6 @@
*/
#define CONFIG_SYS_SICRL 0x00000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* System performance
*/

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@ -17,11 +17,6 @@
*/
#define CONFIG_SYS_SICRL 0x00000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* DDR Setup
*/

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@ -17,8 +17,6 @@
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000

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@ -17,8 +17,6 @@
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000

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@ -39,11 +39,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
#define CONFIG_MISC_INIT_F
/*

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@ -39,11 +39,6 @@
#define CONFIG_HWCONFIG
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* DDR Setup
*/

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@ -46,11 +46,6 @@
*/
#define CONFIG_SYS_OBIR 0x30100000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Device configurations
*/

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@ -16,9 +16,6 @@
*/
#define CONFIG_E300 1 /* E300 Family */
/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR 0xff400000
/*
* Local Bus LCRR
* LCRR: DLL bypass, Clock divider is 8

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@ -25,8 +25,6 @@
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000

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@ -40,11 +40,6 @@
SICRL_I2C2_PF0 |\
SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* SERDES
*/

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@ -20,8 +20,6 @@
#define CONFIG_BOOT_RETRY_MIN 30
#define CONFIG_RESET_TO_RETRY
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */

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@ -40,11 +40,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -25,11 +25,6 @@
#include "km/keymile-common.h"
#include "km/km-powerpc.h"
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -45,11 +45,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -45,11 +45,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -52,11 +52,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -45,11 +45,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -44,11 +44,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -55,11 +55,6 @@
*/
#define CONFIG_SYS_GPIO1_DAT 0x08008C00
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* SERDES
*/

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@ -22,8 +22,6 @@
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000

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@ -40,11 +40,6 @@
SICRL_I2C2_PF0 |\
SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* SERDES
*/

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@ -42,11 +42,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -45,11 +45,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -45,11 +45,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/

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@ -24,8 +24,6 @@
* On-board devices
*
*/
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07000000

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@ -25,8 +25,6 @@
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000