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Cleanup

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This commit is contained in:
Wolfgang Denk 2005-09-25 18:49:35 +02:00
parent 49a7581c6c
commit 716c1dcb41
10 changed files with 197 additions and 211 deletions
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1
board/omap2420h4/sys_info.c
View File

@ -385,4 +385,3 @@ u32 get_device_type(void)
mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
return(mode >>= 8);
}

7
include/configs/MPC8260ADS.h
View File

@ -55,7 +55,6 @@
# define CFG_LOWBOOT 1
#endif
/* ADS flavours */
#define CFG_8260ADS 1 /* MPC8260ADS */
#define CFG_8266ADS 2 /* MPC8266ADS */
@ -185,7 +184,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
#ifndef CONFIG_SDRAM_PBI
#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
#endif
@ -334,7 +332,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#ifdef CFG_LOWBOOT
/* PQ2FADS flash HRCW = 0x0EB4B645 */
#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
@ -386,13 +383,11 @@
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
@ -461,8 +456,6 @@
* these windows.
*/
/*
* Master window that allows the CPU to access PCI Memory (prefetch).
* This window will be setup with the second set of Outbound ATU registers

1
include/configs/integratorap.h
View File

@ -314,4 +314,3 @@
* - PLL BYPASS b00
*/
#endif /* __CONFIG_H */

7
include/configs/omap2420h4.h
View File

@ -40,7 +40,7 @@
/* Clock config to target*/
#define PRCM_CONFIG_II 1
//#define PRCM_CONFIG_III 1
/* #define PRCM_CONFIG_III 1 */
#include <asm/arch/omap2420.h> /* get chip and board defs */
@ -157,7 +157,6 @@
#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
@ -165,7 +164,6 @@
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS
@ -261,9 +259,6 @@
#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
#endif
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/