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https://github.com/brain-hackers/u-boot-brain
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ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2
Factor out common code from rw_mgr_mem_calibrate_writes_center() and rw_mgr_mem_calibrate_vfifo_center() for searching for the left edge of the window. The code is almost identical, so pull it into separate function and cater for the minor differences. Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
parent
c4907898a1
commit
71120773bf
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@ -1780,6 +1780,145 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
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return ret;
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}
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/**
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* search_left_edge() - Find left edge of DQ/DQS working phase
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* @write: Perform read (Stage 2) or write (Stage 3) calibration
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* @rank_bgn: Rank number
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* @write_group: Write Group
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* @read_group: Read Group
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* @test_bgn: Rank number to begin the test
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* @bit_chk: Resulting bit mask after the test
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* @sticky_bit_chk: Resulting sticky bit mask after the test
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* @left_edge: Left edge of the DQ/DQS phase
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* @right_edge: Right edge of the DQ/DQS phase
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* @use_read_test: Perform read test
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*
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* Find left edge of DQ/DQS working phase.
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*/
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static void search_left_edge(const int write, const int rank_bgn,
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const u32 write_group, const u32 read_group, const u32 test_bgn,
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u32 *bit_chk, u32 *sticky_bit_chk,
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int *left_edge, int *right_edge, const u32 use_read_test)
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{
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const u32 correct_mask = write ? param->write_correct_mask :
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param->read_correct_mask;
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const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
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const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
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const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
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RW_MGR_MEM_DQ_PER_READ_DQS;
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u32 stop;
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int i, d;
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for (d = 0; d <= dqs_max; d++) {
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if (write)
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scc_mgr_apply_group_dq_out1_delay(d);
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else
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scc_mgr_apply_group_dq_in_delay(test_bgn, d);
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writel(0, &sdr_scc_mgr->update);
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/*
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* Stop searching when the read test doesn't pass AND when
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* we've seen a passing read on every bit.
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*/
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if (write) { /* WRITE-ONLY */
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stop = !rw_mgr_mem_calibrate_write_test(rank_bgn,
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write_group,
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0, PASS_ONE_BIT,
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bit_chk, 0);
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} else if (use_read_test) { /* READ-ONLY */
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stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
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read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
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bit_chk, 0, 0);
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} else { /* READ-ONLY */
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rw_mgr_mem_calibrate_write_test(rank_bgn,
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write_group,
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0, PASS_ONE_BIT,
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bit_chk, 0);
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*bit_chk = *bit_chk >> (per_dqs *
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(read_group - (write_group *
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RW_MGR_MEM_IF_READ_DQS_WIDTH /
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
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stop = (*bit_chk == 0);
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}
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*sticky_bit_chk = *sticky_bit_chk | *bit_chk;
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stop = stop && (*sticky_bit_chk == correct_mask);
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debug_cond(DLEVEL == 2,
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"%s:%d center(left): dtap=%u => %u == %u && %u", __func__, __LINE__, d,
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*sticky_bit_chk, correct_mask, stop);
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if (stop == 1)
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break;
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/* stop != 1 */
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for (i = 0; i < per_dqs; i++) {
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if (*bit_chk & 1) {
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/*
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* Remember a passing test as
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* the left_edge.
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*/
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left_edge[i] = d;
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} else {
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/*
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* If a left edge has not been seen
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* yet, then a future passing test
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* will mark this edge as the right
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* edge.
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*/
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if (left_edge[i] == delay_max + 1)
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right_edge[i] = -(d + 1);
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}
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*bit_chk = *bit_chk >> 1;
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}
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}
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/* Reset DQ delay chains to 0 */
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if (write)
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scc_mgr_apply_group_dq_out1_delay(0);
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else
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scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
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*sticky_bit_chk = 0;
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for (i = per_dqs - 1; i >= 0; i--) {
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debug_cond(DLEVEL == 2,
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"%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
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__func__, __LINE__, i, left_edge[i],
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i, right_edge[i]);
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/*
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* Check for cases where we haven't found the left edge,
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* which makes our assignment of the the right edge invalid.
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* Reset it to the illegal value.
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*/
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if ((left_edge[i] == delay_max + 1) &&
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(right_edge[i] != delay_max + 1)) {
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right_edge[i] = delay_max + 1;
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debug_cond(DLEVEL == 2,
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"%s:%d vfifo_center: reset right_edge[%u]: %d\n",
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__func__, __LINE__, i, right_edge[i]);
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}
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/*
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* Reset sticky bit
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* READ: except for bits where we have seen both
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* the left and right edge.
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* WRITE: except for bits where we have seen the
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* left edge.
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*/
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*sticky_bit_chk <<= 1;
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if (write) {
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if (left_edge[i] != delay_max + 1)
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*sticky_bit_chk |= 1;
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} else {
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if ((left_edge[i] != delay_max + 1) &&
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(right_edge[i] != delay_max + 1))
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*sticky_bit_chk |= 1;
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}
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}
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}
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/**
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* search_right_edge() - Find right edge of DQ/DQS working phase
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* @write: Perform read (Stage 2) or write (Stage 3) calibration
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@ -1945,7 +2084,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
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uint32_t use_read_test, uint32_t update_fom)
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{
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uint32_t i, p, d, min_index;
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uint32_t i, p, min_index;
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/*
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* Store these as signed since there are comparisons with
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* signed numbers.
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@ -1960,7 +2099,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
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final_dqs_en;
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int32_t dq_margin, dqs_margin;
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uint32_t stop;
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uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
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uint32_t addr;
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int ret;
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@ -1982,92 +2120,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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}
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/* Search for the left edge of the window for each bit */
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for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
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scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
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writel(0, &sdr_scc_mgr->update);
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/*
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* Stop searching when the read test doesn't pass AND when
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* we've seen a passing read on every bit.
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*/
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if (use_read_test) {
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stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
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read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
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&bit_chk, 0, 0);
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} else {
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rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
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0, PASS_ONE_BIT,
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&bit_chk, 0);
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bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
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(read_group - (write_group *
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RW_MGR_MEM_IF_READ_DQS_WIDTH /
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
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stop = (bit_chk == 0);
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}
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sticky_bit_chk = sticky_bit_chk | bit_chk;
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stop = stop && (sticky_bit_chk == param->read_correct_mask);
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debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
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&& %u", __func__, __LINE__, d,
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sticky_bit_chk,
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param->read_correct_mask, stop);
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if (stop == 1) {
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break;
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} else {
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for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
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if (bit_chk & 1) {
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/* Remember a passing test as the
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left_edge */
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left_edge[i] = d;
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} else {
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/* If a left edge has not been seen yet,
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then a future passing test will mark
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this edge as the right edge */
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if (left_edge[i] ==
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IO_IO_IN_DELAY_MAX + 1) {
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right_edge[i] = -(d + 1);
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}
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}
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bit_chk = bit_chk >> 1;
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}
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}
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}
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/* Reset DQ delay chains to 0 */
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scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
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sticky_bit_chk = 0;
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for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
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debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
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%d right_edge[%u]: %d\n", __func__, __LINE__,
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i, left_edge[i], i, right_edge[i]);
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/*
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* Check for cases where we haven't found the left edge,
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* which makes our assignment of the the right edge invalid.
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* Reset it to the illegal value.
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*/
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if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
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right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
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right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
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debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
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right_edge[%u]: %d\n", __func__, __LINE__,
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i, right_edge[i]);
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}
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/*
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* Reset sticky bit (except for bits where we have seen
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* both the left and right edge).
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*/
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sticky_bit_chk = sticky_bit_chk << 1;
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if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
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(right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
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sticky_bit_chk = sticky_bit_chk | 1;
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}
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if (i == 0)
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break;
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}
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search_left_edge(0, rank_bgn, write_group, read_group, test_bgn,
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&bit_chk, &sticky_bit_chk,
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left_edge, right_edge, use_read_test);
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/* Search for the right edge of the window for each bit */
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ret = search_right_edge(0, rank_bgn, write_group, read_group,
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@ -2792,7 +2847,6 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
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int32_t mid_min, orig_mid_min;
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int32_t new_dqs, start_dqs, shift_dq;
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int32_t dq_margin, dqs_margin, dm_margin;
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uint32_t stop;
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uint32_t temp_dq_out1_delay;
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uint32_t addr;
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@ -2819,87 +2873,9 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
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}
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/* Search for the left edge of the window for each bit */
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for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
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scc_mgr_apply_group_dq_out1_delay(write_group, d);
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writel(0, &sdr_scc_mgr->update);
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/*
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* Stop searching when the read test doesn't pass AND when
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* we've seen a passing read on every bit.
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*/
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stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
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0, PASS_ONE_BIT, &bit_chk, 0);
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sticky_bit_chk = sticky_bit_chk | bit_chk;
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stop = stop && (sticky_bit_chk == param->write_correct_mask);
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debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
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== %u && %u [bit_chk= %u ]\n",
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d, sticky_bit_chk, param->write_correct_mask,
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stop, bit_chk);
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if (stop == 1) {
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break;
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} else {
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for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
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if (bit_chk & 1) {
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/*
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* Remember a passing test as the
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* left_edge.
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*/
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left_edge[i] = d;
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} else {
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/*
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* If a left edge has not been seen
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* yet, then a future passing test will
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* mark this edge as the right edge.
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*/
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if (left_edge[i] ==
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IO_IO_OUT1_DELAY_MAX + 1) {
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right_edge[i] = -(d + 1);
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}
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}
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debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
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debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
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(int)(bit_chk & 1), i, left_edge[i]);
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debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
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right_edge[i]);
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bit_chk = bit_chk >> 1;
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}
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}
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}
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/* Reset DQ delay chains to 0 */
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scc_mgr_apply_group_dq_out1_delay(0);
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sticky_bit_chk = 0;
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for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
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debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
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%d right_edge[%u]: %d\n", __func__, __LINE__,
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i, left_edge[i], i, right_edge[i]);
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/*
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* Check for cases where we haven't found the left edge,
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* which makes our assignment of the the right edge invalid.
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* Reset it to the illegal value.
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*/
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if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
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(right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
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right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
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debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
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right_edge[%u]: %d\n", __func__, __LINE__,
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i, right_edge[i]);
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}
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/*
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* Reset sticky bit (except for bits where we have
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* seen the left edge).
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*/
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sticky_bit_chk = sticky_bit_chk << 1;
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if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
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sticky_bit_chk = sticky_bit_chk | 1;
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if (i == 0)
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break;
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}
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search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
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&bit_chk, &sticky_bit_chk,
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left_edge, right_edge, 0);
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/* Search for the right edge of the window for each bit */
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ret = search_right_edge(1, rank_bgn, write_group, 0,
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