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armv8/ls1043ardb: add USB support
Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@ -30,9 +30,9 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
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#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
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#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
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#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
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#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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@ -69,7 +69,23 @@ int dram_init(void)
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 usb_pwrfault;
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fsl_lsch2_early_init_f();
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fsl_lsch2_early_init_f();
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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out_be32(&scfg->rcwpmuxcr0, 0x3333);
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out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
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usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB3_SHIFT) |
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(SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB2_SHIFT) |
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(SCFG_USBPWRFAULT_SHARED <<
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SCFG_USBPWRFAULT_USB1_SHIFT);
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out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
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#endif
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return 0;
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return 0;
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}
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}
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@ -278,4 +278,17 @@
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#define CONFIG_ETHPRIME "FM1@DTSEC3"
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#define CONFIG_ETHPRIME "FM1@DTSEC3"
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#endif
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#endif
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/* USB */
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#define CONFIG_HAS_FSL_XHCI_USB
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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#define CONFIG_USB_XHCI
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#define CONFIG_USB_XHCI_FSL
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#define CONFIG_CMD_USB
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#define CONFIG_USB_STORAGE
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#define CONFIG_CMD_EXT2
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#endif
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#endif /* __LS1043ARDB_H__ */
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#endif /* __LS1043ARDB_H__ */
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@ -54,11 +54,18 @@ struct fsl_xhci {
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#if defined(CONFIG_LS102XA)
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#if defined(CONFIG_LS102XA)
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
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#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
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#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
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#elif defined(CONFIG_LS1043A)
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
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#endif
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#endif
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#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
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#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
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CONFIG_SYS_FSL_XHCI_USB2_ADDR}
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CONFIG_SYS_FSL_XHCI_USB2_ADDR, \
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CONFIG_SYS_FSL_XHCI_USB3_ADDR}
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#endif /* _ASM_ARCH_XHCI_FSL_H_ */
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#endif /* _ASM_ARCH_XHCI_FSL_H_ */
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