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Fix two bugs for MPC83xx DDR2 controller SPD Init
There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1.
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@ -58,8 +58,8 @@ picos_to_clk(int picos)
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int clks;
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ddr_bus_clk = gd->ddr_clk >> 1;
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clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
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if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
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clks = picos / (1000000000 / (ddr_bus_clk / 1000));
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if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
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clks++;
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return clks;
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@ -624,7 +624,7 @@ long int spd_sdram()
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| (1 << (16 + 10)) /* DQS Differential disable */
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| (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
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| (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
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| ((twr_clk >> 1) << 9) /* Write Recovery Autopre */
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| ((twr_clk - 1) << 9) /* Write Recovery Autopre */
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| (caslat << 4) /* caslat */
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| (burstlen << 0) /* Burst length */
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);
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