brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

x86: pci: Allow configuration before relocation

Browse Source 
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2014-11-12 22:42:14 -07:00
parent 6e5b12b614
commit 6fb3b72e87
2 changed files with 63 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
arch/x86/cpu/pci.c
View File

@ -46,3 +46,53 @@ void pci_init_board(void)
hose->last_busno = pci_hose_scan(hose);
}
static struct pci_controller *get_hose(void)
{
if (gd->arch.hose)
return gd->arch.hose;
return pci_bus_to_hose(0);
}
unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
{
uint8_t value;
pci_hose_read_config_byte(get_hose(), dev, where, &value);
return value;
}
unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
{
uint16_t value;
pci_hose_read_config_word(get_hose(), dev, where, &value);
return value;
}
unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
{
uint32_t value;
pci_hose_read_config_dword(get_hose(), dev, where, &value);
return value;
}
void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
{
pci_hose_write_config_byte(get_hose(), dev, where, value);
}
void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
{
pci_hose_write_config_word(get_hose(), dev, where, value);
}
void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
{
pci_hose_write_config_dword(get_hose(), dev, where, value);
}

13
arch/x86/include/asm/pci.h
View File

@ -33,4 +33,17 @@ void board_pci_setup_hose(struct pci_controller *hose);
* later use, but will become invalid one DRAM is available.
*/
int pci_early_init_hose(struct pci_controller **hosep);
/*
* Simple PCI access routines - these work from either the early PCI hose
* or the 'real' one, created after U-Boot has memory available
*/
unsigned int pci_read_config8(pci_dev_t dev, unsigned where);
unsigned int pci_read_config16(pci_dev_t dev, unsigned where);
unsigned int pci_read_config32(pci_dev_t dev, unsigned where);
void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
#endif