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dm: Sort the uclass id in alphabetical order
Some uclass ids are out of order. Per the comments, sort them in alphabetical order. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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@ -33,7 +33,6 @@ enum uclass_id {
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UCLASS_CROS_EC, /* Chrome OS EC */
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UCLASS_CROS_EC, /* Chrome OS EC */
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UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
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UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
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UCLASS_DMA, /* Direct Memory Access */
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UCLASS_DMA, /* Direct Memory Access */
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UCLASS_RAM, /* RAM controller */
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UCLASS_ETH, /* Ethernet device */
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UCLASS_ETH, /* Ethernet device */
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UCLASS_GPIO, /* Bank of general-purpose I/O pins */
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UCLASS_GPIO, /* Bank of general-purpose I/O pins */
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UCLASS_I2C, /* I2C bus */
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UCLASS_I2C, /* I2C bus */
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@ -56,11 +55,12 @@ enum uclass_id {
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
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UCLASS_PINCONFIG, /* Pin configuration node device */
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UCLASS_PINCONFIG, /* Pin configuration node device */
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UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
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UCLASS_PMIC, /* PMIC I/O device */
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UCLASS_PMIC, /* PMIC I/O device */
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UCLASS_PWM, /* Pulse-width modulator */
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UCLASS_PWM, /* Pulse-width modulator */
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UCLASS_PWRSEQ, /* Power sequence device */
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UCLASS_PWRSEQ, /* Power sequence device */
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UCLASS_RAM, /* RAM controller */
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UCLASS_REGULATOR, /* Regulator device */
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UCLASS_REGULATOR, /* Regulator device */
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UCLASS_REMOTEPROC, /* Remote Processor device */
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UCLASS_REMOTEPROC, /* Remote Processor device */
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UCLASS_RESET, /* Reset controller device */
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UCLASS_RESET, /* Reset controller device */
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