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https://github.com/brain-hackers/u-boot-brain
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ppc4xx: Add new weak functions to support boardspecific DDR2 configuration
The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese <sr@denx.de>
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5743a9207a
commit
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@ -109,7 +109,7 @@
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/* Defines for the Read Cycle Delay test */
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/* Defines for the Read Cycle Delay test */
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#define NUMMEMTESTS 8
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#define NUMMEMTESTS 8
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#define NUMMEMWORDS 8
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#define NUMMEMWORDS 8
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#define NUMLOOPS 256 /* memory test loops */
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#define NUMLOOPS 64 /* memory test loops */
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#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
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#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
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@ -138,6 +138,26 @@ void __spd_ddr_init_hang (void)
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}
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}
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void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
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void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
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/*
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* To provide an interface for board specific config values in this common
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* DDR setup code, we implement he "weak" default functions here. They return
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* the default value back to the caller.
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*
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* Please see include/configs/yucca.h for an example fora board specific
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* implementation.
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*/
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u32 __ddr_wrdtr(u32 default_val)
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{
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return default_val;
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}
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u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
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u32 __ddr_clktr(u32 default_val)
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{
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return default_val;
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}
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u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
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/* Private Structure Definitions */
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/* Private Structure Definitions */
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@ -154,7 +174,6 @@ typedef enum ddr_cas_id {
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* Prototypes
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* Prototypes
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*-----------------------------------------------------------------------------*/
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*-----------------------------------------------------------------------------*/
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static unsigned long sdram_memsize(void);
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static unsigned long sdram_memsize(void);
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void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
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static void get_spd_info(unsigned long *dimm_populated,
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static void get_spd_info(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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unsigned long num_dimm_banks);
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@ -216,9 +235,7 @@ static void test(void);
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#else
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#else
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static void DQS_calibration_process(void);
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static void DQS_calibration_process(void);
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#endif
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#endif
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#if defined(DEBUG)
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static void ppc440sp_sdram_register_dump(void);
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static void ppc440sp_sdram_register_dump(void);
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#endif
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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void dcbz_area(u32 start_address, u32 num_bytes);
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void dcbz_area(u32 start_address, u32 num_bytes);
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void dflush(void);
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void dflush(void);
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@ -469,17 +486,14 @@ long int initdram(int board_type)
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*-----------------------------------------------------------------*/
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*-----------------------------------------------------------------*/
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mfsdram(SDRAM_WRDTR, val);
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mfsdram(SDRAM_WRDTR, val);
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mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
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mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
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(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
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ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
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/*------------------------------------------------------------------
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/*------------------------------------------------------------------
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* Set the SDRAM Clock Timing Register
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* Set the SDRAM Clock Timing Register
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*-----------------------------------------------------------------*/
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*-----------------------------------------------------------------*/
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mfsdram(SDRAM_CLKTR, val);
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mfsdram(SDRAM_CLKTR, val);
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#ifdef CFG_44x_DDR2_CKTR_180
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mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
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mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
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ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
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#else
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mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
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#endif
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/*------------------------------------------------------------------
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/*------------------------------------------------------------------
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* Program the BxCF registers.
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* Program the BxCF registers.
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@ -538,7 +552,12 @@ long int initdram(int board_type)
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dram_size = sdram_memsize();
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dram_size = sdram_memsize();
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/* and program tlb entries for this size (dynamic) */
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/* and program tlb entries for this size (dynamic) */
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program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
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/*
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* Program TLB entries with caches enabled, for best performace
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* while auto-calibrating and ECC generation
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*/
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program_tlb(0, 0, dram_size, 0);
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/*------------------------------------------------------------------
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/*------------------------------------------------------------------
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* DQS calibration.
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* DQS calibration.
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@ -549,12 +568,18 @@ long int initdram(int board_type)
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/*------------------------------------------------------------------
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/*------------------------------------------------------------------
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* If ecc is enabled, initialize the parity bits.
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* If ecc is enabled, initialize the parity bits.
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*-----------------------------------------------------------------*/
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*-----------------------------------------------------------------*/
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program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
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program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
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#endif
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#endif
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#ifdef DEBUG
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/*
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* Now after initialization (auto-calibration and ECC generation)
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* remove the TLB entries with caches enabled and program again with
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* desired cache functionality
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*/
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remove_tlb(0, dram_size);
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program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
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ppc440sp_sdram_register_dump();
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ppc440sp_sdram_register_dump();
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#endif
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return dram_size;
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return dram_size;
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}
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}
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@ -2703,6 +2728,7 @@ calibration_loop:
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printf("\nERROR: Cannot determine a common read delay for the "
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printf("\nERROR: Cannot determine a common read delay for the "
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"DIMM(s) installed.\n");
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"DIMM(s) installed.\n");
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debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
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debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
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ppc440sp_sdram_register_dump();
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spd_ddr_init_hang ();
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spd_ddr_init_hang ();
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}
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}
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@ -3028,5 +3054,9 @@ static void ppc440sp_sdram_register_dump(void)
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dcr_data = mfdcr(SDRAM_R3BAS);
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dcr_data = mfdcr(SDRAM_R3BAS);
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printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
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printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
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}
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}
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#else
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static void ppc440sp_sdram_register_dump(void)
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{
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}
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#endif
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#endif
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#endif /* CONFIG_SPD_EEPROM */
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#endif /* CONFIG_SPD_EEPROM */
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