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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
mxs: timrot: Add support to i.MX23
This patch add timer support to i.MX23 and complete bit fields and values on regs-timrot.h. Testet on imx23-olinuxino board. Signed-off-by: Fadil Berisha <f.koliqi@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Fadil Berisha
Stefano Babic
parent
36c7c9250d
commit
6ecd05d2f5
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@ -32,7 +32,11 @@
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#include <asm/arch/sys_proto.h>
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/* Maximum fixed count */
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#define TIMER_LOAD_VAL 0xffffffff
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#if defined(CONFIG_MX23)
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#define TIMER_LOAD_VAL 0xffff
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#elif defined(CONFIG_MX28)
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#define TIMER_LOAD_VAL 0xffffffff
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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@ -69,7 +73,11 @@ int timer_init(void)
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mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
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/* Set fixed_count to 0 */
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#if defined(CONFIG_MX23)
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writel(0, &timrot_regs->hw_timrot_timcount0);
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#elif defined(CONFIG_MX28)
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writel(0, &timrot_regs->hw_timrot_fixed_count0);
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#endif
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/* Set UPDATE bit and 1Khz frequency */
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writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
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@ -77,7 +85,11 @@ int timer_init(void)
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&timrot_regs->hw_timrot_timctrl0);
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/* Set fixed_count to maximal value */
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#if defined(CONFIG_MX23)
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writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
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#elif defined(CONFIG_MX28)
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writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
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#endif
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return 0;
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}
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@ -86,9 +98,16 @@ unsigned long long get_ticks(void)
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{
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struct mxs_timrot_regs *timrot_regs =
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(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
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uint32_t now;
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/* Current tick value */
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uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
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#if defined(CONFIG_MX23)
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/* Upper bits are the valid ones. */
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now = readl(&timrot_regs->hw_timrot_timcount0) >>
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TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
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#elif defined(CONFIG_MX28)
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now = readl(&timrot_regs->hw_timrot_running_count0);
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#endif
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if (lastdec >= now) {
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/*
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@ -31,6 +31,16 @@
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struct mxs_timrot_regs {
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mxs_reg_32(hw_timrot_rotctrl)
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mxs_reg_32(hw_timrot_rotcount)
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#if defined(CONFIG_MX23)
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mxs_reg_32(hw_timrot_timctrl0)
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mxs_reg_32(hw_timrot_timcount0)
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mxs_reg_32(hw_timrot_timctrl1)
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mxs_reg_32(hw_timrot_timcount1)
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mxs_reg_32(hw_timrot_timctrl2)
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mxs_reg_32(hw_timrot_timcount2)
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mxs_reg_32(hw_timrot_timctrl3)
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mxs_reg_32(hw_timrot_timcount3)
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#elif defined(CONFIG_MX28)
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mxs_reg_32(hw_timrot_timctrl0)
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mxs_reg_32(hw_timrot_running_count0)
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mxs_reg_32(hw_timrot_fixed_count0)
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@ -47,6 +57,7 @@ struct mxs_timrot_regs {
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mxs_reg_32(hw_timrot_running_count3)
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mxs_reg_32(hw_timrot_fixed_count3)
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mxs_reg_32(hw_timrot_match_count3)
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#endif
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mxs_reg_32(hw_timrot_version)
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};
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#endif
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@ -71,7 +82,11 @@ struct mxs_timrot_regs {
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#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10)
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#define TIMROT_ROTCTRL_POLARITY_B (1 << 9)
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#define TIMROT_ROTCTRL_POLARITY_A (1 << 8)
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#if defined(CONFIG_MX23)
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#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4)
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#elif defined(CONFIG_MX28)
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#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
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#endif
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#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
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#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
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@ -79,12 +94,21 @@ struct mxs_timrot_regs {
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#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4)
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#if defined(CONFIG_MX23)
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#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4)
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#elif defined(CONFIG_MX28)
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#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4)
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#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4)
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#endif
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#if defined(CONFIG_MX23)
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#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7
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#elif defined(CONFIG_MX28)
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#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf
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#endif
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#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0
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#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0
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#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1
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@ -92,18 +116,25 @@ struct mxs_timrot_regs {
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#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3
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#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4
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#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5
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#if defined(CONFIG_MX23)
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#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6
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#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7
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#elif defined(CONFIG_MX28)
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#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6
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#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7
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#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8
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#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9
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#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa
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#endif
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#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff
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#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0
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#define TIMROT_TIMCTRLn_IRQ (1 << 15)
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#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
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#if defined(CONFIG_MX28)
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#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11)
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#endif
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#define TIMROT_TIMCTRLn_POLARITY (1 << 8)
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#define TIMROT_TIMCTRLn_UPDATE (1 << 7)
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#define TIMROT_TIMCTRLn_RELOAD (1 << 6)
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@ -121,6 +152,15 @@ struct mxs_timrot_regs {
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#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3
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#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4
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#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5
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#if defined(CONFIG_MX23)
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#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6
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#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7
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#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8
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#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9
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#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa
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#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb
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#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc
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#elif defined(CONFIG_MX28)
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#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6
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#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7
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#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8
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@ -131,15 +171,28 @@ struct mxs_timrot_regs {
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#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd
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#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe
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#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf
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#endif
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#if defined(CONFIG_MX23)
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#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16)
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#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16
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#elif defined(CONFIG_MX28)
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#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff
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#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0
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#endif
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#if defined(CONFIG_MX23)
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#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff
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#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
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#elif defined(CONFIG_MX28)
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#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff
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#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
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#endif
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#if defined(CONFIG_MX28)
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#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff
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#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0
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#endif
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
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@ -149,6 +202,15 @@ struct mxs_timrot_regs {
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
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#if defined(CONFIG_MX23)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16)
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#elif defined(CONFIG_MX28)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
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@ -159,7 +221,46 @@ struct mxs_timrot_regs {
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
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#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
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#endif
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#if defined(CONFIG_MX23)
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#define TIMROT_TIMCTRL3_IRQ (1 << 15)
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#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14)
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#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10)
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#endif
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#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9)
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#if defined(CONFIG_MX23)
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#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8)
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#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8
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#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8)
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#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8)
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#define TIMROT_TIMCTRL3_UPDATE (1 << 7)
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#define TIMROT_TIMCTRL3_RELOAD (1 << 6)
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#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4)
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#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4
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#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4)
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#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4)
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#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4)
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#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4)
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#define TIMROT_TIMCTRL3_SELECT_MASK 0xf
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#define TIMROT_TIMCTRL3_SELECT_OFFSET 0
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#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0
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#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1
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#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2
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#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3
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#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4
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#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5
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#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6
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#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7
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#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8
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#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9
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#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa
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#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb
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#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc
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#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16)
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#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16
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#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff
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#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0
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#endif
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#define TIMROT_VERSION_MAJOR_MASK (0xff << 24)
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#define TIMROT_VERSION_MAJOR_OFFSET 24
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