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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-08 05:43:21 +09:00
sf: Fix look for the fastest read command
Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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6dd6e90e13
@ -23,13 +23,16 @@ enum spi_dual_flash {
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/* Enum list - Full read commands */
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/* Enum list - Full read commands */
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enum spi_read_cmds {
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enum spi_read_cmds {
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ARRAY_SLOW = 1 << 0,
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ARRAY_SLOW = 1 << 0,
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DUAL_OUTPUT_FAST = 1 << 1,
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ARRAY_FAST = 1 << 1,
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DUAL_IO_FAST = 1 << 2,
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DUAL_OUTPUT_FAST = 1 << 2,
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QUAD_OUTPUT_FAST = 1 << 3,
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DUAL_IO_FAST = 1 << 3,
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QUAD_IO_FAST = 1 << 4,
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QUAD_OUTPUT_FAST = 1 << 4,
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QUAD_IO_FAST = 1 << 5,
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};
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};
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#define RD_EXTN (ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
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/* Normal - Extended - Full command set */
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#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
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#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
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#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
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#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
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/* sf param flags */
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/* sf param flags */
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@ -15,42 +15,42 @@
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/* SPI/QSPI flash device params structure */
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/* SPI/QSPI flash device params structure */
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const struct spi_flash_params spi_flash_params_table[] = {
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const struct spi_flash_params spi_flash_params_table[] = {
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#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
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#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
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{"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
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{"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K},
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{"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
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{"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
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{"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
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{"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
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{"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
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{"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
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{"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
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{"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
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{"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
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{"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
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{"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
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{"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
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{"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
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#endif
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#endif
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#ifdef CONFIG_SPI_FLASH_EON /* EON */
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#ifdef CONFIG_SPI_FLASH_EON /* EON */
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{"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
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{"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0},
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{"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
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{"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
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{"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0},
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{"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
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{"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0},
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#endif
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#endif
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#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
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#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
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{"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
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{"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
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{"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
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#endif
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#endif
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#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
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#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
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{"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
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{"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
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{"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
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{"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},
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{"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
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{"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0},
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{"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
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{"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0},
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{"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
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{"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0},
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{"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
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{"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0},
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{"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
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{"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
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{"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
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{"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
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{"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
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{"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
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{"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
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{"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
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#endif
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#endif
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#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
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#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
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{"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
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{"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0},
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{"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
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{"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0},
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{"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
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{"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0},
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{"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
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{"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0},
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{"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
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{"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
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{"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
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{"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
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{"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
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{"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
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@ -64,17 +64,17 @@ const struct spi_flash_params spi_flash_params_table[] = {
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{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
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{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
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#endif
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#endif
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#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
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#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
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{"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
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{"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0},
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{"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
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{"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0},
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{"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
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{"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0},
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{"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
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{"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0},
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{"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
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{"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0},
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{"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0, 0},
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{"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0},
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{"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
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{"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
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{"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
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{"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0},
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{"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
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{"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0},
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{"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
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{"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0},
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{"M25PX64", 0x207117, 0x0, 64 * 1024, 128, 0, SECT_4K},
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{"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
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{"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
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{"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
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{"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
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{"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
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{"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
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@ -89,25 +89,25 @@ const struct spi_flash_params spi_flash_params_table[] = {
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{"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
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{"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
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#endif
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#endif
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#ifdef CONFIG_SPI_FLASH_SST /* SST */
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#ifdef CONFIG_SPI_FLASH_SST /* SST */
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{"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
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{"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
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{"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
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{"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
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{"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
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{"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
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{"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
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{"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
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{"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
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{"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
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{"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP},
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#endif
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#endif
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#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
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#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
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{"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
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{"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0},
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{"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
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{"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0},
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{"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
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{"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0},
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{"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
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{"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
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{"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
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{"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
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{"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
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{"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
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{"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
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{"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
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{"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
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{"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
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{"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
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{"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
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{"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
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@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
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/* Read commands array */
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/* Read commands array */
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static u8 spi_read_cmds_array[] = {
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static u8 spi_read_cmds_array[] = {
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CMD_READ_ARRAY_SLOW,
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CMD_READ_ARRAY_SLOW,
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CMD_READ_ARRAY_FAST,
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CMD_READ_DUAL_OUTPUT_FAST,
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CMD_READ_DUAL_OUTPUT_FAST,
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CMD_READ_DUAL_IO_FAST,
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CMD_READ_DUAL_IO_FAST,
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CMD_READ_QUAD_OUTPUT_FAST,
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CMD_READ_QUAD_OUTPUT_FAST,
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