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https://github.com/brain-hackers/u-boot-brain
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Add sync in do_reset() routine for MPC83xx after RPR register
was written to. It is need on some targets when BAT translation is enabled.
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@ -2,6 +2,10 @@
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Changes since U-Boot 1.1.4:
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Changes since U-Boot 1.1.4:
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======================================================================
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======================================================================
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* Add sync in do_reset() routine for MPC83xx after RPR register
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was written to. It is need on some targets when BAT translation
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is enabled.
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* Add bit definitions for MPC83xx DDR controller registers.
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* Add bit definitions for MPC83xx DDR controller registers.
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* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
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* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
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@ -93,6 +93,8 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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/* enable Reset Control Reg */
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/* enable Reset Control Reg */
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immap->reset.rpr = 0x52535445;
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immap->reset.rpr = 0x52535445;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* confirm Reset Control Reg is enabled */
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/* confirm Reset Control Reg is enabled */
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while(!((immap->reset.rcer) & RCER_CRE));
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while(!((immap->reset.rcer) & RCER_CRE));
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