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mx31: Introduce mx31_set_gpr function
Introduce mx31_set_gpr function for setting the GPR (General Purpose Register) on MX31. This function can be useful for setting a group of pins into tied to some specific peripherals. Reuse this function from the linux kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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@ -27,6 +27,8 @@
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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#define IOMUXGPR (IOMUXC_BASE + 0x008)
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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{
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{
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u32 mfi = GET_PLL_MFI(reg);
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u32 mfi = GET_PLL_MFI(reg);
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@ -141,6 +143,19 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
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}
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}
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void mx31_set_gpr(enum iomux_gp_func gp, char en)
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{
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u32 l;
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l = readl(IOMUXGPR);
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if (en)
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l |= gp;
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else
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l &= ~gp;
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writel(l, IOMUXGPR);
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}
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void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
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void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
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{
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{
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struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
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struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
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@ -37,6 +37,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk);
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extern u32 imx_get_uartclk(void);
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extern u32 imx_get_uartclk(void);
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extern void mx31_gpio_mux(unsigned long mode);
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extern void mx31_gpio_mux(unsigned long mode);
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extern void mx31_set_pad(enum iomux_pins pin, u32 config);
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extern void mx31_set_pad(enum iomux_pins pin, u32 config);
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extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
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void mx31_uart1_hw_init(void);
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void mx31_uart1_hw_init(void);
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void mx31_spi2_hw_init(void);
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void mx31_spi2_hw_init(void);
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@ -468,6 +468,44 @@ enum iomux_pins {
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MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
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MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
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};
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};
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/*
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* various IOMUX general purpose functions
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*/
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enum iomux_gp_func {
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MUX_PGP_FIRI = 1 << 0,
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MUX_DDR_MODE = 1 << 1,
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MUX_PGP_CSPI_BB = 1 << 2,
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MUX_PGP_ATA_1 = 1 << 3,
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MUX_PGP_ATA_2 = 1 << 4,
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MUX_PGP_ATA_3 = 1 << 5,
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MUX_PGP_ATA_4 = 1 << 6,
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MUX_PGP_ATA_5 = 1 << 7,
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MUX_PGP_ATA_6 = 1 << 8,
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MUX_PGP_ATA_7 = 1 << 9,
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MUX_PGP_ATA_8 = 1 << 10,
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MUX_PGP_UH2 = 1 << 11,
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MUX_SDCTL_CSD0_SEL = 1 << 12,
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MUX_SDCTL_CSD1_SEL = 1 << 13,
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MUX_CSPI1_UART3 = 1 << 14,
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MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
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MUX_TAMPER_DETECT_EN = 1 << 16,
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MUX_PGP_USB_4WIRE = 1 << 17,
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MUX_PGP_USB_COMMON = 1 << 18,
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MUX_SDHC_MEMSTICK1 = 1 << 19,
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MUX_SDHC_MEMSTICK2 = 1 << 20,
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MUX_PGP_SPLL_BYP = 1 << 21,
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MUX_PGP_UPLL_BYP = 1 << 22,
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MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
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MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
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MUX_CSPI3_UART5_SEL = 1 << 25,
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MUX_PGP_ATA_9 = 1 << 26,
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MUX_PGP_USB_SUSPEND = 1 << 27,
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MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
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MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
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MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
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MUX_CLKO_DDR_MODE = 1 << 31,
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};
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/* Bit definitions for RCSR register in CCM */
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/* Bit definitions for RCSR register in CCM */
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#define CCM_RCSR_NF16B (1 << 31)
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#define CCM_RCSR_NF16B (1 << 31)
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#define CCM_RCSR_NFMS (1 << 30)
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#define CCM_RCSR_NFMS (1 << 30)
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