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rockchip: Clarify docs on SPI writing
We use every second block when creating a SPI image, so update the text to say this explicitly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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@ -262,7 +262,7 @@ To write an image that boots from SPI flash (e.g. for the Haier Chromebook):
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dd if=out.bin of=out.bin.pad bs=4M conv=sync
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dd if=out.bin of=out.bin.pad bs=4M conv=sync
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This converts the SPL image to the required SPI format by adding the Rockchip
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This converts the SPL image to the required SPI format by adding the Rockchip
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header and skipping every 2KB block. Then the U-Boot image is written at
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header and skipping every second 2KB block. Then the U-Boot image is written at
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offset 128KB and the whole image is padded to 4MB which is the SPI flash size.
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offset 128KB and the whole image is padded to 4MB which is the SPI flash size.
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The position of U-Boot is controlled with this setting in U-Boot:
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The position of U-Boot is controlled with this setting in U-Boot:
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