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rockchip: Clarify docs on SPI writing

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We use every second block when creating a SPI image, so update the text to
say this explicitly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Simon Glass 2019-01-21 14:53:27 -07:00 committed by Philipp Tomsich
parent 60853a9b5c
commit 6cecc2b556
1 changed files with 1 additions and 1 deletions
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doc/README.rockchip
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@ -262,7 +262,7 @@ To write an image that boots from SPI flash (e.g. for the Haier Chromebook):
dd if=out.bin of=out.bin.pad bs=4M conv=sync
This converts the SPL image to the required SPI format by adding the Rockchip
header and skipping every 2KB block. Then the U-Boot image is written at
header and skipping every second 2KB block. Then the U-Boot image is written at
offset 128KB and the whole image is padded to 4MB which is the SPI flash size.
The position of U-Boot is controlled with this setting in U-Boot: