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https://github.com/brain-hackers/u-boot-brain
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wandboard: Add support for the MX6QP variant
Add support for the latest MX6QP wandboard variant. Based on Richard Hu's work from Technexion's U-Boot tree. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Fabio Estevam
Otavio Salvador
parent
46800a79b6
commit
6c94a45c23
@ -346,6 +346,9 @@
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#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
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#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
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#endif
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#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
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/* Only for i.MX6SX */
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#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
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#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
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@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define IMX6DQ_DRIVE_STRENGTH 0x30
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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#define IMX6QP_DRIVE_STRENGTH 0x28
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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@ -63,6 +64,36 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
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};
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/* configure MX6QP mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
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.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
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.dram_cas = IMX6QP_DRIVE_STRENGTH,
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.dram_ras = IMX6QP_DRIVE_STRENGTH,
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.dram_reset = IMX6QP_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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@ -81,6 +112,24 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
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};
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/* configure MX6QP mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6QP_DRIVE_STRENGTH,
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.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
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.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
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@ -260,15 +309,87 @@ static void ccgr_init(void)
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x3FF03000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static void spl_dram_init_imx6qp_lpddr3(void)
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{
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/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
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writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
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/* Calibrations - ZQ */
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writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
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/* write leveling */
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writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
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writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
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writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
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writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
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/*
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* DQS gating, read delay, write delay calibration values
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* based on calibration compare of 0x00ffff00
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*/
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writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
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writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
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writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
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writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
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writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
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writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
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writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
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writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
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writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
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writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
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writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
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writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
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writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
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writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
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/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
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writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
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writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
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writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
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writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
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writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
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writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
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writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
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writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
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writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
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writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
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writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
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writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
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writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
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/* add NOC DDR configuration */
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writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
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writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
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writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
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writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
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writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
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writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
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writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
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writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
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writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
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writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
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writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
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writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
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writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
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writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
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writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
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writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
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writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
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}
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static void spl_dram_init(void)
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{
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if (is_cpu_type(MXC_CPU_MX6SOLO)) {
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if (is_mx6dqp()) {
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mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
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spl_dram_init_imx6qp_lpddr3();
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} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
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mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
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mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
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} else if (is_cpu_type(MXC_CPU_MX6DL)) {
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@ -512,7 +512,9 @@ int board_late_init(void)
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#endif
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (is_mx6dq())
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if (is_mx6dqp())
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env_set("board_rev", "MX6QP");
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else if (is_mx6dq())
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env_set("board_rev", "MX6Q");
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else
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env_set("board_rev", "MX6DL");
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@ -534,7 +536,7 @@ int board_init(void)
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#if defined(CONFIG_VIDEO_IPUV3)
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
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if (is_mx6dq()) {
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if (is_mx6dq() || is_mx6dqp()) {
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
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} else {
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@ -109,6 +109,8 @@
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"fi; " \
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"fi\0" \
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"findfdt="\
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"if test $board_name = D1 && test $board_rev = MX6QP ; then " \
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"setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \
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"if test $board_name = D1 && test $board_rev = MX6Q ; then " \
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"setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \
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"if test $board_name = D1 && test $board_rev = MX6DL ; then " \
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