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armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@ -76,5 +76,15 @@ int arch_soc_init(void)
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SCFG_SNPCNFGCR_DBG_RD_WR |
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SCFG_SNPCNFGCR_DBG_RD_WR |
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SCFG_SNPCNFGCR_EDMA_SNP);
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SCFG_SNPCNFGCR_EDMA_SNP);
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/*
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* Memory controller require a register write before being enabled.
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* Affects: DDR
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* Register: EDDRTQCFG
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* Description: Memory controller performance is not optimal with
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* default internal target queue register values.
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* Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
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*/
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out_be32(&scfg->eddrtqcfg, 0x63b20042);
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return 0;
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return 0;
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}
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}
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@ -230,7 +230,7 @@ struct ccsr_scfg {
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u32 scfgrevcr;
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u32 scfgrevcr;
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u32 coresrencr;
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u32 coresrencr;
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u32 pex2pmrdsr;
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u32 pex2pmrdsr;
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u32 ddrc1cr;
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u32 eddrtqcfg;
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u32 ddrc2cr;
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u32 ddrc2cr;
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u32 ddrc3cr;
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u32 ddrc3cr;
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u32 ddrc4cr;
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u32 ddrc4cr;
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