mips: mtmips: add support for mt7628-rfb
This patch adds support for mt7628 reference board. SPL_DM and DT are not enabled for SPL to save about 17KiB for u-boot-spl.bin. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Daniel Schwierzeck
parent
757cbbe956
commit
6bd888b63b
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@ -17,6 +17,7 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
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dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
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dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
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dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
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dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
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dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
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dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
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dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
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@ -0,0 +1,67 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7628a.dtsi"
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/ {
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compatible = "mediatek,mt7628-rfb", "ralink,mt7628a-soc";
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model = "MediaTek MT7628 RFB";
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aliases {
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serial0 = &uart0;
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spi0 = &spi0;
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};
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chosen {
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stdout-path = &uart0;
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};
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};
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&pinctrl {
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state_default: pin_state {
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pleds {
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groups = "p0led", "p1led", "p2led", "p3led", "p4led";
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function = "led";
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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num-cs = <2>;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <25000000>;
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reg = <0>;
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};
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};
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ð {
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mediatek,wan-port = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&ephy_router_mode>;
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};
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&mmc {
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bus-width = <4>;
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cap-sd-highspeed;
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pinctrl-names = "default";
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pinctrl-0 = <&sd_router_mode>;
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status = "okay";
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};
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@ -79,6 +79,14 @@ config BOARD_LINKIT_SMART_7688
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ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
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a MT7688 (PCIe).
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config BOARD_MT7628_RFB
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bool "MediaTek MT7628 RFB"
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depends on SOC_MT7628
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help
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The reference design of MT7628. The board has 128 MiB DDR2, 8 MiB
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SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host,
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1 SDXC, 1 PCIe socket and JTAG pins.
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endchoice
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config SPL_UART2_SPIS_PINMUX
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@ -90,6 +98,7 @@ config SPL_UART2_SPIS_PINMUX
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(shared with SPIS) rather than the usual GPIO 20/21.
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source "board/gardena/smart-gateway-mt7688/Kconfig"
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source "board/mediatek/mt7628/Kconfig"
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source "board/seeed/linkit-smart-7688/Kconfig"
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endmenu
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@ -0,0 +1,12 @@
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if BOARD_MT7628_RFB
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config SYS_BOARD
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default "mt7628"
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config SYS_VENDOR
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default "mediatek"
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config SYS_CONFIG_NAME
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default "mt7628"
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endif
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@ -0,0 +1,7 @@
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MT7628_RFB BOARD
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M: Weijie Gao <weijie.gao@mediatek.com>
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S: Maintained
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F: board/mediatek/mt7628
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F: include/configs/mt7628.h
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F: configs/mt7628_rfb_defconfig
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F: arch/mips/dts/mediatek,mt7628-rfb.dts
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += board.o
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@ -0,0 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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@ -0,0 +1,47 @@
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CONFIG_MIPS=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x30000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL=y
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CONFIG_ARCH_MTMIPS=y
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CONFIG_BOARD_MT7628_RFB=y
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CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
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CONFIG_MIPS_BOOT_FDT=y
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CONFIG_FIT=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_NOR_SUPPORT=y
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_CRC32 is not set
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# CONFIG_CMD_DM is not set
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_SPI=y
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# CONFIG_CMD_NFS is not set
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# CONFIG_PARTITIONS is not set
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CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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# CONFIG_INPUT is not set
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_XMC=y
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CONFIG_MT7628_ETH=y
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# CONFIG_SPECIFY_CONSOLE_INDEX is not set
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CONFIG_SPI=y
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CONFIG_MT7621_SPI=y
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CONFIG_LZMA=y
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CONFIG_SPL_LZMA=y
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@ -0,0 +1,56 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef __CONFIG_MT7628_H
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#define __CONFIG_MT7628_H
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MALLOC_LEN 0x100000
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#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_LOAD_ADDR 0x80010000
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#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_CBSIZE 1024
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/* Serial SPL */
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SYS_NS16550_CLK 40000000
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 0xb0000c00
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#define CONFIG_CONS_INDEX 1
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#endif
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/* Serial common */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
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230400, 460800, 921600 }
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/* SPL */
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_BSS_START_ADDR 0x80010000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_PAD_TO 0
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/* Dummy value */
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#define CONFIG_SYS_UBOOT_BASE 0
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#endif /* __CONFIG_MT7628_H */
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