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clk: sandbox: Adjust clk-divider to emulate reading its value from HW

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The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Lukasz Majewski 2019-06-24 15:50:48 +02:00 committed by Stefano Babic
parent 4ab8e783f3
commit 6bb15d6f07
2 changed files with 12 additions and 1 deletions
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10
drivers/clk/clk-divider.c
View File

@ -74,7 +74,12 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned int val;
val = readl(divider->reg) >> divider->shift;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
val = divider->io_divider_val;
#else
val = readl(divider->reg);
#endif
val >>= divider->shift;
val &= clk_div_mask(divider->width);
return divider_recalc_rate(clk, parent_rate, val, divider->table,
@ -112,6 +117,9 @@ static struct clk *_register_divider(struct device *dev, const char *name,
div->width = width;
div->flags = clk_divider_flags;
div->table = table;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
div->io_divider_val = *(u32 *)reg;
#endif
/* register the clock */
clk = &div->clk;

3
include/linux/clk-provider.h
View File

@ -75,6 +75,9 @@ struct clk_divider {
u8 width;
u8 flags;
const struct clk_div_table *table;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
u32 io_divider_val;
#endif
};
#define clk_div_mask(width) ((1 << (width)) - 1)