brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

imx8m: update clock root and fix core_sel

Browse Source 
Update clock root table to let it be easy to configure clock at
very early stage. Also the core_sel mux parent should be A53 CLK
root and ARM PLL.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2020-04-22 10:55:56 +08:00 committed by Stefano Babic
parent a07bcec403
commit 6b87b3f4dc
2 changed files with 777 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
View File

@ -363,7 +363,8 @@ enum clk_root_src {
EXT_CLK_2,
EXT_CLK_3,
EXT_CLK_4,
OSC_HDMI_CLK
OSC_HDMI_CLK,
ARM_A53_ALT_CLK,
};
enum clk_ccgr_index {

785
arch/arm/mach-imx/imx8m/clock_slice.c
View File

@ -472,16 +472,36 @@ static struct clk_root_map root_array[] = {
{DRAM_PLL1_CLK}
},
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
{ARM_A53_ALT_CLK, ARM_PLL_CLK}
},
};
#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
#elif defined(CONFIG_IMX8MM)
static struct clk_root_map root_array[] = {
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
{OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
},
{ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
},
{VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
{OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
},
{GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
{OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
{OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
@ -497,18 +517,66 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
},
{VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
},
{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
{OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
EXT_CLK_1, EXT_CLK_4}
},
{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
EXT_CLK_1, EXT_CLK_3}
},
{DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
EXT_CLK_2, EXT_CLK_3}
},
{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
#ifdef CONFIG_IMX8MM
{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
#endif
{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
@ -519,6 +587,91 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
{OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
},
{VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
{OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
},
{DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
{OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
},
{DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
{OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
},
{PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
{OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
},
{PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
SYSTEM_PLL1_400M_CLK}
},
{PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
},
{DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
{OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
{OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
},
{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
},
{SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
},
{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
},
{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
},
{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
@ -534,6 +687,46 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
},
{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
},
{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
@ -554,19 +747,546 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
{OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
{OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
},
{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
},
{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
},
{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
},
{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
},
{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
},
{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
},
{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
},
{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
{OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
},
{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
},
{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
},
{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
{MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
{OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
},
{PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
},
{PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
},
{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
},
{VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
{OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
},
{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
},
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
{ARM_A53_ALT_CLK, ARM_PLL_CLK}
},
};
#elif defined(CONFIG_IMX8MN)
static struct clk_root_map root_array[] = {
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
{OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
},
{ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
},
{GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
{OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
{OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
},
{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
},
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
},
{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
{OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
EXT_CLK_1, EXT_CLK_4}
},
{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
EXT_CLK_1, EXT_CLK_3}
},
{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
},
{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{DISPLAY_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
{OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
},
{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
},
{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
},
{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
},
{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
VIDEO_PLL_CLK}
},
{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
{OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
},
{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
},
{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
{OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
{OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
},
{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
},
{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
},
{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
},
{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
},
{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
},
{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
},
{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
},
{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
{OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
},
{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
},
{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
},
{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{DISPLAY_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
{DISPLAY_CAMERA_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 58,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
},
{SAI7_CLK_ROOT, IP_CLOCK_SLICE, 70,
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
},
{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
},
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
{ARM_A53_ALT_CLK, ARM_PLL_CLK}
},
};
#elif defined(CONFIG_IMX8MP)
static struct clk_root_map root_array[] = {
@ -605,6 +1325,26 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
},
{MEDIA_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
{OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
},
{MEDIA_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
},
{HDMI_APB_CLK_ROOT, BUS_CLOCK_SLICE, 6,
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
},
{HDMI_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 7,
{OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
},
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
@ -630,6 +1370,11 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{MEDIA_DISP2_CLK_ROOT, AHB_CLOCK_SLICE, 3,
{OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
@ -640,11 +1385,6 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 6,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL1_133M_CLK}
},
{I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
@ -823,11 +1563,36 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
},
{HDMI_REF_266M_CLK_ROOT, IP_CLOCK_SLICE, 56,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_266M_CLK,
SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
{MEDIA_MIPI_PHY1_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MEDIA_DISP1_PIX_CLK_ROOT, IP_CLOCK_SLICE, 60,
{OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{MEDIA_LDB_CLK_ROOT, IP_CLOCK_SLICE, 62,
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 63,
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
@ -837,7 +1602,7 @@ static struct clk_root_map root_array[] = {
{DRAM_PLL1_CLK}
},
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
{ARM_A53_ALT_CLK, ARM_PLL_CLK}
},
};
#endif