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Blackfin: bfin_mac: set MDCDIV based on SCLK
Rather than hardcoding MDCDIV to 24 (which is correct for ~125mhz SCLK), use the real algorithm so it gets set correctly regardless of SCLK. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Ben Warren <biggerbadderben@gmail.com>
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@ -323,9 +323,12 @@ static void SoftResetPHY(void)
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}
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}
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#endif
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#endif
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/* MDC = SCLK / MDC_freq / 2 - 1 */
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#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
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static int SetupSystemRegs(int *opmode)
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static int SetupSystemRegs(int *opmode)
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{
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{
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u16 sysctl, phydat;
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u16 phydat;
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int count = 0;
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int count = 0;
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/* Enable PHY output */
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/* Enable PHY output */
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*pVR_CTL |= CLKBUFOE;
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*pVR_CTL |= CLKBUFOE;
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@ -368,12 +371,9 @@ static int SetupSystemRegs(int *opmode)
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# endif
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# endif
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#endif
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#endif
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/* MDC = 2.5 MHz */
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sysctl = SET_MDCDIV(24);
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/* Odd word alignment for Receive Frame DMA word */
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/* Odd word alignment for Receive Frame DMA word */
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/* Configure checksum support and rcve frame word alignment */
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/* Configure checksum support and rcve frame word alignment */
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sysctl |= RXDWA | RXCKS;
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*pEMAC_SYSCTL = RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(2500000));
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*pEMAC_SYSCTL = sysctl;
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/* auto negotiation on */
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/* auto negotiation on */
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/* full duplex */
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/* full duplex */
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/* 100 Mbps */
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/* 100 Mbps */
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